4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/linkage.h>
21 #include <asm/processor.h>
22 #include <asm/unistd.h>
23 #include <asm/thread_info.h>
24 #include <asm/errno.h>
25 #include <asm/spr_defs.h>
28 #include <asm/pgtable.h>
29 #include <asm/asm-offsets.h>
31 #define DISABLE_INTERRUPTS(t1,t2) \
32 l.mfspr t2,r0,SPR_SR ;\
33 l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
34 l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
38 #define ENABLE_INTERRUPTS(t1) \
39 l.mfspr t1,r0,SPR_SR ;\
40 l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\
43 /* =========================================================[ macros ]=== */
46 * We need to disable interrupts at beginning of RESTORE_ALL
47 * since interrupt might come in after we've loaded EPC return address
48 * and overwrite EPC with address somewhere in RESTORE_ALL
49 * which is of course wrong!
53 DISABLE_INTERRUPTS(r3,r4) ;\
55 l.mtspr r0,r3,SPR_EPCR_BASE ;\
57 l.mtspr r0,r3,SPR_ESR_BASE ;\
58 l.lwz r2,PT_GPR2(r1) ;\
59 l.lwz r3,PT_GPR3(r1) ;\
60 l.lwz r4,PT_GPR4(r1) ;\
61 l.lwz r5,PT_GPR5(r1) ;\
62 l.lwz r6,PT_GPR6(r1) ;\
63 l.lwz r7,PT_GPR7(r1) ;\
64 l.lwz r8,PT_GPR8(r1) ;\
65 l.lwz r9,PT_GPR9(r1) ;\
66 l.lwz r10,PT_GPR10(r1) ;\
67 l.lwz r11,PT_GPR11(r1) ;\
68 l.lwz r12,PT_GPR12(r1) ;\
69 l.lwz r13,PT_GPR13(r1) ;\
70 l.lwz r14,PT_GPR14(r1) ;\
71 l.lwz r15,PT_GPR15(r1) ;\
72 l.lwz r16,PT_GPR16(r1) ;\
73 l.lwz r17,PT_GPR17(r1) ;\
74 l.lwz r18,PT_GPR18(r1) ;\
75 l.lwz r19,PT_GPR19(r1) ;\
76 l.lwz r20,PT_GPR20(r1) ;\
77 l.lwz r21,PT_GPR21(r1) ;\
78 l.lwz r22,PT_GPR22(r1) ;\
79 l.lwz r23,PT_GPR23(r1) ;\
80 l.lwz r24,PT_GPR24(r1) ;\
81 l.lwz r25,PT_GPR25(r1) ;\
82 l.lwz r26,PT_GPR26(r1) ;\
83 l.lwz r27,PT_GPR27(r1) ;\
84 l.lwz r28,PT_GPR28(r1) ;\
85 l.lwz r29,PT_GPR29(r1) ;\
86 l.lwz r30,PT_GPR30(r1) ;\
87 l.lwz r31,PT_GPR31(r1) ;\
92 #define EXCEPTION_ENTRY(handler) \
95 /* r1, EPCR, ESR a already saved */ ;\
96 l.sw PT_GPR2(r1),r2 ;\
97 l.sw PT_GPR3(r1),r3 ;\
98 /* r4 already save */ ;\
99 l.sw PT_GPR5(r1),r5 ;\
100 l.sw PT_GPR6(r1),r6 ;\
101 l.sw PT_GPR7(r1),r7 ;\
102 l.sw PT_GPR8(r1),r8 ;\
103 l.sw PT_GPR9(r1),r9 ;\
104 /* r10 already saved */ ;\
105 l.sw PT_GPR11(r1),r11 ;\
106 /* r12 already saved */ ;\
107 l.sw PT_GPR13(r1),r13 ;\
108 l.sw PT_GPR14(r1),r14 ;\
109 l.sw PT_GPR15(r1),r15 ;\
110 l.sw PT_GPR16(r1),r16 ;\
111 l.sw PT_GPR17(r1),r17 ;\
112 l.sw PT_GPR18(r1),r18 ;\
113 l.sw PT_GPR19(r1),r19 ;\
114 l.sw PT_GPR20(r1),r20 ;\
115 l.sw PT_GPR21(r1),r21 ;\
116 l.sw PT_GPR22(r1),r22 ;\
117 l.sw PT_GPR23(r1),r23 ;\
118 l.sw PT_GPR24(r1),r24 ;\
119 l.sw PT_GPR25(r1),r25 ;\
120 l.sw PT_GPR26(r1),r26 ;\
121 l.sw PT_GPR27(r1),r27 ;\
122 l.sw PT_GPR28(r1),r28 ;\
123 l.sw PT_GPR29(r1),r29 ;\
124 /* r30 already save */ ;\
125 /* l.sw PT_GPR30(r1),r30*/ ;\
126 l.sw PT_GPR31(r1),r31 ;\
127 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
129 l.sw PT_ORIG_GPR11(r1),r30
131 #define UNHANDLED_EXCEPTION(handler,vector) \
134 /* r1, EPCR, ESR already saved */ ;\
135 l.sw PT_GPR2(r1),r2 ;\
136 l.sw PT_GPR3(r1),r3 ;\
137 l.sw PT_GPR5(r1),r5 ;\
138 l.sw PT_GPR6(r1),r6 ;\
139 l.sw PT_GPR7(r1),r7 ;\
140 l.sw PT_GPR8(r1),r8 ;\
141 l.sw PT_GPR9(r1),r9 ;\
142 /* r10 already saved */ ;\
143 l.sw PT_GPR11(r1),r11 ;\
144 /* r12 already saved */ ;\
145 l.sw PT_GPR13(r1),r13 ;\
146 l.sw PT_GPR14(r1),r14 ;\
147 l.sw PT_GPR15(r1),r15 ;\
148 l.sw PT_GPR16(r1),r16 ;\
149 l.sw PT_GPR17(r1),r17 ;\
150 l.sw PT_GPR18(r1),r18 ;\
151 l.sw PT_GPR19(r1),r19 ;\
152 l.sw PT_GPR20(r1),r20 ;\
153 l.sw PT_GPR21(r1),r21 ;\
154 l.sw PT_GPR22(r1),r22 ;\
155 l.sw PT_GPR23(r1),r23 ;\
156 l.sw PT_GPR24(r1),r24 ;\
157 l.sw PT_GPR25(r1),r25 ;\
158 l.sw PT_GPR26(r1),r26 ;\
159 l.sw PT_GPR27(r1),r27 ;\
160 l.sw PT_GPR28(r1),r28 ;\
161 l.sw PT_GPR29(r1),r29 ;\
162 /* r31 already saved */ ;\
163 l.sw PT_GPR30(r1),r30 ;\
164 /* l.sw PT_GPR31(r1),r31 */ ;\
165 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
167 l.sw PT_ORIG_GPR11(r1),r30 ;\
169 /* r4 is exception EA */ ;\
170 l.addi r5,r0,vector ;\
171 l.jal unhandled_exception ;\
173 l.j _ret_from_exception ;\
177 #define CLEAR_LWA_FLAG(reg) \
178 l.movhi reg,hi(lwa_flag) ;\
179 l.ori reg,reg,lo(lwa_flag) ;\
182 * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
183 * contain the same values as when exception we're handling
184 * occured. in fact they never do. if you need them use
185 * values saved on stack (for SPR_EPC, SPR_ESR) or content
186 * of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
187 * in 'arch/openrisc/kernel/head.S'
190 /* =====================================================[ exceptions] === */
192 /* ---[ 0x100: RESET exception ]----------------------------------------- */
194 EXCEPTION_ENTRY(_tng_kernel_start)
198 /* ---[ 0x200: BUS exception ]------------------------------------------- */
200 EXCEPTION_ENTRY(_bus_fault_handler)
202 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
204 l.addi r3,r1,0 /* pt_regs */
206 l.j _ret_from_exception
209 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
210 EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
216 EXCEPTION_ENTRY(_data_page_fault_handler)
218 /* set up parameters for do_page_fault */
219 l.ori r5,r0,0x300 // exception vector
221 l.addi r3,r1,0 // pt_regs
222 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
224 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
225 l.lwz r6,PT_PC(r3) // address of an offending insn
226 l.lwz r6,0(r6) // instruction that caused pf
228 l.srli r6,r6,26 // check opcode for jump insn
231 l.sfeqi r6,1 // l.jal
233 l.sfeqi r6,3 // l.bnf
237 l.sfeqi r6,0x11 // l.jr
239 l.sfeqi r6,0x12 // l.jalr
246 8: // offending insn is in delay slot
247 l.lwz r6,PT_PC(r3) // address of an offending insn
249 l.lwz r6,0(r6) // instruction that caused pf
250 l.srli r6,r6,26 // get opcode
251 9: // offending instruction opcode loaded in r6
255 l.mfspr r6,r0,SPR_SR // SR
256 l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
257 l.sfne r6,r0 // exception happened in delay slot
259 l.lwz r6,PT_PC(r3) // address of an offending insn
261 l.addi r6,r6,4 // offending insn is in delay slot
263 l.lwz r6,0(r6) // instruction that caused pf
264 l.srli r6,r6,26 // check opcode for write access
267 l.sfgeui r6,0x33 // check opcode for write access
271 l.ori r6,r0,0x1 // write access
274 1: l.ori r6,r0,0x0 // !write access
277 /* call fault.c handler in or32/mm/fault.c */
280 l.j _ret_from_exception
283 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
284 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
290 EXCEPTION_ENTRY(_insn_page_fault_handler)
292 /* set up parameters for do_page_fault */
293 l.ori r5,r0,0x400 // exception vector
295 l.addi r3,r1,0 // pt_regs
296 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
297 l.ori r6,r0,0x0 // !write access
299 /* call fault.c handler in or32/mm/fault.c */
302 l.j _ret_from_exception
306 /* ---[ 0x500: Timer exception ]----------------------------------------- */
308 EXCEPTION_ENTRY(_timer_handler)
310 l.jal timer_interrupt
311 l.addi r3,r1,0 /* pt_regs */
316 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
318 EXCEPTION_ENTRY(_alignment_handler)
320 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
321 l.jal do_unaligned_access
322 l.addi r3,r1,0 /* pt_regs */
324 l.j _ret_from_exception
328 EXCEPTION_ENTRY(_alignment_handler)
329 // l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
331 // l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
334 l.lwz r3,0(r5) /* Load insn */
335 l.srli r4,r3,26 /* Shift left to get the insn opcode */
337 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
351 l.addi r5,r5,4 /* Increment PC to get return insn address */
354 l.slli r4,r3,6 /* Get the signed extended jump length */
357 l.lwz r3,4(r5) /* Load the real load/store insn */
359 l.add r5,r5,r4 /* Calculate jump target address */
362 l.srli r4,r3,26 /* Shift left to get the insn opcode */
365 l.slli r4,r3,9 /* Shift to get the reg nb */
368 l.lwz r3,4(r5) /* Load the real load/store insn */
370 l.add r4,r4,r1 /* Load the jump register value from the stack */
373 l.srli r4,r3,26 /* Shift left to get the insn opcode */
377 // l.mtspr r0,r5,SPR_EPCR_BASE
394 1: l.j 1b /* I don't know what to do */
478 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
480 EXCEPTION_ENTRY(_illegal_instruction_handler)
481 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
482 l.jal do_illegal_instruction
483 l.addi r3,r1,0 /* pt_regs */
485 l.j _ret_from_exception
488 /* ---[ 0x800: External interrupt exception ]---------------------------- */
490 EXCEPTION_ENTRY(_external_irq_handler)
491 #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
492 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
493 l.andi r4,r4,SPR_SR_IEE
495 l.bnf 1f // ext irq enabled, all ok.
507 .section .rodata, "a"
509 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
514 l.ori r4,r4,SPR_SR_IEE // fix the bug
520 l.movhi r8,hi(do_IRQ)
521 l.ori r8,r8,lo(do_IRQ)
527 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
530 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
533 /* ---[ 0xb00: Range exception ]----------------------------------------- */
535 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
537 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
540 * Syscalls are a special type of exception in that they are
541 * _explicitly_ invoked by userspace and can therefore be
542 * held to conform to the same ABI as normal functions with
543 * respect to whether registers are preserved across the call
547 /* Upon syscall entry we just save the callee-saved registers
548 * and not the call-clobbered ones.
551 _string_syscall_return:
552 .string "syscall return %ld \n\r\0"
555 ENTRY(_sys_call_handler)
556 /* syscalls run with interrupts enabled */
557 ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp
559 /* r1, EPCR, ESR a already saved */
561 /* r3-r8 must be saved because syscall restart relies
562 * on us being able to restart the syscall args... technically
563 * they should be clobbered, otherwise
568 * r4 holds the EEAR address of the fault, use it as screatch reg and
569 * then load the original r4
578 /* r10 already saved */
579 l.sw PT_GPR11(r1),r11
580 /* orig_gpr11 must be set for syscalls */
581 l.sw PT_ORIG_GPR11(r1),r11
582 /* r12,r13 already saved */
584 /* r14-r28 (even) aren't touched by the syscall fast path below
585 * so we don't need to save them. However, the functions that return
586 * to userspace via a call to switch() DO need to save these because
587 * switch() effectively clobbers them... saving these registers for
588 * such functions is handled in their syscall wrappers (see fork, vfork,
591 /* r30 is the only register we clobber in the fast path */
592 /* r30 already saved */
593 /* l.sw PT_GPR30(r1),r30 */
595 _syscall_check_trace_enter:
596 /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
597 l.lwz r30,TI_FLAGS(r10)
598 l.andi r30,r30,_TIF_SYSCALL_TRACE
600 l.bf _syscall_trace_enter
604 /* Ensure that the syscall number is reasonable */
605 l.sfgeui r11,__NR_syscalls
610 l.movhi r29,hi(sys_call_table)
611 l.ori r29,r29,lo(sys_call_table)
620 /* All syscalls return here... just pay attention to ret_from_fork
621 * which does it in a round-about way.
623 l.sw PT_GPR11(r1),r11 // save return value
627 l.movhi r3,hi(_string_syscall_return)
628 l.ori r3,r3,lo(_string_syscall_return)
633 l.movhi r27,hi(printk)
634 l.ori r27,r27,lo(printk)
640 _syscall_check_trace_leave:
641 /* r30 is a callee-saved register so this should still hold the
642 * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
643 * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
646 l.bf _syscall_trace_leave
649 /* This is where the exception-return code begins... interrupts need to be
650 * disabled the rest of the way here because we can't afford to miss any
651 * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
654 /* Here we need to disable interrupts */
655 DISABLE_INTERRUPTS(r27,r29)
656 l.lwz r30,TI_FLAGS(r10)
657 l.andi r30,r30,_TIF_WORK_MASK
660 l.bnf _syscall_resume_userspace
663 /* Work pending follows a different return path, so we need to
664 * make sure that all the call-saved registers get into pt_regs
665 * before branching...
667 l.sw PT_GPR14(r1),r14
668 l.sw PT_GPR16(r1),r16
669 l.sw PT_GPR18(r1),r18
670 l.sw PT_GPR20(r1),r20
671 l.sw PT_GPR22(r1),r22
672 l.sw PT_GPR24(r1),r24
673 l.sw PT_GPR26(r1),r26
674 l.sw PT_GPR28(r1),r28
676 /* _work_pending needs to be called with interrupts disabled */
680 _syscall_resume_userspace:
681 // ENABLE_INTERRUPTS(r29)
684 /* This is the hot path for returning to userspace from a syscall. If there's
685 * work to be done and the branch to _work_pending was taken above, then the
686 * return to userspace will be done via the normal exception return path...
687 * that path restores _all_ registers and will overwrite the "clobbered"
688 * registers with whatever garbage is in pt_regs -- that's OK because those
689 * registers are clobbered anyway and because the extra work is insignificant
690 * in the context of the extra work that _work_pending is doing.
692 /* Once again, syscalls are special and only guarantee to preserve the
693 * same registers as a normal function call */
695 /* The assumption here is that the registers r14-r28 (even) are untouched and
696 * don't need to be restored... be sure that that's really the case!
699 /* This is still too much... we should only be restoring what we actually
700 * clobbered... we should even be using 'scratch' (odd) regs above so that
701 * we don't need to restore anything, hardly...
707 /* r3-r8 are technically clobbered, but syscall restart needs these
718 l.lwz r10,PT_GPR10(r1)
719 l.lwz r11,PT_GPR11(r1)
721 /* r30 is the only register we clobber in the fast path */
722 l.lwz r30,PT_GPR30(r1)
724 /* Here we use r13-r19 (odd) as scratch regs */
728 /* Interrupts need to be disabled for setting EPCR and ESR
729 * so that another interrupt doesn't come in here and clobber
730 * them before we can use them for our l.rfe */
731 DISABLE_INTERRUPTS(r17,r19)
732 l.mtspr r0,r13,SPR_EPCR_BASE
733 l.mtspr r0,r15,SPR_ESR_BASE
737 * Keep the below tracing and error handling out of the hot path...
740 _syscall_trace_enter:
741 /* Here we pass pt_regs to do_syscall_trace_enter. Make sure
742 * that function is really getting all the info it needs as
743 * pt_regs isn't a complete set of userspace regs, just the
744 * ones relevant to the syscall...
746 * Note use of delay slot for setting argument.
748 l.jal do_syscall_trace_enter
751 /* Restore arguments (not preserved across do_syscall_trace_enter)
752 * so that we can do the syscall for real and return to the syscall
755 l.lwz r11,PT_GPR11(r1)
765 _syscall_trace_leave:
766 l.jal do_syscall_trace_leave
769 l.j _syscall_check_work
773 /* Here we effectively pretend to have executed an imaginary
774 * syscall that returns -ENOSYS and then return to the regular
776 * Note that "return value" is set in the delay slot...
779 l.addi r11,r0,-ENOSYS
781 /******* END SYSCALL HANDLING *******/
783 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
785 UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
787 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
789 EXCEPTION_ENTRY(_trap_handler)
791 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
793 l.addi r3,r1,0 /* pt_regs */
795 l.j _ret_from_exception
798 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
800 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
802 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
804 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
806 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
808 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
810 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
812 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
814 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
816 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
818 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
820 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
822 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
824 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
826 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
828 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
830 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
832 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
834 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
836 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
838 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
840 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
842 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
844 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
846 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
848 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
850 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
852 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
854 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
856 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
858 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
860 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
862 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
864 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
866 /* ========================================================[ return ] === */
869 DISABLE_INTERRUPTS(r3,r4)
870 l.lwz r4,TI_FLAGS(r10)
871 l.andi r13,r4,_TIF_WORK_MASK
877 l.lwz r5,PT_ORIG_GPR11(r1)
883 l.jal do_work_pending
884 l.ori r3,r1,0 /* pt_regs */
893 l.ori r11,r11,__NR_restart_syscall
894 l.j _syscall_check_trace_enter
897 l.lwz r11,PT_ORIG_GPR11(r1)
898 /* Restore arg registers */
904 l.j _syscall_check_trace_enter
909 /* This returns to userspace code */
912 ENTRY(_ret_from_intr)
913 ENTRY(_ret_from_exception)
915 l.andi r3,r4,SPR_SR_SM
919 l.j _resume_userspace
926 /* Check if we are a kernel thread */
931 /* ...we are a kernel thread so invoke the requested callback */
936 /* _syscall_returns expect r11 to contain return value */
937 l.lwz r11,PT_GPR11(r1)
939 /* The syscall fast path return expects call-saved registers
940 * r12-r28 to be untouched, so we restore them here as they
941 * will have been effectively clobbered when arriving here
942 * via the call to switch()
944 l.lwz r12,PT_GPR12(r1)
945 l.lwz r14,PT_GPR14(r1)
946 l.lwz r16,PT_GPR16(r1)
947 l.lwz r18,PT_GPR18(r1)
948 l.lwz r20,PT_GPR20(r1)
949 l.lwz r22,PT_GPR22(r1)
950 l.lwz r24,PT_GPR24(r1)
951 l.lwz r26,PT_GPR26(r1)
952 l.lwz r28,PT_GPR28(r1)
957 /* ========================================================[ switch ] === */
960 * This routine switches between two different tasks. The process
961 * state of one is saved on its kernel stack. Then the state
962 * of the other is restored from its kernel stack. The memory
963 * management hardware is updated to the second process's state.
964 * Finally, we can return to the second process, via the 'return'.
966 * Note: there are two ways to get to the "going out" portion
967 * of this code; either by coming in via the entry (_switch)
968 * or via "fork" which must set up an environment equivalent
969 * to the "_switch" path. If you change this (or in particular, the
970 * SAVE_REGS macro), you'll have to change the fork code also.
974 /* _switch MUST never lay on page boundry, cause it runs from
975 * effective addresses and beeing interrupted by iTLB miss would kill it.
976 * dTLB miss seams to never accour in the bad place since data accesses
977 * are from task structures which are always page aligned.
979 * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
980 * register, then load the previous register values and only at the end call
981 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
982 * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
985 * To avoid this problems it is sufficient to align _switch to
986 * some nice round number smaller than it's size...
989 /* ABI rules apply here... we either enter _switch via schedule() or via
990 * an imaginary call to which we shall return at return_from_fork. Either
991 * way, we are a function call and only need to preserve the callee-saved
992 * registers when we return. As such, we don't need to save the registers
993 * on the stack that we won't be returning as they were...
998 /* We don't store SR as _switch only gets called in a context where
999 * the SR will be the same going in and coming out... */
1001 /* Set up new pt_regs struct for saving task state */
1002 l.addi r1,r1,-(INT_FRAME_SIZE)
1004 /* No need to store r1/PT_SP as it goes into KSP below */
1007 /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1008 * and expects r12 to be callee-saved... */
1009 l.sw PT_GPR12(r1),r12
1010 l.sw PT_GPR14(r1),r14
1011 l.sw PT_GPR16(r1),r16
1012 l.sw PT_GPR18(r1),r18
1013 l.sw PT_GPR20(r1),r20
1014 l.sw PT_GPR22(r1),r22
1015 l.sw PT_GPR24(r1),r24
1016 l.sw PT_GPR26(r1),r26
1017 l.sw PT_GPR28(r1),r28
1018 l.sw PT_GPR30(r1),r30
1020 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1022 /* We use thread_info->ksp for storing the address of the above
1023 * structure so that we can get back to it later... we don't want
1024 * to lose the value of thread_info->ksp, though, so store it as
1025 * pt_regs->sp so that we can easily restore it when we are made
1029 /* Save the old value of thread_info->ksp as pt_regs->sp */
1030 l.lwz r29,TI_KSP(r10)
1033 /* Swap kernel stack pointers */
1034 l.sw TI_KSP(r10),r1 /* Save old stack pointer */
1035 l.or r10,r4,r0 /* Set up new current_thread_info */
1036 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
1038 /* Restore the old value of thread_info->ksp */
1040 l.sw TI_KSP(r10),r29
1042 /* ...and restore the registers, except r11 because the return value
1043 * has already been set above.
1045 l.lwz r2,PT_GPR2(r1)
1046 l.lwz r9,PT_GPR9(r1)
1047 /* No need to restore r10 */
1048 /* ...and do not restore r11 */
1050 /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1051 * and expects r12 to be callee-saved... */
1052 l.lwz r12,PT_GPR12(r1)
1053 l.lwz r14,PT_GPR14(r1)
1054 l.lwz r16,PT_GPR16(r1)
1055 l.lwz r18,PT_GPR18(r1)
1056 l.lwz r20,PT_GPR20(r1)
1057 l.lwz r22,PT_GPR22(r1)
1058 l.lwz r24,PT_GPR24(r1)
1059 l.lwz r26,PT_GPR26(r1)
1060 l.lwz r28,PT_GPR28(r1)
1061 l.lwz r30,PT_GPR30(r1)
1063 /* Unwind stack to pre-switch state */
1064 l.addi r1,r1,(INT_FRAME_SIZE)
1066 /* Return via the link-register back to where we 'came from', where
1067 * that may be either schedule(), ret_from_fork(), or
1068 * ret_from_kernel_thread(). If we are returning to a new thread,
1069 * we are expected to have set up the arg to schedule_tail already,
1070 * hence we do so here unconditionally:
1072 l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
1076 /* ==================================================================== */
1078 /* These all use the delay slot for setting the argument register, so the
1079 * jump is always happening after the l.addi instruction.
1081 * These are all just wrappers that don't touch the link-register r9, so the
1082 * return from the "real" syscall function will return back to the syscall
1083 * code that did the l.jal that brought us here.
1086 /* fork requires that we save all the callee-saved registers because they
1087 * are all effectively clobbered by the call to _switch. Here we store
1088 * all the registers that aren't touched by the syscall fast path and thus
1089 * weren't saved there.
1092 _fork_save_extra_regs_and_call:
1093 l.sw PT_GPR14(r1),r14
1094 l.sw PT_GPR16(r1),r16
1095 l.sw PT_GPR18(r1),r18
1096 l.sw PT_GPR20(r1),r20
1097 l.sw PT_GPR22(r1),r22
1098 l.sw PT_GPR24(r1),r24
1099 l.sw PT_GPR26(r1),r26
1101 l.sw PT_GPR28(r1),r28
1104 l.movhi r29,hi(sys_clone)
1105 l.ori r29,r29,lo(sys_clone)
1106 l.j _fork_save_extra_regs_and_call
1110 l.movhi r29,hi(sys_fork)
1111 l.ori r29,r29,lo(sys_fork)
1112 l.j _fork_save_extra_regs_and_call
1115 ENTRY(sys_rt_sigreturn)
1116 l.jal _sys_rt_sigreturn
1119 l.bnf _no_syscall_trace
1121 l.jal do_syscall_trace_leave
1124 l.j _resume_userspace
1127 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1128 * The functions takes a variable number of parameters depending on which
1129 * particular flavour of atomic you want... parameter 1 is a flag identifying
1130 * the atomic in question. Currently, this function implements the
1131 * following variants:
1137 * Atomically exchange the values in pointers 1 and 2.
1141 ENTRY(sys_or1k_atomic)
1142 /* FIXME: This ignores r3 and always does an XCHG */
1143 DISABLE_INTERRUPTS(r17,r19)
1148 ENABLE_INTERRUPTS(r17)
1152 /* ============================================================[ EOF ]=== */