1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2005-2017 Andes Technology Corporation
5 #include <linux/bootmem.h>
6 #include <linux/seq_file.h>
7 #include <linux/memblock.h>
8 #include <linux/console.h>
9 #include <linux/screen_info.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/of_fdt.h>
13 #include <linux/of_platform.h>
14 #include <asm/setup.h>
15 #include <asm/sections.h>
16 #include <asm/proc-fns.h>
17 #include <asm/cache_info.h>
19 #include <nds32_intrinsic.h>
21 #define HWCAP_MFUSR_PC 0x000001
22 #define HWCAP_EXT 0x000002
23 #define HWCAP_EXT2 0x000004
24 #define HWCAP_FPU 0x000008
25 #define HWCAP_AUDIO 0x000010
26 #define HWCAP_BASE16 0x000020
27 #define HWCAP_STRING 0x000040
28 #define HWCAP_REDUCED_REGS 0x000080
29 #define HWCAP_VIDEO 0x000100
30 #define HWCAP_ENCRYPT 0x000200
31 #define HWCAP_EDM 0x000400
32 #define HWCAP_LMDMA 0x000800
33 #define HWCAP_PFM 0x001000
34 #define HWCAP_HSMP 0x002000
35 #define HWCAP_TRACE 0x004000
36 #define HWCAP_DIV 0x008000
37 #define HWCAP_MAC 0x010000
38 #define HWCAP_L2C 0x020000
39 #define HWCAP_FPU_DP 0x040000
40 #define HWCAP_V2 0x080000
41 #define HWCAP_DX_REGS 0x100000
43 unsigned long cpu_id, cpu_rev, cpu_cfgid;
45 char *endianness = NULL;
47 unsigned int __atags_pointer __initdata;
48 unsigned int elf_hwcap;
49 EXPORT_SYMBOL(elf_hwcap);
52 * The following string table, must sync with HWCAP_xx bitmask,
53 * which is defined in <asm/procinfo.h>
55 static const char *hwcap_str[] = {
80 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
81 #define WRITE_METHOD "write through"
83 #define WRITE_METHOD "write back"
86 struct cache_info L1_cache_info[2];
87 static void __init dump_cpu_info(int cpu)
90 char str[sizeof(hwcap_str) + 16];
92 for (i = 0; hwcap_str[i]; i++) {
93 if (elf_hwcap & (1 << i)) {
94 sprintf(str + p, "%s ", hwcap_str[i]);
95 p += strlen(hwcap_str[i]) + 1;
99 pr_info("CPU%d Features: %s\n", cpu, str);
101 L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
102 L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
103 L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
104 L1_cache_info[ICACHE].size =
105 L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
106 L1_cache_info[ICACHE].sets / 1024;
107 pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
108 L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
109 L1_cache_info[ICACHE].line_size);
110 L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
111 L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
112 L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
113 L1_cache_info[DCACHE].size =
114 L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
115 L1_cache_info[DCACHE].sets / 1024;
116 pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
117 L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
118 L1_cache_info[DCACHE].line_size);
119 pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
120 if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
122 ("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
123 L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
124 #ifdef CONFIG_CPU_CACHE_ALIASING
128 L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
129 L1_cache_info[ICACHE].ways;
130 L1_cache_info[ICACHE].aliasing_num = aliasing_num;
131 L1_cache_info[ICACHE].aliasing_mask =
132 (aliasing_num - 1) << PAGE_SHIFT;
134 L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
135 L1_cache_info[DCACHE].ways;
136 L1_cache_info[DCACHE].aliasing_num = aliasing_num;
137 L1_cache_info[DCACHE].aliasing_mask =
138 (aliasing_num - 1) << PAGE_SHIFT;
143 static void __init setup_cpuinfo(void)
145 unsigned long tmp = 0, cpu_name;
147 cpu_dcache_inval_all();
148 cpu_icache_inval_all();
151 cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
152 cpu_name = ((cpu_id) & 0xf0) >> 4;
153 cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
154 cpu_id = cpu_id & 0xf;
155 cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
156 cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
158 pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
159 cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
161 elf_hwcap |= HWCAP_MFUSR_PC;
163 if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
164 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
165 elf_hwcap |= HWCAP_DIV;
167 if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
168 || (cpu_id == 12 && cpu_rev < 4))
169 elf_hwcap |= HWCAP_MAC;
171 elf_hwcap |= HWCAP_V2;
172 elf_hwcap |= HWCAP_DIV;
173 elf_hwcap |= HWCAP_MAC;
176 if (cpu_cfgid & 0x0001)
177 elf_hwcap |= HWCAP_EXT;
179 if (cpu_cfgid & 0x0002)
180 elf_hwcap |= HWCAP_BASE16;
182 if (cpu_cfgid & 0x0004)
183 elf_hwcap |= HWCAP_EXT2;
185 if (cpu_cfgid & 0x0008)
186 elf_hwcap |= HWCAP_FPU;
188 if (cpu_cfgid & 0x0010)
189 elf_hwcap |= HWCAP_STRING;
191 if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
196 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
197 elf_hwcap |= HWCAP_EDM;
199 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
200 elf_hwcap |= HWCAP_LMDMA;
202 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
203 elf_hwcap |= HWCAP_PFM;
205 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
206 elf_hwcap |= HWCAP_HSMP;
208 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
209 elf_hwcap |= HWCAP_TRACE;
211 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
212 elf_hwcap |= HWCAP_AUDIO;
214 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
215 elf_hwcap |= HWCAP_L2C;
217 tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
218 if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
219 tmp |= CACHE_CTL_mskDC_EN;
221 if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
222 tmp |= CACHE_CTL_mskIC_EN;
223 __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
225 dump_cpu_info(smp_processor_id());
228 static void __init setup_memory(void)
230 unsigned long ram_start_pfn;
231 unsigned long free_ram_start_pfn;
232 phys_addr_t memory_start, memory_end;
233 struct memblock_region *region;
235 memory_end = memory_start = 0;
237 /* Find main memory where is the kernel */
238 for_each_memblock(memory, region) {
239 memory_start = region->base;
240 memory_end = region->base + region->size;
241 pr_info("%s: Memory: 0x%x-0x%x\n", __func__,
242 memory_start, memory_end);
249 ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
250 /* free_ram_start_pfn is first page after kernel */
251 free_ram_start_pfn = PFN_UP(__pa(&_end));
252 max_pfn = PFN_DOWN(memblock_end_of_DRAM());
253 /* it could update max_pfn */
254 if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
255 max_low_pfn = max_pfn;
257 max_low_pfn = MAXMEM_PFN + ram_start_pfn;
258 if (!IS_ENABLED(CONFIG_HIGHMEM))
259 max_pfn = MAXMEM_PFN + ram_start_pfn;
261 /* high_memory is related with VMALLOC */
262 high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
263 min_low_pfn = free_ram_start_pfn;
266 * initialize the boot-time allocator (with low memory only).
268 * This makes the memory from the end of the kernel to the end of
271 memblock_set_bottom_up(true);
272 memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn));
274 early_init_fdt_reserve_self();
275 early_init_fdt_scan_reserved_mem();
280 void __init setup_arch(char **cmdline_p)
282 early_init_devtree(__atags_pointer ? \
283 phys_to_virt(__atags_pointer) : __dtb_start);
287 init_mm.start_code = (unsigned long)&_stext;
288 init_mm.end_code = (unsigned long)&_etext;
289 init_mm.end_data = (unsigned long)&_edata;
290 init_mm.brk = (unsigned long)&_end;
292 /* setup bootmem allocator */
295 /* paging_init() sets up the MMU and marks all pages as reserved */
298 /* invalidate all TLB entries because the new mapping is created */
299 __nds32__tlbop_flua();
301 /* use generic way to parse */
304 unflatten_and_copy_device_tree();
306 if(IS_ENABLED(CONFIG_VT)) {
307 if(IS_ENABLED(CONFIG_DUMMY_CONSOLE))
308 conswitchp = &dummy_con;
311 *cmdline_p = boot_command_line;
315 static int c_show(struct seq_file *m, void *v)
319 seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
320 cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
322 seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
323 CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
324 CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
325 CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
327 seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
328 CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
329 CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
330 CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
332 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
333 loops_per_jiffy / (500000 / HZ),
334 (loops_per_jiffy / (5000 / HZ)) % 100);
336 /* dump out the processor features */
337 seq_puts(m, "Features\t: ");
339 for (i = 0; hwcap_str[i]; i++)
340 if (elf_hwcap & (1 << i))
341 seq_printf(m, "%s ", hwcap_str[i]);
348 static void *c_start(struct seq_file *m, loff_t * pos)
350 return *pos < 1 ? (void *)1 : NULL;
353 static void *c_next(struct seq_file *m, void *v, loff_t * pos)
359 static void c_stop(struct seq_file *m, void *v)
363 struct seq_operations cpuinfo_op = {