1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
5 * Copyright (C) 2001-2002 MontaVista Software Inc.
6 * Author: Yoichi Yuasa <source@mvista.com>
7 * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
11 * MontaVista Software Inc. <source@mvista.com>
12 * - New creation, NEC VR4122 and VR4131 are supported.
13 * - Added support for NEC VR4111 and VR4121.
15 * Yoichi Yuasa <yuasa@linux-mips.org>
16 * - Coped with INTASSIGN of NEC VR4133.
18 #include <linux/errno.h>
19 #include <linux/export.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/irq.h>
23 #include <linux/smp.h>
24 #include <linux/types.h>
28 #include <asm/vr41xx/irq.h>
29 #include <asm/vr41xx/vr41xx.h>
31 static void __iomem *icu1_base;
32 static void __iomem *icu2_base;
34 static unsigned char sysint1_assign[16] = {
35 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
36 static unsigned char sysint2_assign[16] = {
37 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
39 #define ICU1_TYPE1_BASE 0x0b000080UL
40 #define ICU2_TYPE1_BASE 0x0b000200UL
42 #define ICU1_TYPE2_BASE 0x0f000080UL
43 #define ICU2_TYPE2_BASE 0x0f0000a0UL
45 #define ICU1_SIZE 0x20
46 #define ICU2_SIZE 0x1c
48 #define SYSINT1REG 0x00
49 #define PIUINTREG 0x02
50 #define INTASSIGN0 0x04
51 #define INTASSIGN1 0x06
52 #define GIUINTLREG 0x08
53 #define DSIUINTREG 0x0a
54 #define MSYSINT1REG 0x0c
55 #define MPIUINTREG 0x0e
56 #define MAIUINTREG 0x10
57 #define MKIUINTREG 0x12
58 #define MMACINTREG 0x12
59 #define MGIUINTLREG 0x14
60 #define MDSIUINTREG 0x16
63 #define INTASSIGN2 0x1c
64 #define INTASSIGN3 0x1e
66 #define SYSINT2REG 0x00
67 #define GIUINTHREG 0x02
68 #define FIRINTREG 0x04
69 #define MSYSINT2REG 0x06
70 #define MGIUINTHREG 0x08
71 #define MFIRINTREG 0x0a
72 #define PCIINTREG 0x0c
73 #define PCIINT0 0x0001
74 #define SCUINTREG 0x0e
75 #define SCUINT0 0x0001
76 #define CSIINTREG 0x10
77 #define MPCIINTREG 0x12
78 #define MSCUINTREG 0x14
79 #define MCSIINTREG 0x16
80 #define BCUINTREG 0x18
81 #define BCUINTR 0x0001
82 #define MBCUINTREG 0x1a
84 #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
85 #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
87 #define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
89 #define icu1_read(offset) readw(icu1_base + (offset))
90 #define icu1_write(offset, value) writew((value), icu1_base + (offset))
92 #define icu2_read(offset) readw(icu2_base + (offset))
93 #define icu2_write(offset, value) writew((value), icu2_base + (offset))
95 #define INTASSIGN_MAX 4
96 #define INTASSIGN_MASK 0x0007
98 static inline uint16_t icu1_set(uint8_t offset, uint16_t set)
102 data = icu1_read(offset);
104 icu1_write(offset, data);
109 static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear)
113 data = icu1_read(offset);
115 icu1_write(offset, data);
120 static inline uint16_t icu2_set(uint8_t offset, uint16_t set)
124 data = icu2_read(offset);
126 icu2_write(offset, data);
131 static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)
135 data = icu2_read(offset);
137 icu2_write(offset, data);
142 void vr41xx_enable_piuint(uint16_t mask)
144 struct irq_desc *desc = irq_to_desc(PIU_IRQ);
147 if (current_cpu_type() == CPU_VR4111 ||
148 current_cpu_type() == CPU_VR4121) {
149 raw_spin_lock_irqsave(&desc->lock, flags);
150 icu1_set(MPIUINTREG, mask);
151 raw_spin_unlock_irqrestore(&desc->lock, flags);
155 EXPORT_SYMBOL(vr41xx_enable_piuint);
157 void vr41xx_disable_piuint(uint16_t mask)
159 struct irq_desc *desc = irq_to_desc(PIU_IRQ);
162 if (current_cpu_type() == CPU_VR4111 ||
163 current_cpu_type() == CPU_VR4121) {
164 raw_spin_lock_irqsave(&desc->lock, flags);
165 icu1_clear(MPIUINTREG, mask);
166 raw_spin_unlock_irqrestore(&desc->lock, flags);
170 EXPORT_SYMBOL(vr41xx_disable_piuint);
172 void vr41xx_enable_aiuint(uint16_t mask)
174 struct irq_desc *desc = irq_to_desc(AIU_IRQ);
177 if (current_cpu_type() == CPU_VR4111 ||
178 current_cpu_type() == CPU_VR4121) {
179 raw_spin_lock_irqsave(&desc->lock, flags);
180 icu1_set(MAIUINTREG, mask);
181 raw_spin_unlock_irqrestore(&desc->lock, flags);
185 EXPORT_SYMBOL(vr41xx_enable_aiuint);
187 void vr41xx_disable_aiuint(uint16_t mask)
189 struct irq_desc *desc = irq_to_desc(AIU_IRQ);
192 if (current_cpu_type() == CPU_VR4111 ||
193 current_cpu_type() == CPU_VR4121) {
194 raw_spin_lock_irqsave(&desc->lock, flags);
195 icu1_clear(MAIUINTREG, mask);
196 raw_spin_unlock_irqrestore(&desc->lock, flags);
200 EXPORT_SYMBOL(vr41xx_disable_aiuint);
202 void vr41xx_enable_kiuint(uint16_t mask)
204 struct irq_desc *desc = irq_to_desc(KIU_IRQ);
207 if (current_cpu_type() == CPU_VR4111 ||
208 current_cpu_type() == CPU_VR4121) {
209 raw_spin_lock_irqsave(&desc->lock, flags);
210 icu1_set(MKIUINTREG, mask);
211 raw_spin_unlock_irqrestore(&desc->lock, flags);
215 EXPORT_SYMBOL(vr41xx_enable_kiuint);
217 void vr41xx_disable_kiuint(uint16_t mask)
219 struct irq_desc *desc = irq_to_desc(KIU_IRQ);
222 if (current_cpu_type() == CPU_VR4111 ||
223 current_cpu_type() == CPU_VR4121) {
224 raw_spin_lock_irqsave(&desc->lock, flags);
225 icu1_clear(MKIUINTREG, mask);
226 raw_spin_unlock_irqrestore(&desc->lock, flags);
230 EXPORT_SYMBOL(vr41xx_disable_kiuint);
232 void vr41xx_enable_macint(uint16_t mask)
234 struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ);
237 raw_spin_lock_irqsave(&desc->lock, flags);
238 icu1_set(MMACINTREG, mask);
239 raw_spin_unlock_irqrestore(&desc->lock, flags);
242 EXPORT_SYMBOL(vr41xx_enable_macint);
244 void vr41xx_disable_macint(uint16_t mask)
246 struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ);
249 raw_spin_lock_irqsave(&desc->lock, flags);
250 icu1_clear(MMACINTREG, mask);
251 raw_spin_unlock_irqrestore(&desc->lock, flags);
254 EXPORT_SYMBOL(vr41xx_disable_macint);
256 void vr41xx_enable_dsiuint(uint16_t mask)
258 struct irq_desc *desc = irq_to_desc(DSIU_IRQ);
261 raw_spin_lock_irqsave(&desc->lock, flags);
262 icu1_set(MDSIUINTREG, mask);
263 raw_spin_unlock_irqrestore(&desc->lock, flags);
266 EXPORT_SYMBOL(vr41xx_enable_dsiuint);
268 void vr41xx_disable_dsiuint(uint16_t mask)
270 struct irq_desc *desc = irq_to_desc(DSIU_IRQ);
273 raw_spin_lock_irqsave(&desc->lock, flags);
274 icu1_clear(MDSIUINTREG, mask);
275 raw_spin_unlock_irqrestore(&desc->lock, flags);
278 EXPORT_SYMBOL(vr41xx_disable_dsiuint);
280 void vr41xx_enable_firint(uint16_t mask)
282 struct irq_desc *desc = irq_to_desc(FIR_IRQ);
285 raw_spin_lock_irqsave(&desc->lock, flags);
286 icu2_set(MFIRINTREG, mask);
287 raw_spin_unlock_irqrestore(&desc->lock, flags);
290 EXPORT_SYMBOL(vr41xx_enable_firint);
292 void vr41xx_disable_firint(uint16_t mask)
294 struct irq_desc *desc = irq_to_desc(FIR_IRQ);
297 raw_spin_lock_irqsave(&desc->lock, flags);
298 icu2_clear(MFIRINTREG, mask);
299 raw_spin_unlock_irqrestore(&desc->lock, flags);
302 EXPORT_SYMBOL(vr41xx_disable_firint);
304 void vr41xx_enable_pciint(void)
306 struct irq_desc *desc = irq_to_desc(PCI_IRQ);
309 if (current_cpu_type() == CPU_VR4122 ||
310 current_cpu_type() == CPU_VR4131 ||
311 current_cpu_type() == CPU_VR4133) {
312 raw_spin_lock_irqsave(&desc->lock, flags);
313 icu2_write(MPCIINTREG, PCIINT0);
314 raw_spin_unlock_irqrestore(&desc->lock, flags);
318 EXPORT_SYMBOL(vr41xx_enable_pciint);
320 void vr41xx_disable_pciint(void)
322 struct irq_desc *desc = irq_to_desc(PCI_IRQ);
325 if (current_cpu_type() == CPU_VR4122 ||
326 current_cpu_type() == CPU_VR4131 ||
327 current_cpu_type() == CPU_VR4133) {
328 raw_spin_lock_irqsave(&desc->lock, flags);
329 icu2_write(MPCIINTREG, 0);
330 raw_spin_unlock_irqrestore(&desc->lock, flags);
334 EXPORT_SYMBOL(vr41xx_disable_pciint);
336 void vr41xx_enable_scuint(void)
338 struct irq_desc *desc = irq_to_desc(SCU_IRQ);
341 if (current_cpu_type() == CPU_VR4122 ||
342 current_cpu_type() == CPU_VR4131 ||
343 current_cpu_type() == CPU_VR4133) {
344 raw_spin_lock_irqsave(&desc->lock, flags);
345 icu2_write(MSCUINTREG, SCUINT0);
346 raw_spin_unlock_irqrestore(&desc->lock, flags);
350 EXPORT_SYMBOL(vr41xx_enable_scuint);
352 void vr41xx_disable_scuint(void)
354 struct irq_desc *desc = irq_to_desc(SCU_IRQ);
357 if (current_cpu_type() == CPU_VR4122 ||
358 current_cpu_type() == CPU_VR4131 ||
359 current_cpu_type() == CPU_VR4133) {
360 raw_spin_lock_irqsave(&desc->lock, flags);
361 icu2_write(MSCUINTREG, 0);
362 raw_spin_unlock_irqrestore(&desc->lock, flags);
366 EXPORT_SYMBOL(vr41xx_disable_scuint);
368 void vr41xx_enable_csiint(uint16_t mask)
370 struct irq_desc *desc = irq_to_desc(CSI_IRQ);
373 if (current_cpu_type() == CPU_VR4122 ||
374 current_cpu_type() == CPU_VR4131 ||
375 current_cpu_type() == CPU_VR4133) {
376 raw_spin_lock_irqsave(&desc->lock, flags);
377 icu2_set(MCSIINTREG, mask);
378 raw_spin_unlock_irqrestore(&desc->lock, flags);
382 EXPORT_SYMBOL(vr41xx_enable_csiint);
384 void vr41xx_disable_csiint(uint16_t mask)
386 struct irq_desc *desc = irq_to_desc(CSI_IRQ);
389 if (current_cpu_type() == CPU_VR4122 ||
390 current_cpu_type() == CPU_VR4131 ||
391 current_cpu_type() == CPU_VR4133) {
392 raw_spin_lock_irqsave(&desc->lock, flags);
393 icu2_clear(MCSIINTREG, mask);
394 raw_spin_unlock_irqrestore(&desc->lock, flags);
398 EXPORT_SYMBOL(vr41xx_disable_csiint);
400 void vr41xx_enable_bcuint(void)
402 struct irq_desc *desc = irq_to_desc(BCU_IRQ);
405 if (current_cpu_type() == CPU_VR4122 ||
406 current_cpu_type() == CPU_VR4131 ||
407 current_cpu_type() == CPU_VR4133) {
408 raw_spin_lock_irqsave(&desc->lock, flags);
409 icu2_write(MBCUINTREG, BCUINTR);
410 raw_spin_unlock_irqrestore(&desc->lock, flags);
414 EXPORT_SYMBOL(vr41xx_enable_bcuint);
416 void vr41xx_disable_bcuint(void)
418 struct irq_desc *desc = irq_to_desc(BCU_IRQ);
421 if (current_cpu_type() == CPU_VR4122 ||
422 current_cpu_type() == CPU_VR4131 ||
423 current_cpu_type() == CPU_VR4133) {
424 raw_spin_lock_irqsave(&desc->lock, flags);
425 icu2_write(MBCUINTREG, 0);
426 raw_spin_unlock_irqrestore(&desc->lock, flags);
430 EXPORT_SYMBOL(vr41xx_disable_bcuint);
432 static void disable_sysint1_irq(struct irq_data *d)
434 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));
437 static void enable_sysint1_irq(struct irq_data *d)
439 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));
442 static struct irq_chip sysint1_irq_type = {
444 .irq_mask = disable_sysint1_irq,
445 .irq_unmask = enable_sysint1_irq,
448 static void disable_sysint2_irq(struct irq_data *d)
450 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));
453 static void enable_sysint2_irq(struct irq_data *d)
455 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));
458 static struct irq_chip sysint2_irq_type = {
460 .irq_mask = disable_sysint2_irq,
461 .irq_unmask = enable_sysint2_irq,
464 static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
466 struct irq_desc *desc = irq_to_desc(irq);
467 uint16_t intassign0, intassign1;
470 pin = SYSINT1_IRQ_TO_PIN(irq);
472 raw_spin_lock_irq(&desc->lock);
474 intassign0 = icu1_read(INTASSIGN0);
475 intassign1 = icu1_read(INTASSIGN1);
479 intassign0 &= ~INTASSIGN_MASK;
480 intassign0 |= (uint16_t)assign;
483 intassign0 &= ~(INTASSIGN_MASK << 3);
484 intassign0 |= (uint16_t)assign << 3;
487 intassign0 &= ~(INTASSIGN_MASK << 6);
488 intassign0 |= (uint16_t)assign << 6;
491 intassign0 &= ~(INTASSIGN_MASK << 9);
492 intassign0 |= (uint16_t)assign << 9;
495 intassign0 &= ~(INTASSIGN_MASK << 12);
496 intassign0 |= (uint16_t)assign << 12;
499 intassign1 &= ~INTASSIGN_MASK;
500 intassign1 |= (uint16_t)assign;
503 intassign1 &= ~(INTASSIGN_MASK << 6);
504 intassign1 |= (uint16_t)assign << 6;
507 intassign1 &= ~(INTASSIGN_MASK << 9);
508 intassign1 |= (uint16_t)assign << 9;
511 raw_spin_unlock_irq(&desc->lock);
515 sysint1_assign[pin] = assign;
516 icu1_write(INTASSIGN0, intassign0);
517 icu1_write(INTASSIGN1, intassign1);
519 raw_spin_unlock_irq(&desc->lock);
524 static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
526 struct irq_desc *desc = irq_to_desc(irq);
527 uint16_t intassign2, intassign3;
530 pin = SYSINT2_IRQ_TO_PIN(irq);
532 raw_spin_lock_irq(&desc->lock);
534 intassign2 = icu1_read(INTASSIGN2);
535 intassign3 = icu1_read(INTASSIGN3);
539 intassign2 &= ~INTASSIGN_MASK;
540 intassign2 |= (uint16_t)assign;
543 intassign2 &= ~(INTASSIGN_MASK << 3);
544 intassign2 |= (uint16_t)assign << 3;
547 intassign2 &= ~(INTASSIGN_MASK << 6);
548 intassign2 |= (uint16_t)assign << 6;
551 intassign2 &= ~(INTASSIGN_MASK << 9);
552 intassign2 |= (uint16_t)assign << 9;
555 intassign2 &= ~(INTASSIGN_MASK << 12);
556 intassign2 |= (uint16_t)assign << 12;
559 intassign3 &= ~INTASSIGN_MASK;
560 intassign3 |= (uint16_t)assign;
563 intassign3 &= ~(INTASSIGN_MASK << 3);
564 intassign3 |= (uint16_t)assign << 3;
567 intassign3 &= ~(INTASSIGN_MASK << 6);
568 intassign3 |= (uint16_t)assign << 6;
571 intassign3 &= ~(INTASSIGN_MASK << 9);
572 intassign3 |= (uint16_t)assign << 9;
575 intassign3 &= ~(INTASSIGN_MASK << 12);
576 intassign3 |= (uint16_t)assign << 12;
579 raw_spin_unlock_irq(&desc->lock);
583 sysint2_assign[pin] = assign;
584 icu1_write(INTASSIGN2, intassign2);
585 icu1_write(INTASSIGN3, intassign3);
587 raw_spin_unlock_irq(&desc->lock);
592 int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
594 int retval = -EINVAL;
596 if (current_cpu_type() != CPU_VR4133)
599 if (intassign > INTASSIGN_MAX)
602 if (irq >= SYSINT1_IRQ_BASE && irq <= SYSINT1_IRQ_LAST)
603 retval = set_sysint1_assign(irq, intassign);
604 else if (irq >= SYSINT2_IRQ_BASE && irq <= SYSINT2_IRQ_LAST)
605 retval = set_sysint2_assign(irq, intassign);
610 EXPORT_SYMBOL(vr41xx_set_intassign);
612 static int icu_get_irq(unsigned int irq)
614 uint16_t pend1, pend2;
615 uint16_t mask1, mask2;
618 pend1 = icu1_read(SYSINT1REG);
619 mask1 = icu1_read(MSYSINT1REG);
621 pend2 = icu2_read(SYSINT2REG);
622 mask2 = icu2_read(MSYSINT2REG);
628 for (i = 0; i < 16; i++) {
629 if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i)))
630 return SYSINT1_IRQ(i);
635 for (i = 0; i < 16; i++) {
636 if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i)))
637 return SYSINT2_IRQ(i);
641 printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
646 static int __init vr41xx_icu_init(void)
648 unsigned long icu1_start, icu2_start;
651 switch (current_cpu_type()) {
654 icu1_start = ICU1_TYPE1_BASE;
655 icu2_start = ICU2_TYPE1_BASE;
660 icu1_start = ICU1_TYPE2_BASE;
661 icu2_start = ICU2_TYPE2_BASE;
664 printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
668 if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL)
671 if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) {
672 release_mem_region(icu1_start, ICU1_SIZE);
676 icu1_base = ioremap(icu1_start, ICU1_SIZE);
677 if (icu1_base == NULL) {
678 release_mem_region(icu1_start, ICU1_SIZE);
679 release_mem_region(icu2_start, ICU2_SIZE);
683 icu2_base = ioremap(icu2_start, ICU2_SIZE);
684 if (icu2_base == NULL) {
686 release_mem_region(icu1_start, ICU1_SIZE);
687 release_mem_region(icu2_start, ICU2_SIZE);
691 icu1_write(MSYSINT1REG, 0);
692 icu1_write(MGIUINTLREG, 0xffff);
694 icu2_write(MSYSINT2REG, 0);
695 icu2_write(MGIUINTHREG, 0xffff);
697 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
698 irq_set_chip_and_handler(i, &sysint1_irq_type,
701 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
702 irq_set_chip_and_handler(i, &sysint2_irq_type,
705 cascade_irq(INT0_IRQ, icu_get_irq);
706 cascade_irq(INT1_IRQ, icu_get_irq);
707 cascade_irq(INT2_IRQ, icu_get_irq);
708 cascade_irq(INT3_IRQ, icu_get_irq);
709 cascade_irq(INT4_IRQ, icu_get_irq);
714 core_initcall(vr41xx_icu_init);