arch/mips/vr41xx/common/bcu.c

   1 /*
   2  *  bcu.c, Bus Control Unit routines for the NEC VR4100 series.
   3  *
   4  *  Copyright (C) 2002  MontaVista Software Inc.
   5  *    Author: Yoichi Yuasa <source@mvista.com>
   6  *  Copyright (C) 2003-2005  Yoichi Yuasa <yuasa@linux-mips.org>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 /*
  23  * Changes:
  24  *  MontaVista Software Inc. <source@mvista.com>
  25  *  - New creation, NEC VR4122 and VR4131 are supported.
  26  *  - Added support for NEC VR4111 and VR4121.
  27  *
  28  *  Yoichi Yuasa <yuasa@linux-mips.org>
  29  *  - Added support for NEC VR4133.
  30  */
  31 #include <linux/export.h>
  32 #include <linux/kernel.h>
  33 #include <linux/smp.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/cpu-type.h>
  37 #include <asm/cpu.h>
  38 #include <asm/io.h>
  39
  40 #define CLKSPEEDREG_TYPE1       (void __iomem *)KSEG1ADDR(0x0b000014)
  41 #define CLKSPEEDREG_TYPE2       (void __iomem *)KSEG1ADDR(0x0f000014)
  42  #define CLKSP(x)               ((x) & 0x001f)
  43  #define CLKSP_VR4133(x)        ((x) & 0x0007)
  44
  45  #define DIV2B                  0x8000
  46  #define DIV3B                  0x4000
  47  #define DIV4B                  0x2000
  48
  49  #define DIVT(x)                (((x) & 0xf000) >> 12)
  50  #define DIVVT(x)               (((x) & 0x0f00) >> 8)
  51
  52  #define TDIVMODE(x)            (2 << (((x) & 0x1000) >> 12))
  53  #define VTDIVMODE(x)           (((x) & 0x0700) >> 8)
  54
  55 static unsigned long vr41xx_vtclock;
  56 static unsigned long vr41xx_tclock;
  57
  58 unsigned long vr41xx_get_vtclock_frequency(void)
  59 {
  60         return vr41xx_vtclock;
  61 }
  62
  63 EXPORT_SYMBOL_GPL(vr41xx_get_vtclock_frequency);
  64
  65 unsigned long vr41xx_get_tclock_frequency(void)
  66 {
  67         return vr41xx_tclock;
  68 }
  69
  70 EXPORT_SYMBOL_GPL(vr41xx_get_tclock_frequency);
  71
  72 static inline uint16_t read_clkspeed(void)
  73 {
  74         switch (current_cpu_type()) {
  75         case CPU_VR4111:
  76         case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1);
  77         case CPU_VR4122:
  78         case CPU_VR4131:
  79         case CPU_VR4133: return readw(CLKSPEEDREG_TYPE2);
  80         default:
  81                 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
  82                 break;
  83         }
  84
  85         return 0;
  86 }
  87
  88 static inline unsigned long calculate_pclock(uint16_t clkspeed)
  89 {
  90         unsigned long pclock = 0;
  91
  92         switch (current_cpu_type()) {
  93         case CPU_VR4111:
  94         case CPU_VR4121:
  95                 pclock = 18432000 * 64;
  96                 pclock /= CLKSP(clkspeed);
  97                 break;
  98         case CPU_VR4122:
  99                 pclock = 18432000 * 98;
 100                 pclock /= CLKSP(clkspeed);
 101                 break;
 102         case CPU_VR4131:
 103                 pclock = 18432000 * 108;
 104                 pclock /= CLKSP(clkspeed);
 105                 break;
 106         case CPU_VR4133:
 107                 switch (CLKSP_VR4133(clkspeed)) {
 108                 case 0:
 109                         pclock = 133000000;
 110                         break;
 111                 case 1:
 112                         pclock = 149000000;
 113                         break;
 114                 case 2:
 115                         pclock = 165900000;
 116                         break;
 117                 case 3:
 118                         pclock = 199100000;
 119                         break;
 120                 case 4:
 121                         pclock = 265900000;
 122                         break;
 123                 default:
 124                         printk(KERN_INFO "Unknown PClock speed for NEC VR4133\n");
 125                         break;
 126                 }
 127                 break;
 128         default:
 129                 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 130                 break;
 131         }
 132
 133         printk(KERN_INFO "PClock: %ldHz\n", pclock);
 134
 135         return pclock;
 136 }
 137
 138 static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long pclock)
 139 {
 140         unsigned long vtclock = 0;
 141
 142         switch (current_cpu_type()) {
 143         case CPU_VR4111:
 144                 /* The NEC VR4111 doesn't have the VTClock. */
 145                 break;
 146         case CPU_VR4121:
 147                 vtclock = pclock;
 148                 /* DIVVT == 9 Divide by 1.5 . VTClock = (PClock * 6) / 9 */
 149                 if (DIVVT(clkspeed) == 9)
 150                         vtclock = pclock * 6;
 151                 /* DIVVT == 10 Divide by 2.5 . VTClock = (PClock * 4) / 10 */
 152                 else if (DIVVT(clkspeed) == 10)
 153                         vtclock = pclock * 4;
 154                 vtclock /= DIVVT(clkspeed);
 155                 printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
 156                 break;
 157         case CPU_VR4122:
 158                 if(VTDIVMODE(clkspeed) == 7)
 159                         vtclock = pclock / 1;
 160                 else if(VTDIVMODE(clkspeed) == 1)
 161                         vtclock = pclock / 2;
 162                 else
 163                         vtclock = pclock / VTDIVMODE(clkspeed);
 164                 printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
 165                 break;
 166         case CPU_VR4131:
 167         case CPU_VR4133:
 168                 vtclock = pclock / VTDIVMODE(clkspeed);
 169                 printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
 170                 break;
 171         default:
 172                 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 173                 break;
 174         }
 175
 176         return vtclock;
 177 }
 178
 179 static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pclock,
 180                                              unsigned long vtclock)
 181 {
 182         unsigned long tclock = 0;
 183
 184         switch (current_cpu_type()) {
 185         case CPU_VR4111:
 186                 if (!(clkspeed & DIV2B))
 187                         tclock = pclock / 2;
 188                 else if (!(clkspeed & DIV3B))
 189                         tclock = pclock / 3;
 190                 else if (!(clkspeed & DIV4B))
 191                         tclock = pclock / 4;
 192                 break;
 193         case CPU_VR4121:
 194                 tclock = pclock / DIVT(clkspeed);
 195                 break;
 196         case CPU_VR4122:
 197         case CPU_VR4131:
 198         case CPU_VR4133:
 199                 tclock = vtclock / TDIVMODE(clkspeed);
 200                 break;
 201         default:
 202                 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 203                 break;
 204         }
 205
 206         printk(KERN_INFO "TClock: %ldHz\n", tclock);
 207
 208         return tclock;
 209 }
 210
 211 void vr41xx_calculate_clock_frequency(void)
 212 {
 213         unsigned long pclock;
 214         uint16_t clkspeed;
 215
 216         clkspeed = read_clkspeed();
 217
 218         pclock = calculate_pclock(clkspeed);
 219         vr41xx_vtclock = calculate_vtclock(clkspeed, pclock);
 220         vr41xx_tclock = calculate_tclock(clkspeed, pclock, vr41xx_vtclock);
 221 }
 222
 223 EXPORT_SYMBOL_GPL(vr41xx_calculate_clock_frequency);