arch/mips/ralink/rt305x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  * Parts of this file are based on Ralink's 2.6.21 BSP
   5  *
   6  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   7  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   8  * Copyright (C) 2013 John Crispin <john@phrozen.org>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/bug.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/mipsregs.h>
  17 #include <asm/mach-ralink/ralink_regs.h>
  18 #include <asm/mach-ralink/rt305x.h>
  19
  20 #include "common.h"
  21
  22 static unsigned long rt5350_get_mem_size(void)
  23 {
  24         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  25         unsigned long ret;
  26         u32 t;
  27
  28         t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
  29         t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
  30                 RT5350_SYSCFG0_DRAM_SIZE_MASK;
  31
  32         switch (t) {
  33         case RT5350_SYSCFG0_DRAM_SIZE_2M:
  34                 ret = 2;
  35                 break;
  36         case RT5350_SYSCFG0_DRAM_SIZE_8M:
  37                 ret = 8;
  38                 break;
  39         case RT5350_SYSCFG0_DRAM_SIZE_16M:
  40                 ret = 16;
  41                 break;
  42         case RT5350_SYSCFG0_DRAM_SIZE_32M:
  43                 ret = 32;
  44                 break;
  45         case RT5350_SYSCFG0_DRAM_SIZE_64M:
  46                 ret = 64;
  47                 break;
  48         default:
  49                 panic("rt5350: invalid DRAM size: %u", t);
  50                 break;
  51         }
  52
  53         return ret;
  54 }
  55
  56 void __init ralink_clk_init(void)
  57 {
  58         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  59         unsigned long wmac_rate = 40000000;
  60
  61         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  62
  63         if (soc_is_rt305x() || soc_is_rt3350()) {
  64                 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
  65                      RT305X_SYSCFG_CPUCLK_MASK;
  66                 switch (t) {
  67                 case RT305X_SYSCFG_CPUCLK_LOW:
  68                         cpu_rate = 320000000;
  69                         break;
  70                 case RT305X_SYSCFG_CPUCLK_HIGH:
  71                         cpu_rate = 384000000;
  72                         break;
  73                 }
  74                 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
  75         } else if (soc_is_rt3352()) {
  76                 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
  77                      RT3352_SYSCFG0_CPUCLK_MASK;
  78                 switch (t) {
  79                 case RT3352_SYSCFG0_CPUCLK_LOW:
  80                         cpu_rate = 384000000;
  81                         break;
  82                 case RT3352_SYSCFG0_CPUCLK_HIGH:
  83                         cpu_rate = 400000000;
  84                         break;
  85                 }
  86                 sys_rate = wdt_rate = cpu_rate / 3;
  87                 uart_rate = 40000000;
  88         } else if (soc_is_rt5350()) {
  89                 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
  90                      RT5350_SYSCFG0_CPUCLK_MASK;
  91                 switch (t) {
  92                 case RT5350_SYSCFG0_CPUCLK_360:
  93                         cpu_rate = 360000000;
  94                         sys_rate = cpu_rate / 3;
  95                         break;
  96                 case RT5350_SYSCFG0_CPUCLK_320:
  97                         cpu_rate = 320000000;
  98                         sys_rate = cpu_rate / 4;
  99                         break;
 100                 case RT5350_SYSCFG0_CPUCLK_300:
 101                         cpu_rate = 300000000;
 102                         sys_rate = cpu_rate / 3;
 103                         break;
 104                 default:
 105                         BUG();
 106                 }
 107                 uart_rate = 40000000;
 108                 wdt_rate = sys_rate;
 109         } else {
 110                 BUG();
 111         }
 112
 113         if (soc_is_rt3352() || soc_is_rt5350()) {
 114                 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
 115
 116                 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
 117                         wmac_rate = 20000000;
 118         }
 119
 120         ralink_clk_add("cpu", cpu_rate);
 121         ralink_clk_add("sys", sys_rate);
 122         ralink_clk_add("10000900.i2c", uart_rate);
 123         ralink_clk_add("10000a00.i2s", uart_rate);
 124         ralink_clk_add("10000b00.spi", sys_rate);
 125         ralink_clk_add("10000b40.spi", sys_rate);
 126         ralink_clk_add("10000100.timer", wdt_rate);
 127         ralink_clk_add("10000120.watchdog", wdt_rate);
 128         ralink_clk_add("10000500.uart", uart_rate);
 129         ralink_clk_add("10000c00.uartlite", uart_rate);
 130         ralink_clk_add("10100000.ethernet", sys_rate);
 131         ralink_clk_add("10180000.wmac", wmac_rate);
 132 }
 133
 134 void __init ralink_of_remap(void)
 135 {
 136         rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
 137         rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
 138
 139         if (!rt_sysc_membase || !rt_memc_membase)
 140                 panic("Failed to remap core resources");
 141 }
 142
 143 void __init prom_soc_init(struct ralink_soc_info *soc_info)
 144 {
 145         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
 146         unsigned char *name;
 147         u32 n0;
 148         u32 n1;
 149         u32 id;
 150
 151         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 152         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 153
 154         if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
 155                 unsigned long icache_sets;
 156
 157                 icache_sets = (read_c0_config1() >> 22) & 7;
 158                 if (icache_sets == 1) {
 159                         ralink_soc = RT305X_SOC_RT3050;
 160                         name = "RT3050";
 161                         soc_info->compatible = "ralink,rt3050-soc";
 162                 } else {
 163                         ralink_soc = RT305X_SOC_RT3052;
 164                         name = "RT3052";
 165                         soc_info->compatible = "ralink,rt3052-soc";
 166                 }
 167         } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
 168                 ralink_soc = RT305X_SOC_RT3350;
 169                 name = "RT3350";
 170                 soc_info->compatible = "ralink,rt3350-soc";
 171         } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
 172                 ralink_soc = RT305X_SOC_RT3352;
 173                 name = "RT3352";
 174                 soc_info->compatible = "ralink,rt3352-soc";
 175         } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
 176                 ralink_soc = RT305X_SOC_RT5350;
 177                 name = "RT5350";
 178                 soc_info->compatible = "ralink,rt5350-soc";
 179         } else {
 180                 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
 181         }
 182
 183         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
 184
 185         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 186                 "Ralink %s id:%u rev:%u",
 187                 name,
 188                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 189                 (id & CHIP_ID_REV_MASK));
 190
 191         soc_info->mem_base = RT305X_SDRAM_BASE;
 192         if (soc_is_rt5350()) {
 193                 soc_info->mem_size = rt5350_get_mem_size();
 194         } else if (soc_is_rt305x() || soc_is_rt3350()) {
 195                 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
 196                 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
 197         } else if (soc_is_rt3352()) {
 198                 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
 199                 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
 200         }
 201 }