1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/sys_soc.h>
12 #include <linux/memblock.h>
14 #include <asm/bootinfo.h>
15 #include <asm/mipsregs.h>
16 #include <asm/smp-ops.h>
17 #include <asm/mips-cps.h>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7621.h>
23 #define MT7621_MEM_TEST_PATTERN 0xaa5555aa
25 static u32 detect_magic __initdata;
27 phys_addr_t mips_cpc_default_phys_base(void)
29 panic("Cannot detect cpc address");
32 static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
34 void *dm = (void *)KSEG1ADDR(&detect_magic);
36 if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
38 __raw_writel(MT7621_MEM_TEST_PATTERN, dm);
39 if (__raw_readl(dm) != __raw_readl(dm + size))
41 __raw_writel(~MT7621_MEM_TEST_PATTERN, dm);
42 return __raw_readl(dm) == __raw_readl(dm + size);
45 static void __init mt7621_memory_detect(void)
49 for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
50 if (mt7621_addr_wraparound_test(size)) {
51 memblock_add(MT7621_LOWMEM_BASE, size);
56 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
57 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
60 void __init ralink_of_remap(void)
62 rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
63 rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
65 if (!rt_sysc_membase || !rt_memc_membase)
66 panic("Failed to remap core resources");
69 static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
71 struct soc_device *soc_dev;
72 struct soc_device_attribute *soc_dev_attr;
74 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
78 soc_dev_attr->soc_id = "mt7621";
79 soc_dev_attr->family = "Ralink";
81 if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
82 (rev & CHIP_REV_ECO_MASK) == 1)
83 soc_dev_attr->revision = "E2";
85 soc_dev_attr->revision = "E1";
87 soc_dev_attr->data = soc_info;
89 soc_dev = soc_device_register(soc_dev_attr);
90 if (IS_ERR(soc_dev)) {
96 void __init prom_soc_init(struct ralink_soc_info *soc_info)
98 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
99 unsigned char *name = NULL;
104 /* Early detection of CMP support */
108 if (mips_cps_numiocu(0)) {
110 * mips_cm_probe() wipes out bootloader
111 * config for CM regions and we have to configure them
112 * again. This SoC cannot talk to pamlbus devices
113 * witout proper iocu region set up.
115 * FIXME: it would be better to do this with values
116 * from DT, but we need this very early because
117 * without this we cannot talk to pretty much anything
120 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
121 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
122 CM_GCR_REGn_MASK_CMTGT_IOCU0);
126 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
127 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
129 if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
131 soc_info->compatible = "mediatek,mt7621-soc";
133 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
135 ralink_soc = MT762X_SOC_MT7621AT;
136 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
138 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
139 "MediaTek %s ver:%u eco:%u",
141 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
142 (rev & CHIP_REV_ECO_MASK));
144 soc_info->mem_detect = mt7621_memory_detect;
146 soc_dev_init(soc_info, rev);
148 if (!register_cps_smp_ops())
150 if (!register_cmp_smp_ops())
152 if (!register_vsmp_smp_ops())