arch/mips/ralink/clk.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2013 John Crispin <john@phrozen.org>
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/export.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <asm/mach-ralink/ralink_regs.h>
  15
  16 #include <asm/time.h>
  17
  18 #include "common.h"
  19
  20 static const char *clk_cpu(int *idx)
  21 {
  22         switch (ralink_soc) {
  23         case RT2880_SOC:
  24                 *idx = 0;
  25                 return "ralink,rt2880-sysc";
  26         case RT3883_SOC:
  27                 *idx = 0;
  28                 return "ralink,rt3883-sysc";
  29         case RT305X_SOC_RT3050:
  30                 *idx = 0;
  31                 return "ralink,rt3050-sysc";
  32         case RT305X_SOC_RT3052:
  33                 *idx = 0;
  34                 return "ralink,rt3052-sysc";
  35         case RT305X_SOC_RT3350:
  36                 *idx = 1;
  37                 return "ralink,rt3350-sysc";
  38         case RT305X_SOC_RT3352:
  39                 *idx = 1;
  40                 return "ralink,rt3352-sysc";
  41         case RT305X_SOC_RT5350:
  42                 *idx = 1;
  43                 return "ralink,rt5350-sysc";
  44         case MT762X_SOC_MT7620A:
  45                 *idx = 2;
  46                 return "ralink,mt7620-sysc";
  47         case MT762X_SOC_MT7620N:
  48                 *idx = 2;
  49                 return "ralink,mt7620-sysc";
  50         case MT762X_SOC_MT7628AN:
  51                 *idx = 1;
  52                 return "ralink,mt7628-sysc";
  53         case MT762X_SOC_MT7688:
  54                 *idx = 1;
  55                 return "ralink,mt7688-sysc";
  56         default:
  57                 *idx = -1;
  58                 return "invalid";
  59         }
  60 }
  61
  62 void __init plat_time_init(void)
  63 {
  64         struct of_phandle_args clkspec;
  65         const char *compatible;
  66         struct clk *clk;
  67         int cpu_clk_idx;
  68
  69         ralink_of_remap();
  70
  71         compatible = clk_cpu(&cpu_clk_idx);
  72         if (cpu_clk_idx == -1)
  73                 panic("unable to get CPU clock index");
  74
  75         of_clk_init(NULL);
  76         clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
  77         clkspec.args_count = 1;
  78         clkspec.args[0] = cpu_clk_idx;
  79         clk = of_clk_get_from_provider(&clkspec);
  80         if (IS_ERR(clk))
  81                 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
  82         pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
  83         mips_hpt_frequency = clk_get_rate(clk) / 2;
  84         clk_put(clk);
  85         timer_probe();
  86 }