2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2011 Wind River Systems,
9 * written by Ralf Baechle (ralf@linux-mips.org)
11 #include <linux/bug.h>
12 #include <linux/kernel.h>
14 #include <linux/bootmem.h>
15 #include <linux/export.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/of_address.h>
21 #include <asm/cpu-info.h>
24 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
29 * The PCI controller list.
31 static LIST_HEAD(controllers);
33 static int pci_initialized;
36 * We need to avoid collisions with `mirrored' VGA ports
37 * and other strange ISA hardware, so we always want the
38 * addresses to be allocated in the 0x000-0x0ff region
41 * Why? Because some silly external IO cards only decode
42 * the low 10 bits of the IO address. The 0x00-0xff region
43 * is reserved for motherboard devices that decode all 16
44 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
45 * but we want to try to avoid allocating at 0x2900-0x2bff
46 * which might have be mirrored at 0x0100-0x03ff..
49 pcibios_align_resource(void *data, const struct resource *res,
50 resource_size_t size, resource_size_t align)
52 struct pci_dev *dev = data;
53 struct pci_controller *hose = dev->sysdata;
54 resource_size_t start = res->start;
56 if (res->flags & IORESOURCE_IO) {
57 /* Make sure we start at our min on all hoses */
58 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
59 start = PCIBIOS_MIN_IO + hose->io_resource->start;
62 * Put everything into 0x00-0xff region modulo 0x400
65 start = (start + 0x3ff) & ~0x3ff;
66 } else if (res->flags & IORESOURCE_MEM) {
67 /* Make sure we start at our min on all hoses */
68 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
69 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
75 static void pcibios_scanbus(struct pci_controller *hose)
77 static int next_busno;
78 static int need_domain_info;
82 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
83 next_busno = (*hose->get_busno)();
85 pci_add_resource_offset(&resources,
86 hose->mem_resource, hose->mem_offset);
87 pci_add_resource_offset(&resources,
88 hose->io_resource, hose->io_offset);
89 pci_add_resource_offset(&resources,
90 hose->busn_resource, hose->busn_offset);
91 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
95 need_domain_info = need_domain_info || pci_domain_nr(bus);
96 set_pci_need_domain_info(hose, need_domain_info);
99 pci_free_resource_list(&resources);
103 next_busno = bus->busn_res.end + 1;
104 /* Don't allow 8-bit bus number overflow inside the hose -
105 reserve some space for bridges. */
106 if (next_busno > 224) {
108 need_domain_info = 1;
112 * We insert PCI resources into the iomem_resource and
113 * ioport_resource trees in either pci_bus_claim_resources()
114 * or pci_bus_assign_resources().
116 if (pci_has_flag(PCI_PROBE_ONLY)) {
117 pci_bus_claim_resources(bus);
119 struct pci_bus *child;
121 pci_bus_size_bridges(bus);
122 pci_bus_assign_resources(bus);
123 list_for_each_entry(child, &bus->children, node)
124 pcie_bus_configure_settings(child);
126 pci_bus_add_devices(bus);
130 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
132 struct of_pci_range range;
133 struct of_pci_range_parser parser;
135 pr_info("PCI host bridge %s ranges:\n", node->full_name);
136 hose->of_node = node;
138 if (of_pci_range_parser_init(&parser, node))
141 for_each_of_pci_range(&parser, &range) {
142 struct resource *res = NULL;
144 switch (range.flags & IORESOURCE_TYPE_BITS) {
146 pr_info(" IO 0x%016llx..0x%016llx\n",
148 range.cpu_addr + range.size - 1);
150 (unsigned long)ioremap(range.cpu_addr,
152 res = hose->io_resource;
155 pr_info(" MEM 0x%016llx..0x%016llx\n",
157 range.cpu_addr + range.size - 1);
158 res = hose->mem_resource;
162 res->name = node->full_name;
163 res->flags = range.flags;
164 res->start = range.cpu_addr;
165 res->end = range.cpu_addr + range.size - 1;
166 res->parent = res->child = res->sibling = NULL;
171 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
173 struct pci_controller *hose = bus->sysdata;
175 return of_node_get(hose->of_node);
179 static DEFINE_MUTEX(pci_scan_mutex);
181 void register_pci_controller(struct pci_controller *hose)
183 struct resource *parent;
185 parent = hose->mem_resource->parent;
187 parent = &iomem_resource;
189 if (request_resource(parent, hose->mem_resource) < 0)
192 parent = hose->io_resource->parent;
194 parent = &ioport_resource;
196 if (request_resource(parent, hose->io_resource) < 0) {
197 release_resource(hose->mem_resource);
201 INIT_LIST_HEAD(&hose->list);
202 list_add(&hose->list, &controllers);
205 * Do not panic here but later - this might happen before console init.
207 if (!hose->io_map_base) {
209 "registering PCI controller with io_map_base unset\n");
213 * Scan the bus if it is register after the PCI subsystem
216 if (pci_initialized) {
217 mutex_lock(&pci_scan_mutex);
218 pcibios_scanbus(hose);
219 mutex_unlock(&pci_scan_mutex);
226 "Skipping PCI bus scan due to resource conflict\n");
229 static int __init pcibios_init(void)
231 struct pci_controller *hose;
233 /* Scan all of the recorded PCI controllers. */
234 list_for_each_entry(hose, &controllers, list)
235 pcibios_scanbus(hose);
237 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
244 subsys_initcall(pcibios_init);
246 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
252 pci_read_config_word(dev, PCI_COMMAND, &cmd);
254 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
255 /* Only set up the requested stuff */
256 if (!(mask & (1<<idx)))
259 r = &dev->resource[idx];
260 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
262 if ((idx == PCI_ROM_RESOURCE) &&
263 (!(r->flags & IORESOURCE_ROM_ENABLE)))
265 if (!r->start && r->end) {
266 printk(KERN_ERR "PCI: Device %s not available "
267 "because of resource collisions\n",
271 if (r->flags & IORESOURCE_IO)
272 cmd |= PCI_COMMAND_IO;
273 if (r->flags & IORESOURCE_MEM)
274 cmd |= PCI_COMMAND_MEMORY;
276 if (cmd != old_cmd) {
277 printk("PCI: Enabling device %s (%04x -> %04x)\n",
278 pci_name(dev), old_cmd, cmd);
279 pci_write_config_word(dev, PCI_COMMAND, cmd);
284 int pcibios_enable_device(struct pci_dev *dev, int mask)
288 if ((err = pcibios_enable_resources(dev, mask)) < 0)
291 return pcibios_plat_dev_init(dev);
294 void pcibios_fixup_bus(struct pci_bus *bus)
296 struct pci_dev *dev = bus->self;
298 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
299 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
300 pci_read_bridge_bases(bus);
304 char * (*pcibios_plat_setup)(char *str) __initdata;
306 char *__init pcibios_setup(char *str)
308 if (pcibios_plat_setup)
309 return pcibios_plat_setup(str);