2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completely out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/cache.h>
31 #include <asm/cacheflush.h>
32 #include <asm/cpu-type.h>
33 #include <asm/pgtable.h>
36 #include <asm/setup.h>
38 static int mips_xpa_disabled;
40 static int __init xpa_disable(char *s)
42 mips_xpa_disabled = 1;
47 __setup("noxpa", xpa_disable);
50 * TLB load/store/modify handlers.
52 * Only the fastpath gets synthesized at runtime, the slowpath for
53 * do_page_fault remains normal asm.
55 extern void tlb_do_page_fault_0(void);
56 extern void tlb_do_page_fault_1(void);
58 struct work_registers {
67 } ____cacheline_aligned_in_smp;
69 static struct tlb_reg_save handler_reg_save[NR_CPUS];
71 static inline int r45k_bvahwbug(void)
73 /* XXX: We should probe for the presence of this bug, but we don't. */
77 static inline int r4k_250MHZhwbug(void)
79 /* XXX: We should probe for the presence of this bug, but we don't. */
83 static inline int __maybe_unused bcm1250_m3_war(void)
85 return BCM1250_M3_WAR;
88 static inline int __maybe_unused r10000_llsc_war(void)
90 return R10000_LLSC_WAR;
93 static int use_bbit_insns(void)
95 switch (current_cpu_type()) {
96 case CPU_CAVIUM_OCTEON:
97 case CPU_CAVIUM_OCTEON_PLUS:
98 case CPU_CAVIUM_OCTEON2:
99 case CPU_CAVIUM_OCTEON3:
106 static int use_lwx_insns(void)
108 switch (current_cpu_type()) {
109 case CPU_CAVIUM_OCTEON2:
110 case CPU_CAVIUM_OCTEON3:
116 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
117 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
118 static bool scratchpad_available(void)
122 static int scratchpad_offset(int i)
125 * CVMSEG starts at address -32768 and extends for
126 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
128 i += 1; /* Kernel use starts at the top and works down. */
129 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
132 static bool scratchpad_available(void)
136 static int scratchpad_offset(int i)
139 /* Really unreachable, but evidently some GCC want this. */
144 * Found by experiment: At least some revisions of the 4kc throw under
145 * some circumstances a machine check exception, triggered by invalid
146 * values in the index register. Delaying the tlbp instruction until
147 * after the next branch, plus adding an additional nop in front of
148 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
149 * why; it's not an issue caused by the core RTL.
152 static int m4kc_tlbp_war(void)
154 return (current_cpu_data.processor_id & 0xffff00) ==
155 (PRID_COMP_MIPS | PRID_IMP_4KC);
158 /* Handle labels (which must be positive integers). */
160 label_second_part = 1,
165 label_split = label_tlbw_hazard_0 + 8,
166 label_tlbl_goaround1,
167 label_tlbl_goaround2,
171 label_smp_pgtable_change,
172 label_r3000_write_probe_fail,
173 label_large_segbits_fault,
174 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
175 label_tlb_huge_update,
179 UASM_L_LA(_second_part)
182 UASM_L_LA(_vmalloc_done)
183 /* _tlbw_hazard_x is handled differently. */
185 UASM_L_LA(_tlbl_goaround1)
186 UASM_L_LA(_tlbl_goaround2)
187 UASM_L_LA(_nopage_tlbl)
188 UASM_L_LA(_nopage_tlbs)
189 UASM_L_LA(_nopage_tlbm)
190 UASM_L_LA(_smp_pgtable_change)
191 UASM_L_LA(_r3000_write_probe_fail)
192 UASM_L_LA(_large_segbits_fault)
193 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
194 UASM_L_LA(_tlb_huge_update)
197 static int hazard_instance;
199 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
203 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
210 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
214 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
222 * pgtable bits are assigned dynamically depending on processor feature
223 * and statically based on kernel configuration. This spits out the actual
224 * values the kernel is using. Required to make sense from disassembled
225 * TLB exception handlers.
227 static void output_pgtable_bits_defines(void)
229 #define pr_define(fmt, ...) \
230 pr_debug("#define " fmt, ##__VA_ARGS__)
232 pr_debug("#include <asm/asm.h>\n");
233 pr_debug("#include <asm/regdef.h>\n");
236 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
237 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
238 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
239 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
240 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
241 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
242 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
244 #ifdef _PAGE_NO_EXEC_SHIFT
246 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
248 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
249 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
250 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
251 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
255 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
259 pr_debug("LEAF(%s)\n", symbol);
261 pr_debug("\t.set push\n");
262 pr_debug("\t.set noreorder\n");
264 for (i = 0; i < count; i++)
265 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
267 pr_debug("\t.set\tpop\n");
269 pr_debug("\tEND(%s)\n", symbol);
272 /* The only general purpose registers allowed in TLB handlers. */
276 /* Some CP0 registers */
277 #define C0_INDEX 0, 0
278 #define C0_ENTRYLO0 2, 0
279 #define C0_TCBIND 2, 2
280 #define C0_ENTRYLO1 3, 0
281 #define C0_CONTEXT 4, 0
282 #define C0_PAGEMASK 5, 0
283 #define C0_PWBASE 5, 5
284 #define C0_PWFIELD 5, 6
285 #define C0_PWSIZE 5, 7
286 #define C0_PWCTL 6, 6
287 #define C0_BADVADDR 8, 0
289 #define C0_ENTRYHI 10, 0
291 #define C0_XCONTEXT 20, 0
294 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
296 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
299 /* The worst case length of the handler is around 18 instructions for
300 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
301 * Maximum space available is 32 instructions for R3000 and 64
302 * instructions for R4000.
304 * We deliberately chose a buffer size of 128, so we won't scribble
305 * over anything important on overflow before we panic.
307 static u32 tlb_handler[128];
309 /* simply assume worst case size for labels and relocs */
310 static struct uasm_label labels[128];
311 static struct uasm_reloc relocs[128];
313 static int check_for_high_segbits;
314 static bool fill_includes_sw_bits;
316 static unsigned int kscratch_used_mask;
318 static inline int __maybe_unused c0_kscratch(void)
320 switch (current_cpu_type()) {
329 static int allocate_kscratch(void)
332 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
339 r--; /* make it zero based */
341 kscratch_used_mask |= (1 << r);
346 static int scratch_reg;
348 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
350 static struct work_registers build_get_work_registers(u32 **p)
352 struct work_registers r;
354 if (scratch_reg >= 0) {
355 /* Save in CPU local C0_KScratch? */
356 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
363 if (num_possible_cpus() > 1) {
364 /* Get smp_processor_id */
365 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
366 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
368 /* handler_reg_save index in K0 */
369 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
371 UASM_i_LA(p, K1, (long)&handler_reg_save);
372 UASM_i_ADDU(p, K0, K0, K1);
374 UASM_i_LA(p, K0, (long)&handler_reg_save);
376 /* K0 now points to save area, save $1 and $2 */
377 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
378 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
386 static void build_restore_work_registers(u32 **p)
388 if (scratch_reg >= 0) {
390 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
393 /* K0 already points to save area, restore $1 and $2 */
394 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
395 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
398 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
401 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
402 * we cannot do r3000 under these circumstances.
404 * Declare pgd_current here instead of including mmu_context.h to avoid type
405 * conflicts for tlbmiss_handler_setup_pgd
407 extern unsigned long pgd_current[];
410 * The R3000 TLB handler is simple.
412 static void build_r3000_tlb_refill_handler(void)
414 long pgdc = (long)pgd_current;
417 memset(tlb_handler, 0, sizeof(tlb_handler));
420 uasm_i_mfc0(&p, K0, C0_BADVADDR);
421 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
422 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
423 uasm_i_srl(&p, K0, K0, 22); /* load delay */
424 uasm_i_sll(&p, K0, K0, 2);
425 uasm_i_addu(&p, K1, K1, K0);
426 uasm_i_mfc0(&p, K0, C0_CONTEXT);
427 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
428 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
429 uasm_i_addu(&p, K1, K1, K0);
430 uasm_i_lw(&p, K0, 0, K1);
431 uasm_i_nop(&p); /* load delay */
432 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
433 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
434 uasm_i_tlbwr(&p); /* cp0 delay */
436 uasm_i_rfe(&p); /* branch delay */
438 if (p > tlb_handler + 32)
439 panic("TLB refill handler space exceeded");
441 pr_debug("Wrote TLB refill handler (%u instructions).\n",
442 (unsigned int)(p - tlb_handler));
444 memcpy((void *)ebase, tlb_handler, 0x80);
445 local_flush_icache_range(ebase, ebase + 0x80);
447 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
449 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
452 * The R4000 TLB handler is much more complicated. We have two
453 * consecutive handler areas with 32 instructions space each.
454 * Since they aren't used at the same time, we can overflow in the
455 * other one.To keep things simple, we first assume linear space,
456 * then we relocate it to the final handler layout as needed.
458 static u32 final_handler[64];
463 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
464 * 2. A timing hazard exists for the TLBP instruction.
466 * stalling_instruction
469 * The JTLB is being read for the TLBP throughout the stall generated by the
470 * previous instruction. This is not really correct as the stalling instruction
471 * can modify the address used to access the JTLB. The failure symptom is that
472 * the TLBP instruction will use an address created for the stalling instruction
473 * and not the address held in C0_ENHI and thus report the wrong results.
475 * The software work-around is to not allow the instruction preceding the TLBP
476 * to stall - make it an NOP or some other instruction guaranteed not to stall.
478 * Errata 2 will not be fixed. This errata is also on the R5000.
480 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
482 static void __maybe_unused build_tlb_probe_entry(u32 **p)
484 switch (current_cpu_type()) {
485 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
501 * Write random or indexed TLB entry, and care about the hazards from
502 * the preceding mtc0 and for the following eret.
504 enum tlb_write_entry { tlb_random, tlb_indexed };
506 static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
507 struct uasm_reloc **r,
508 enum tlb_write_entry wmode)
510 void(*tlbw)(u32 **) = NULL;
513 case tlb_random: tlbw = uasm_i_tlbwr; break;
514 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
517 if (cpu_has_mips_r2_r6) {
518 if (cpu_has_mips_r2_exec_hazard)
524 switch (current_cpu_type()) {
532 * This branch uses up a mtc0 hazard nop slot and saves
533 * two nops after the tlbw instruction.
535 uasm_bgezl_hazard(p, r, hazard_instance);
537 uasm_bgezl_label(l, p, hazard_instance);
551 uasm_i_nop(p); /* QED specifies 2 nops hazard */
552 uasm_i_nop(p); /* QED specifies 2 nops hazard */
626 panic("No TLB refill handler yet (CPU type: %d)",
632 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
635 if (_PAGE_GLOBAL_SHIFT == 0) {
636 /* pte_t is already in EntryLo format */
640 if (cpu_has_rixi && !!_PAGE_NO_EXEC) {
641 if (fill_includes_sw_bits) {
642 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
644 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
645 UASM_i_ROTR(p, reg, reg,
646 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
649 #ifdef CONFIG_PHYS_ADDR_T_64BIT
650 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
652 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
657 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
659 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
660 unsigned int tmp, enum label_id lid,
663 if (restore_scratch) {
665 * Ensure the MFC0 below observes the value written to the
666 * KScratch register by the prior MTC0.
668 if (scratch_reg >= 0)
671 /* Reset default page size */
672 if (PM_DEFAULT_MASK >> 16) {
673 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
674 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
675 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
676 uasm_il_b(p, r, lid);
677 } else if (PM_DEFAULT_MASK) {
678 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
679 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
680 uasm_il_b(p, r, lid);
682 uasm_i_mtc0(p, 0, C0_PAGEMASK);
683 uasm_il_b(p, r, lid);
685 if (scratch_reg >= 0)
686 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
688 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
690 /* Reset default page size */
691 if (PM_DEFAULT_MASK >> 16) {
692 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
693 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
694 uasm_il_b(p, r, lid);
695 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
696 } else if (PM_DEFAULT_MASK) {
697 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
698 uasm_il_b(p, r, lid);
699 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
701 uasm_il_b(p, r, lid);
702 uasm_i_mtc0(p, 0, C0_PAGEMASK);
707 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
708 struct uasm_reloc **r,
710 enum tlb_write_entry wmode,
713 /* Set huge page tlb entry size */
714 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
715 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
716 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
718 build_tlb_write_entry(p, l, r, wmode);
720 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
724 * Check if Huge PTE is present, if so then jump to LABEL.
727 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
728 unsigned int pmd, int lid)
730 UASM_i_LW(p, tmp, 0, pmd);
731 if (use_bbit_insns()) {
732 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
734 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
735 uasm_il_bnez(p, r, tmp, lid);
739 static void build_huge_update_entries(u32 **p, unsigned int pte,
745 * A huge PTE describes an area the size of the
746 * configured huge page size. This is twice the
747 * of the large TLB entry size we intend to use.
748 * A TLB entry half the size of the configured
749 * huge page size is configured into entrylo0
750 * and entrylo1 to cover the contiguous huge PTE
753 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
755 /* We can clobber tmp. It isn't used after this.*/
757 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
759 build_convert_pte_to_entrylo(p, pte);
760 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
761 /* convert to entrylo1 */
763 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
765 UASM_i_ADDU(p, pte, pte, tmp);
767 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
770 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
771 struct uasm_label **l,
777 UASM_i_SC(p, pte, 0, ptr);
778 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
779 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
781 UASM_i_SW(p, pte, 0, ptr);
783 if (cpu_has_ftlb && flush) {
784 BUG_ON(!cpu_has_tlbinv);
786 UASM_i_MFC0(p, ptr, C0_ENTRYHI);
787 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
788 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
789 build_tlb_write_entry(p, l, r, tlb_indexed);
791 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
792 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
793 build_huge_update_entries(p, pte, ptr);
794 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
799 build_huge_update_entries(p, pte, ptr);
800 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
802 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
806 * TMP and PTR are scratch.
807 * TMP will be clobbered, PTR will hold the pmd entry.
810 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
811 unsigned int tmp, unsigned int ptr)
813 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
814 long pgdc = (long)pgd_current;
817 * The vmalloc handling is not in the hotpath.
819 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
821 if (check_for_high_segbits) {
823 * The kernel currently implicitely assumes that the
824 * MIPS SEGBITS parameter for the processor is
825 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
826 * allocate virtual addresses outside the maximum
827 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
828 * that doesn't prevent user code from accessing the
829 * higher xuseg addresses. Here, we make sure that
830 * everything but the lower xuseg addresses goes down
831 * the module_alloc/vmalloc path.
833 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
834 uasm_il_bnez(p, r, ptr, label_vmalloc);
836 uasm_il_bltz(p, r, tmp, label_vmalloc);
838 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
841 /* pgd is in pgd_reg */
843 UASM_i_MFC0(p, ptr, C0_PWBASE);
845 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
847 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
849 * &pgd << 11 stored in CONTEXT [23..63].
851 UASM_i_MFC0(p, ptr, C0_CONTEXT);
853 /* Clear lower 23 bits of context. */
854 uasm_i_dins(p, ptr, 0, 0, 23);
856 /* 1 0 1 0 1 << 6 xkphys cached */
857 uasm_i_ori(p, ptr, ptr, 0x540);
858 uasm_i_drotr(p, ptr, ptr, 11);
859 #elif defined(CONFIG_SMP)
860 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
861 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
862 UASM_i_LA_mostly(p, tmp, pgdc);
863 uasm_i_daddu(p, ptr, ptr, tmp);
864 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
865 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
867 UASM_i_LA_mostly(p, ptr, pgdc);
868 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
872 uasm_l_vmalloc_done(l, *p);
874 /* get pgd offset in bytes */
875 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
877 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
878 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
879 #ifndef __PAGETABLE_PMD_FOLDED
880 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
881 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
882 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
883 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
884 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
889 * BVADDR is the faulting address, PTR is scratch.
890 * PTR will hold the pgd for vmalloc.
893 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
894 unsigned int bvaddr, unsigned int ptr,
895 enum vmalloc64_mode mode)
897 long swpd = (long)swapper_pg_dir;
898 int single_insn_swpd;
899 int did_vmalloc_branch = 0;
901 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
903 uasm_l_vmalloc(l, *p);
905 if (mode != not_refill && check_for_high_segbits) {
906 if (single_insn_swpd) {
907 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
908 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
909 did_vmalloc_branch = 1;
912 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
915 if (!did_vmalloc_branch) {
916 if (single_insn_swpd) {
917 uasm_il_b(p, r, label_vmalloc_done);
918 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
920 UASM_i_LA_mostly(p, ptr, swpd);
921 uasm_il_b(p, r, label_vmalloc_done);
922 if (uasm_in_compat_space_p(swpd))
923 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
925 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
928 if (mode != not_refill && check_for_high_segbits) {
929 uasm_l_large_segbits_fault(l, *p);
931 if (mode == refill_scratch && scratch_reg >= 0)
935 * We get here if we are an xsseg address, or if we are
936 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
938 * Ignoring xsseg (assume disabled so would generate
939 * (address errors?), the only remaining possibility
940 * is the upper xuseg addresses. On processors with
941 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
942 * addresses would have taken an address error. We try
943 * to mimic that here by taking a load/istream page
946 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
949 if (mode == refill_scratch) {
950 if (scratch_reg >= 0)
951 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
953 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
960 #else /* !CONFIG_64BIT */
963 * TMP and PTR are scratch.
964 * TMP will be clobbered, PTR will hold the pgd entry.
966 static void __maybe_unused
967 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
970 /* pgd is in pgd_reg */
971 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
972 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
974 long pgdc = (long)pgd_current;
976 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
978 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
979 UASM_i_LA_mostly(p, tmp, pgdc);
980 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
981 uasm_i_addu(p, ptr, tmp, ptr);
983 UASM_i_LA_mostly(p, ptr, pgdc);
985 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
986 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
988 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
989 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
990 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
993 #endif /* !CONFIG_64BIT */
995 static void build_adjust_context(u32 **p, unsigned int ctx)
997 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
998 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1000 switch (current_cpu_type()) {
1017 UASM_i_SRL(p, ctx, ctx, shift);
1018 uasm_i_andi(p, ctx, ctx, mask);
1021 static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1024 * Bug workaround for the Nevada. It seems as if under certain
1025 * circumstances the move from cp0_context might produce a
1026 * bogus result when the mfc0 instruction and its consumer are
1027 * in a different cacheline or a load instruction, probably any
1028 * memory reference, is between them.
1030 switch (current_cpu_type()) {
1032 UASM_i_LW(p, ptr, 0, ptr);
1033 GET_CONTEXT(p, tmp); /* get context reg */
1037 GET_CONTEXT(p, tmp); /* get context reg */
1038 UASM_i_LW(p, ptr, 0, ptr);
1042 build_adjust_context(p, tmp);
1043 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1046 static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1048 int pte_off_even = 0;
1049 int pte_off_odd = sizeof(pte_t);
1051 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1052 /* The low 32 bits of EntryLo is stored in pte_high */
1053 pte_off_even += offsetof(pte_t, pte_high);
1054 pte_off_odd += offsetof(pte_t, pte_high);
1057 if (IS_ENABLED(CONFIG_XPA)) {
1058 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1059 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1060 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1062 if (cpu_has_xpa && !mips_xpa_disabled) {
1063 uasm_i_lw(p, tmp, 0, ptep);
1064 uasm_i_ext(p, tmp, tmp, 0, 24);
1065 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1068 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
1069 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1070 UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
1072 if (cpu_has_xpa && !mips_xpa_disabled) {
1073 uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
1074 uasm_i_ext(p, tmp, tmp, 0, 24);
1075 uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
1080 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
1081 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
1082 if (r45k_bvahwbug())
1083 build_tlb_probe_entry(p);
1084 build_convert_pte_to_entrylo(p, tmp);
1085 if (r4k_250MHZhwbug())
1086 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1087 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1088 build_convert_pte_to_entrylo(p, ptep);
1089 if (r45k_bvahwbug())
1090 uasm_i_mfc0(p, tmp, C0_INDEX);
1091 if (r4k_250MHZhwbug())
1092 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1093 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1096 struct mips_huge_tlb_info {
1098 int restore_scratch;
1099 bool need_reload_pte;
1102 static struct mips_huge_tlb_info
1103 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1104 struct uasm_reloc **r, unsigned int tmp,
1105 unsigned int ptr, int c0_scratch_reg)
1107 struct mips_huge_tlb_info rv;
1108 unsigned int even, odd;
1109 int vmalloc_branch_delay_filled = 0;
1110 const int scratch = 1; /* Our extra working register */
1112 rv.huge_pte = scratch;
1113 rv.restore_scratch = 0;
1114 rv.need_reload_pte = false;
1116 if (check_for_high_segbits) {
1117 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1120 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1122 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1124 if (c0_scratch_reg >= 0)
1125 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1127 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1129 uasm_i_dsrl_safe(p, scratch, tmp,
1130 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1131 uasm_il_bnez(p, r, scratch, label_vmalloc);
1133 if (pgd_reg == -1) {
1134 vmalloc_branch_delay_filled = 1;
1135 /* Clear lower 23 bits of context. */
1136 uasm_i_dins(p, ptr, 0, 0, 23);
1140 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1142 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1144 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1146 if (c0_scratch_reg >= 0)
1147 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1149 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1152 /* Clear lower 23 bits of context. */
1153 uasm_i_dins(p, ptr, 0, 0, 23);
1155 uasm_il_bltz(p, r, tmp, label_vmalloc);
1158 if (pgd_reg == -1) {
1159 vmalloc_branch_delay_filled = 1;
1160 /* 1 0 1 0 1 << 6 xkphys cached */
1161 uasm_i_ori(p, ptr, ptr, 0x540);
1162 uasm_i_drotr(p, ptr, ptr, 11);
1165 #ifdef __PAGETABLE_PMD_FOLDED
1166 #define LOC_PTEP scratch
1168 #define LOC_PTEP ptr
1171 if (!vmalloc_branch_delay_filled)
1172 /* get pgd offset in bytes */
1173 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1175 uasm_l_vmalloc_done(l, *p);
1179 * fall-through case = badvaddr *pgd_current
1180 * vmalloc case = badvaddr swapper_pg_dir
1183 if (vmalloc_branch_delay_filled)
1184 /* get pgd offset in bytes */
1185 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1187 #ifdef __PAGETABLE_PMD_FOLDED
1188 GET_CONTEXT(p, tmp); /* get context reg */
1190 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1192 if (use_lwx_insns()) {
1193 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1195 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1196 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1199 #ifndef __PAGETABLE_PMD_FOLDED
1200 /* get pmd offset in bytes */
1201 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1202 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1203 GET_CONTEXT(p, tmp); /* get context reg */
1205 if (use_lwx_insns()) {
1206 UASM_i_LWX(p, scratch, scratch, ptr);
1208 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1209 UASM_i_LW(p, scratch, 0, ptr);
1212 /* Adjust the context during the load latency. */
1213 build_adjust_context(p, tmp);
1215 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1216 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1218 * The in the LWX case we don't want to do the load in the
1219 * delay slot. It cannot issue in the same cycle and may be
1220 * speculative and unneeded.
1222 if (use_lwx_insns())
1224 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1227 /* build_update_entries */
1228 if (use_lwx_insns()) {
1231 UASM_i_LWX(p, even, scratch, tmp);
1232 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1233 UASM_i_LWX(p, odd, scratch, tmp);
1235 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1238 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1239 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1242 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1243 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1244 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1246 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1247 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1248 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1250 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1252 if (c0_scratch_reg >= 0) {
1254 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1255 build_tlb_write_entry(p, l, r, tlb_random);
1256 uasm_l_leave(l, *p);
1257 rv.restore_scratch = 1;
1258 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1259 build_tlb_write_entry(p, l, r, tlb_random);
1260 uasm_l_leave(l, *p);
1261 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1263 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1264 build_tlb_write_entry(p, l, r, tlb_random);
1265 uasm_l_leave(l, *p);
1266 rv.restore_scratch = 1;
1269 uasm_i_eret(p); /* return from trap */
1275 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1276 * because EXL == 0. If we wrap, we can also use the 32 instruction
1277 * slots before the XTLB refill exception handler which belong to the
1278 * unused TLB refill exception.
1280 #define MIPS64_REFILL_INSNS 32
1282 static void build_r4000_tlb_refill_handler(void)
1284 u32 *p = tlb_handler;
1285 struct uasm_label *l = labels;
1286 struct uasm_reloc *r = relocs;
1288 unsigned int final_len;
1289 struct mips_huge_tlb_info htlb_info __maybe_unused;
1290 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1292 memset(tlb_handler, 0, sizeof(tlb_handler));
1293 memset(labels, 0, sizeof(labels));
1294 memset(relocs, 0, sizeof(relocs));
1295 memset(final_handler, 0, sizeof(final_handler));
1297 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1298 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1300 vmalloc_mode = refill_scratch;
1302 htlb_info.huge_pte = K0;
1303 htlb_info.restore_scratch = 0;
1304 htlb_info.need_reload_pte = true;
1305 vmalloc_mode = refill_noscratch;
1307 * create the plain linear handler
1309 if (bcm1250_m3_war()) {
1310 unsigned int segbits = 44;
1312 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1313 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1314 uasm_i_xor(&p, K0, K0, K1);
1315 uasm_i_dsrl_safe(&p, K1, K0, 62);
1316 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1317 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1318 uasm_i_or(&p, K0, K0, K1);
1319 uasm_il_bnez(&p, &r, K0, label_leave);
1320 /* No need for uasm_i_nop */
1324 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1326 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1329 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1330 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1333 build_get_ptep(&p, K0, K1);
1334 build_update_entries(&p, K0, K1);
1335 build_tlb_write_entry(&p, &l, &r, tlb_random);
1336 uasm_l_leave(&l, p);
1337 uasm_i_eret(&p); /* return from trap */
1339 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1340 uasm_l_tlb_huge_update(&l, p);
1341 if (htlb_info.need_reload_pte)
1342 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1343 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1344 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1345 htlb_info.restore_scratch);
1349 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1353 * Overflow check: For the 64bit handler, we need at least one
1354 * free instruction slot for the wrap-around branch. In worst
1355 * case, if the intended insertion point is a delay slot, we
1356 * need three, with the second nop'ed and the third being
1359 switch (boot_cpu_type()) {
1361 if (sizeof(long) == 4) {
1363 /* Loongson2 ebase is different than r4k, we have more space */
1364 if ((p - tlb_handler) > 64)
1365 panic("TLB refill handler space exceeded");
1367 * Now fold the handler in the TLB refill handler space.
1370 /* Simplest case, just copy the handler. */
1371 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1372 final_len = p - tlb_handler;
1375 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1376 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1377 && uasm_insn_has_bdelay(relocs,
1378 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1379 panic("TLB refill handler space exceeded");
1381 * Now fold the handler in the TLB refill handler space.
1383 f = final_handler + MIPS64_REFILL_INSNS;
1384 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1385 /* Just copy the handler. */
1386 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1387 final_len = p - tlb_handler;
1389 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1390 const enum label_id ls = label_tlb_huge_update;
1392 const enum label_id ls = label_vmalloc;
1398 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1400 BUG_ON(i == ARRAY_SIZE(labels));
1401 split = labels[i].addr;
1404 * See if we have overflown one way or the other.
1406 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1407 split < p - MIPS64_REFILL_INSNS)
1412 * Split two instructions before the end. One
1413 * for the branch and one for the instruction
1414 * in the delay slot.
1416 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1419 * If the branch would fall in a delay slot,
1420 * we must back up an additional instruction
1421 * so that it is no longer in a delay slot.
1423 if (uasm_insn_has_bdelay(relocs, split - 1))
1426 /* Copy first part of the handler. */
1427 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1428 f += split - tlb_handler;
1431 /* Insert branch. */
1432 uasm_l_split(&l, final_handler);
1433 uasm_il_b(&f, &r, label_split);
1434 if (uasm_insn_has_bdelay(relocs, split))
1437 uasm_copy_handler(relocs, labels,
1438 split, split + 1, f);
1439 uasm_move_labels(labels, f, f + 1, -1);
1445 /* Copy the rest of the handler. */
1446 uasm_copy_handler(relocs, labels, split, p, final_handler);
1447 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1454 uasm_resolve_relocs(relocs, labels);
1455 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1458 memcpy((void *)ebase, final_handler, 0x100);
1459 local_flush_icache_range(ebase, ebase + 0x100);
1461 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1464 static void setup_pw(void)
1466 unsigned long pgd_i, pgd_w;
1467 #ifndef __PAGETABLE_PMD_FOLDED
1468 unsigned long pmd_i, pmd_w;
1470 unsigned long pt_i, pt_w;
1471 unsigned long pte_i, pte_w;
1472 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1475 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
1477 pgd_i = PGDIR_SHIFT; /* 1st level PGD */
1478 #ifndef __PAGETABLE_PMD_FOLDED
1479 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
1481 pmd_i = PMD_SHIFT; /* 2nd level PMD */
1482 pmd_w = PMD_SHIFT - PAGE_SHIFT;
1484 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
1487 pt_i = PAGE_SHIFT; /* 3rd level PTE */
1488 pt_w = PAGE_SHIFT - 3;
1490 pte_i = ilog2(_PAGE_GLOBAL);
1493 #ifndef __PAGETABLE_PMD_FOLDED
1494 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
1495 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
1497 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
1498 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
1501 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1502 write_c0_pwctl(1 << 6 | psn);
1504 write_c0_kpgd(swapper_pg_dir);
1505 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
1508 static void build_loongson3_tlb_refill_handler(void)
1510 u32 *p = tlb_handler;
1511 struct uasm_label *l = labels;
1512 struct uasm_reloc *r = relocs;
1514 memset(labels, 0, sizeof(labels));
1515 memset(relocs, 0, sizeof(relocs));
1516 memset(tlb_handler, 0, sizeof(tlb_handler));
1518 if (check_for_high_segbits) {
1519 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1520 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1521 uasm_il_beqz(&p, &r, K1, label_vmalloc);
1524 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
1526 uasm_l_vmalloc(&l, p);
1529 uasm_i_dmfc0(&p, K1, C0_PGD);
1531 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
1532 #ifndef __PAGETABLE_PMD_FOLDED
1533 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
1535 uasm_i_ldpte(&p, K1, 0); /* even */
1536 uasm_i_ldpte(&p, K1, 1); /* odd */
1539 /* restore page mask */
1540 if (PM_DEFAULT_MASK >> 16) {
1541 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
1542 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
1543 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1544 } else if (PM_DEFAULT_MASK) {
1545 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
1546 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1548 uasm_i_mtc0(&p, 0, C0_PAGEMASK);
1553 if (check_for_high_segbits) {
1554 uasm_l_large_segbits_fault(&l, p);
1555 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
1560 uasm_resolve_relocs(relocs, labels);
1561 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
1562 local_flush_icache_range(ebase + 0x80, ebase + 0x100);
1563 dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32);
1566 extern u32 handle_tlbl[], handle_tlbl_end[];
1567 extern u32 handle_tlbs[], handle_tlbs_end[];
1568 extern u32 handle_tlbm[], handle_tlbm_end[];
1569 extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
1570 extern u32 tlbmiss_handler_setup_pgd_end[];
1572 static void build_setup_pgd(void)
1575 const int __maybe_unused a1 = 5;
1576 const int __maybe_unused a2 = 6;
1577 u32 *p = tlbmiss_handler_setup_pgd_start;
1578 const int tlbmiss_handler_setup_pgd_size =
1579 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1580 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1581 long pgdc = (long)pgd_current;
1584 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1585 sizeof(tlbmiss_handler_setup_pgd[0]));
1586 memset(labels, 0, sizeof(labels));
1587 memset(relocs, 0, sizeof(relocs));
1588 pgd_reg = allocate_kscratch();
1589 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1590 if (pgd_reg == -1) {
1591 struct uasm_label *l = labels;
1592 struct uasm_reloc *r = relocs;
1594 /* PGD << 11 in c0_Context */
1596 * If it is a ckseg0 address, convert to a physical
1597 * address. Shifting right by 29 and adding 4 will
1598 * result in zero for these addresses.
1601 UASM_i_SRA(&p, a1, a0, 29);
1602 UASM_i_ADDIU(&p, a1, a1, 4);
1603 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1605 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1606 uasm_l_tlbl_goaround1(&l, p);
1607 UASM_i_SLL(&p, a0, a0, 11);
1608 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1612 /* PGD in c0_KScratch */
1614 UASM_i_MTC0(&p, a0, C0_PWBASE);
1616 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1622 /* Save PGD to pgd_current[smp_processor_id()] */
1623 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1624 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1625 UASM_i_LA_mostly(&p, a2, pgdc);
1626 UASM_i_ADDU(&p, a2, a2, a1);
1627 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1629 UASM_i_LA_mostly(&p, a2, pgdc);
1630 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1633 /* if pgd_reg is allocated, save PGD also to scratch register */
1634 if (pgd_reg != -1) {
1635 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1643 if (p >= tlbmiss_handler_setup_pgd_end)
1644 panic("tlbmiss_handler_setup_pgd space exceeded");
1646 uasm_resolve_relocs(relocs, labels);
1647 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1648 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1650 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1651 tlbmiss_handler_setup_pgd_size);
1655 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1658 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1660 uasm_i_lld(p, pte, 0, ptr);
1663 UASM_i_LL(p, pte, 0, ptr);
1665 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1667 uasm_i_ld(p, pte, 0, ptr);
1670 UASM_i_LW(p, pte, 0, ptr);
1675 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1676 unsigned int mode, unsigned int scratch)
1678 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1679 unsigned int swmode = mode & ~hwmode;
1681 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
1682 uasm_i_lui(p, scratch, swmode >> 16);
1683 uasm_i_or(p, pte, pte, scratch);
1684 BUG_ON(swmode & 0xffff);
1686 uasm_i_ori(p, pte, pte, mode);
1690 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1692 uasm_i_scd(p, pte, 0, ptr);
1695 UASM_i_SC(p, pte, 0, ptr);
1697 if (r10000_llsc_war())
1698 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1700 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1702 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1703 if (!cpu_has_64bits) {
1704 /* no uasm_i_nop needed */
1705 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1706 uasm_i_ori(p, pte, pte, hwmode);
1707 BUG_ON(hwmode & ~0xffff);
1708 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1709 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1710 /* no uasm_i_nop needed */
1711 uasm_i_lw(p, pte, 0, ptr);
1718 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1720 uasm_i_sd(p, pte, 0, ptr);
1723 UASM_i_SW(p, pte, 0, ptr);
1725 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1726 if (!cpu_has_64bits) {
1727 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1728 uasm_i_ori(p, pte, pte, hwmode);
1729 BUG_ON(hwmode & ~0xffff);
1730 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1731 uasm_i_lw(p, pte, 0, ptr);
1738 * Check if PTE is present, if not then jump to LABEL. PTR points to
1739 * the page table where this PTE is located, PTE will be re-loaded
1740 * with it's original value.
1743 build_pte_present(u32 **p, struct uasm_reloc **r,
1744 int pte, int ptr, int scratch, enum label_id lid)
1746 int t = scratch >= 0 ? scratch : pte;
1750 if (use_bbit_insns()) {
1751 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1754 if (_PAGE_PRESENT_SHIFT) {
1755 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1758 uasm_i_andi(p, t, cur, 1);
1759 uasm_il_beqz(p, r, t, lid);
1761 /* You lose the SMP race :-(*/
1762 iPTE_LW(p, pte, ptr);
1765 if (_PAGE_PRESENT_SHIFT) {
1766 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1769 uasm_i_andi(p, t, cur,
1770 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
1771 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
1772 uasm_il_bnez(p, r, t, lid);
1774 /* You lose the SMP race :-(*/
1775 iPTE_LW(p, pte, ptr);
1779 /* Make PTE valid, store result in PTR. */
1781 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1782 unsigned int ptr, unsigned int scratch)
1784 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1786 iPTE_SW(p, r, pte, ptr, mode, scratch);
1790 * Check if PTE can be written to, if not branch to LABEL. Regardless
1791 * restore PTE with value from PTR when done.
1794 build_pte_writable(u32 **p, struct uasm_reloc **r,
1795 unsigned int pte, unsigned int ptr, int scratch,
1798 int t = scratch >= 0 ? scratch : pte;
1801 if (_PAGE_PRESENT_SHIFT) {
1802 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1805 uasm_i_andi(p, t, cur,
1806 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1807 uasm_i_xori(p, t, t,
1808 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1809 uasm_il_bnez(p, r, t, lid);
1811 /* You lose the SMP race :-(*/
1812 iPTE_LW(p, pte, ptr);
1817 /* Make PTE writable, update software status bits as well, then store
1821 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1822 unsigned int ptr, unsigned int scratch)
1824 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1827 iPTE_SW(p, r, pte, ptr, mode, scratch);
1831 * Check if PTE can be modified, if not branch to LABEL. Regardless
1832 * restore PTE with value from PTR when done.
1835 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1836 unsigned int pte, unsigned int ptr, int scratch,
1839 if (use_bbit_insns()) {
1840 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1843 int t = scratch >= 0 ? scratch : pte;
1844 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1845 uasm_i_andi(p, t, t, 1);
1846 uasm_il_beqz(p, r, t, lid);
1848 /* You lose the SMP race :-(*/
1849 iPTE_LW(p, pte, ptr);
1853 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1857 * R3000 style TLB load/store/modify handlers.
1861 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1865 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1867 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1868 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1871 uasm_i_rfe(p); /* branch delay */
1875 * This places the pte into ENTRYLO0 and writes it with tlbwi
1876 * or tlbwr as appropriate. This is because the index register
1877 * may have the probe fail bit set as a result of a trap on a
1878 * kseg2 access, i.e. without refill. Then it returns.
1881 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1882 struct uasm_reloc **r, unsigned int pte,
1885 uasm_i_mfc0(p, tmp, C0_INDEX);
1886 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1887 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1888 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1889 uasm_i_tlbwi(p); /* cp0 delay */
1891 uasm_i_rfe(p); /* branch delay */
1892 uasm_l_r3000_write_probe_fail(l, *p);
1893 uasm_i_tlbwr(p); /* cp0 delay */
1895 uasm_i_rfe(p); /* branch delay */
1899 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1902 long pgdc = (long)pgd_current;
1904 uasm_i_mfc0(p, pte, C0_BADVADDR);
1905 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1906 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1907 uasm_i_srl(p, pte, pte, 22); /* load delay */
1908 uasm_i_sll(p, pte, pte, 2);
1909 uasm_i_addu(p, ptr, ptr, pte);
1910 uasm_i_mfc0(p, pte, C0_CONTEXT);
1911 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1912 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1913 uasm_i_addu(p, ptr, ptr, pte);
1914 uasm_i_lw(p, pte, 0, ptr);
1915 uasm_i_tlbp(p); /* load delay */
1918 static void build_r3000_tlb_load_handler(void)
1920 u32 *p = handle_tlbl;
1921 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1922 struct uasm_label *l = labels;
1923 struct uasm_reloc *r = relocs;
1925 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1926 memset(labels, 0, sizeof(labels));
1927 memset(relocs, 0, sizeof(relocs));
1929 build_r3000_tlbchange_handler_head(&p, K0, K1);
1930 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1931 uasm_i_nop(&p); /* load delay */
1932 build_make_valid(&p, &r, K0, K1, -1);
1933 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1935 uasm_l_nopage_tlbl(&l, p);
1936 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1939 if (p >= handle_tlbl_end)
1940 panic("TLB load handler fastpath space exceeded");
1942 uasm_resolve_relocs(relocs, labels);
1943 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1944 (unsigned int)(p - handle_tlbl));
1946 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1949 static void build_r3000_tlb_store_handler(void)
1951 u32 *p = handle_tlbs;
1952 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1953 struct uasm_label *l = labels;
1954 struct uasm_reloc *r = relocs;
1956 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1957 memset(labels, 0, sizeof(labels));
1958 memset(relocs, 0, sizeof(relocs));
1960 build_r3000_tlbchange_handler_head(&p, K0, K1);
1961 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1962 uasm_i_nop(&p); /* load delay */
1963 build_make_write(&p, &r, K0, K1, -1);
1964 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1966 uasm_l_nopage_tlbs(&l, p);
1967 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1970 if (p >= handle_tlbs_end)
1971 panic("TLB store handler fastpath space exceeded");
1973 uasm_resolve_relocs(relocs, labels);
1974 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1975 (unsigned int)(p - handle_tlbs));
1977 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1980 static void build_r3000_tlb_modify_handler(void)
1982 u32 *p = handle_tlbm;
1983 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1984 struct uasm_label *l = labels;
1985 struct uasm_reloc *r = relocs;
1987 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1988 memset(labels, 0, sizeof(labels));
1989 memset(relocs, 0, sizeof(relocs));
1991 build_r3000_tlbchange_handler_head(&p, K0, K1);
1992 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1993 uasm_i_nop(&p); /* load delay */
1994 build_make_write(&p, &r, K0, K1, -1);
1995 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1997 uasm_l_nopage_tlbm(&l, p);
1998 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2001 if (p >= handle_tlbm_end)
2002 panic("TLB modify handler fastpath space exceeded");
2004 uasm_resolve_relocs(relocs, labels);
2005 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2006 (unsigned int)(p - handle_tlbm));
2008 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
2010 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
2013 * R4000 style TLB load/store/modify handlers.
2015 static struct work_registers
2016 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
2017 struct uasm_reloc **r)
2019 struct work_registers wr = build_get_work_registers(p);
2022 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
2024 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
2027 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2029 * For huge tlb entries, pmd doesn't contain an address but
2030 * instead contains the tlb pte. Check the PAGE_HUGE bit and
2031 * see if we need to jump to huge tlb processing.
2033 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
2036 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
2037 UASM_i_LW(p, wr.r2, 0, wr.r2);
2038 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
2039 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
2040 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
2043 uasm_l_smp_pgtable_change(l, *p);
2045 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
2046 if (!m4kc_tlbp_war()) {
2047 build_tlb_probe_entry(p);
2049 /* race condition happens, leaving */
2051 uasm_i_mfc0(p, wr.r3, C0_INDEX);
2052 uasm_il_bltz(p, r, wr.r3, label_leave);
2060 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
2061 struct uasm_reloc **r, unsigned int tmp,
2064 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
2065 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
2066 build_update_entries(p, tmp, ptr);
2067 build_tlb_write_entry(p, l, r, tlb_indexed);
2068 uasm_l_leave(l, *p);
2069 build_restore_work_registers(p);
2070 uasm_i_eret(p); /* return from trap */
2073 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
2077 static void build_r4000_tlb_load_handler(void)
2079 u32 *p = handle_tlbl;
2080 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
2081 struct uasm_label *l = labels;
2082 struct uasm_reloc *r = relocs;
2083 struct work_registers wr;
2085 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
2086 memset(labels, 0, sizeof(labels));
2087 memset(relocs, 0, sizeof(relocs));
2089 if (bcm1250_m3_war()) {
2090 unsigned int segbits = 44;
2092 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
2093 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
2094 uasm_i_xor(&p, K0, K0, K1);
2095 uasm_i_dsrl_safe(&p, K1, K0, 62);
2096 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
2097 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
2098 uasm_i_or(&p, K0, K0, K1);
2099 uasm_il_bnez(&p, &r, K0, label_leave);
2100 /* No need for uasm_i_nop */
2103 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2104 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2105 if (m4kc_tlbp_war())
2106 build_tlb_probe_entry(&p);
2108 if (cpu_has_rixi && !cpu_has_rixiex) {
2110 * If the page is not _PAGE_VALID, RI or XI could not
2111 * have triggered it. Skip the expensive test..
2113 if (use_bbit_insns()) {
2114 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2115 label_tlbl_goaround1);
2117 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2118 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
2124 switch (current_cpu_type()) {
2126 if (cpu_has_mips_r2_exec_hazard) {
2129 case CPU_CAVIUM_OCTEON:
2130 case CPU_CAVIUM_OCTEON_PLUS:
2131 case CPU_CAVIUM_OCTEON2:
2136 /* Examine entrylo 0 or 1 based on ptr. */
2137 if (use_bbit_insns()) {
2138 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2140 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2141 uasm_i_beqz(&p, wr.r3, 8);
2143 /* load it in the delay slot*/
2144 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2145 /* load it if ptr is odd */
2146 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2148 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2149 * XI must have triggered it.
2151 if (use_bbit_insns()) {
2152 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2154 uasm_l_tlbl_goaround1(&l, p);
2156 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2157 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2160 uasm_l_tlbl_goaround1(&l, p);
2162 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
2163 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2165 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2167 * This is the entry point when build_r4000_tlbchange_handler_head
2168 * spots a huge page.
2170 uasm_l_tlb_huge_update(&l, p);
2171 iPTE_LW(&p, wr.r1, wr.r2);
2172 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2173 build_tlb_probe_entry(&p);
2175 if (cpu_has_rixi && !cpu_has_rixiex) {
2177 * If the page is not _PAGE_VALID, RI or XI could not
2178 * have triggered it. Skip the expensive test..
2180 if (use_bbit_insns()) {
2181 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2182 label_tlbl_goaround2);
2184 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2185 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2191 switch (current_cpu_type()) {
2193 if (cpu_has_mips_r2_exec_hazard) {
2196 case CPU_CAVIUM_OCTEON:
2197 case CPU_CAVIUM_OCTEON_PLUS:
2198 case CPU_CAVIUM_OCTEON2:
2203 /* Examine entrylo 0 or 1 based on ptr. */
2204 if (use_bbit_insns()) {
2205 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2207 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2208 uasm_i_beqz(&p, wr.r3, 8);
2210 /* load it in the delay slot*/
2211 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2212 /* load it if ptr is odd */
2213 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2215 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2216 * XI must have triggered it.
2218 if (use_bbit_insns()) {
2219 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2221 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2222 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2224 if (PM_DEFAULT_MASK == 0)
2227 * We clobbered C0_PAGEMASK, restore it. On the other branch
2228 * it is restored in build_huge_tlb_write_entry.
2230 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2232 uasm_l_tlbl_goaround2(&l, p);
2234 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2235 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2238 uasm_l_nopage_tlbl(&l, p);
2239 build_restore_work_registers(&p);
2240 #ifdef CONFIG_CPU_MICROMIPS
2241 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2242 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2243 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2247 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2250 if (p >= handle_tlbl_end)
2251 panic("TLB load handler fastpath space exceeded");
2253 uasm_resolve_relocs(relocs, labels);
2254 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2255 (unsigned int)(p - handle_tlbl));
2257 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2260 static void build_r4000_tlb_store_handler(void)
2262 u32 *p = handle_tlbs;
2263 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2264 struct uasm_label *l = labels;
2265 struct uasm_reloc *r = relocs;
2266 struct work_registers wr;
2268 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2269 memset(labels, 0, sizeof(labels));
2270 memset(relocs, 0, sizeof(relocs));
2272 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2273 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2274 if (m4kc_tlbp_war())
2275 build_tlb_probe_entry(&p);
2276 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2277 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2279 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2281 * This is the entry point when
2282 * build_r4000_tlbchange_handler_head spots a huge page.
2284 uasm_l_tlb_huge_update(&l, p);
2285 iPTE_LW(&p, wr.r1, wr.r2);
2286 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2287 build_tlb_probe_entry(&p);
2288 uasm_i_ori(&p, wr.r1, wr.r1,
2289 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2290 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2293 uasm_l_nopage_tlbs(&l, p);
2294 build_restore_work_registers(&p);
2295 #ifdef CONFIG_CPU_MICROMIPS
2296 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2297 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2298 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2302 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2305 if (p >= handle_tlbs_end)
2306 panic("TLB store handler fastpath space exceeded");
2308 uasm_resolve_relocs(relocs, labels);
2309 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2310 (unsigned int)(p - handle_tlbs));
2312 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2315 static void build_r4000_tlb_modify_handler(void)
2317 u32 *p = handle_tlbm;
2318 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2319 struct uasm_label *l = labels;
2320 struct uasm_reloc *r = relocs;
2321 struct work_registers wr;
2323 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2324 memset(labels, 0, sizeof(labels));
2325 memset(relocs, 0, sizeof(relocs));
2327 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2328 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2329 if (m4kc_tlbp_war())
2330 build_tlb_probe_entry(&p);
2331 /* Present and writable bits set, set accessed and dirty bits. */
2332 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2333 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2335 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2337 * This is the entry point when
2338 * build_r4000_tlbchange_handler_head spots a huge page.
2340 uasm_l_tlb_huge_update(&l, p);
2341 iPTE_LW(&p, wr.r1, wr.r2);
2342 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2343 build_tlb_probe_entry(&p);
2344 uasm_i_ori(&p, wr.r1, wr.r1,
2345 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2346 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
2349 uasm_l_nopage_tlbm(&l, p);
2350 build_restore_work_registers(&p);
2351 #ifdef CONFIG_CPU_MICROMIPS
2352 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2353 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2354 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2358 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2361 if (p >= handle_tlbm_end)
2362 panic("TLB modify handler fastpath space exceeded");
2364 uasm_resolve_relocs(relocs, labels);
2365 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2366 (unsigned int)(p - handle_tlbm));
2368 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2371 static void flush_tlb_handlers(void)
2373 local_flush_icache_range((unsigned long)handle_tlbl,
2374 (unsigned long)handle_tlbl_end);
2375 local_flush_icache_range((unsigned long)handle_tlbs,
2376 (unsigned long)handle_tlbs_end);
2377 local_flush_icache_range((unsigned long)handle_tlbm,
2378 (unsigned long)handle_tlbm_end);
2379 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2380 (unsigned long)tlbmiss_handler_setup_pgd_end);
2383 static void print_htw_config(void)
2385 unsigned long config;
2387 const int field = 2 * sizeof(unsigned long);
2389 config = read_c0_pwfield();
2390 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2392 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2393 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2394 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2395 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2396 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2398 config = read_c0_pwsize();
2399 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2401 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
2402 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2403 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2404 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2405 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2406 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2408 pwctl = read_c0_pwctl();
2409 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2411 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2412 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2413 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2414 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
2415 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2416 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2417 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2420 static void config_htw_params(void)
2422 unsigned long pwfield, pwsize, ptei;
2423 unsigned int config;
2426 * We are using 2-level page tables, so we only need to
2427 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2428 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2429 * write values less than 0xc in these fields because the entire
2430 * write will be dropped. As a result of which, we must preserve
2431 * the original reset values and overwrite only what we really want.
2434 pwfield = read_c0_pwfield();
2435 /* re-initialize the GDI field */
2436 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2437 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2438 /* re-initialize the PTI field including the even/odd bit */
2439 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2440 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2441 if (CONFIG_PGTABLE_LEVELS >= 3) {
2442 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2443 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2445 /* Set the PTEI right shift */
2446 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2448 write_c0_pwfield(pwfield);
2449 /* Check whether the PTEI value is supported */
2450 back_to_back_c0_hazard();
2451 pwfield = read_c0_pwfield();
2452 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2454 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2457 * Drop option to avoid HTW being enabled via another path
2460 current_cpu_data.options &= ~MIPS_CPU_HTW;
2464 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2465 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2466 if (CONFIG_PGTABLE_LEVELS >= 3)
2467 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2469 /* Set pointer size to size of directory pointers */
2470 if (IS_ENABLED(CONFIG_64BIT))
2471 pwsize |= MIPS_PWSIZE_PS_MASK;
2472 /* PTEs may be multiple pointers long (e.g. with XPA) */
2473 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2474 & MIPS_PWSIZE_PTEW_MASK;
2476 write_c0_pwsize(pwsize);
2478 /* Make sure everything is set before we enable the HTW */
2479 back_to_back_c0_hazard();
2482 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2485 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2486 if (IS_ENABLED(CONFIG_64BIT))
2487 config |= MIPS_PWCTL_XU_MASK;
2488 write_c0_pwctl(config);
2489 pr_info("Hardware Page Table Walker enabled\n");
2494 static void config_xpa_params(void)
2497 unsigned int pagegrain;
2499 if (mips_xpa_disabled) {
2500 pr_info("Extended Physical Addressing (XPA) disabled\n");
2504 pagegrain = read_c0_pagegrain();
2505 write_c0_pagegrain(pagegrain | PG_ELPA);
2506 back_to_back_c0_hazard();
2507 pagegrain = read_c0_pagegrain();
2509 if (pagegrain & PG_ELPA)
2510 pr_info("Extended Physical Addressing (XPA) enabled\n");
2512 panic("Extended Physical Addressing (XPA) disabled");
2516 static void check_pabits(void)
2518 unsigned long entry;
2519 unsigned pabits, fillbits;
2521 if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2523 * We'll only be making use of the fact that we can rotate bits
2524 * into the fill if the CPU supports RIXI, so don't bother
2525 * probing this for CPUs which don't.
2530 write_c0_entrylo0(~0ul);
2531 back_to_back_c0_hazard();
2532 entry = read_c0_entrylo0();
2534 /* clear all non-PFN bits */
2535 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2536 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2538 /* find a lower bound on PABITS, and upper bound on fill bits */
2539 pabits = fls_long(entry) + 6;
2540 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2542 /* minus the RI & XI bits */
2543 fillbits -= min_t(unsigned, fillbits, 2);
2545 if (fillbits >= ilog2(_PAGE_NO_EXEC))
2546 fill_includes_sw_bits = true;
2548 pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2551 void build_tlb_refill_handler(void)
2554 * The refill handler is generated per-CPU, multi-node systems
2555 * may have local storage for it. The other handlers are only
2558 static int run_once = 0;
2560 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
2561 panic("Kernels supporting XPA currently require CPUs with RIXI");
2563 output_pgtable_bits_defines();
2567 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2570 switch (current_cpu_type()) {
2578 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2579 if (cpu_has_local_ebase)
2580 build_r3000_tlb_refill_handler();
2582 if (!cpu_has_local_ebase)
2583 build_r3000_tlb_refill_handler();
2585 build_r3000_tlb_load_handler();
2586 build_r3000_tlb_store_handler();
2587 build_r3000_tlb_modify_handler();
2588 flush_tlb_handlers();
2592 panic("No R3000 TLB refill handler");
2598 panic("No R6000 TLB refill handler yet");
2602 panic("No R8000 TLB refill handler yet");
2610 scratch_reg = allocate_kscratch();
2612 build_r4000_tlb_load_handler();
2613 build_r4000_tlb_store_handler();
2614 build_r4000_tlb_modify_handler();
2616 build_loongson3_tlb_refill_handler();
2617 else if (!cpu_has_local_ebase)
2618 build_r4000_tlb_refill_handler();
2619 flush_tlb_handlers();
2622 if (cpu_has_local_ebase)
2623 build_r4000_tlb_refill_handler();
2625 config_xpa_params();
2627 config_htw_params();