2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/cache.h>
31 #include <asm/cacheflush.h>
32 #include <asm/cpu-type.h>
33 #include <asm/pgtable.h>
36 #include <asm/setup.h>
38 static int mips_xpa_disabled;
40 static int __init xpa_disable(char *s)
42 mips_xpa_disabled = 1;
47 __setup("noxpa", xpa_disable);
50 * TLB load/store/modify handlers.
52 * Only the fastpath gets synthesized at runtime, the slowpath for
53 * do_page_fault remains normal asm.
55 extern void tlb_do_page_fault_0(void);
56 extern void tlb_do_page_fault_1(void);
58 struct work_registers {
67 } ____cacheline_aligned_in_smp;
69 static struct tlb_reg_save handler_reg_save[NR_CPUS];
71 static inline int r45k_bvahwbug(void)
73 /* XXX: We should probe for the presence of this bug, but we don't. */
77 static inline int r4k_250MHZhwbug(void)
79 /* XXX: We should probe for the presence of this bug, but we don't. */
83 static inline int __maybe_unused bcm1250_m3_war(void)
85 return BCM1250_M3_WAR;
88 static inline int __maybe_unused r10000_llsc_war(void)
90 return R10000_LLSC_WAR;
93 static int use_bbit_insns(void)
95 switch (current_cpu_type()) {
96 case CPU_CAVIUM_OCTEON:
97 case CPU_CAVIUM_OCTEON_PLUS:
98 case CPU_CAVIUM_OCTEON2:
99 case CPU_CAVIUM_OCTEON3:
106 static int use_lwx_insns(void)
108 switch (current_cpu_type()) {
109 case CPU_CAVIUM_OCTEON2:
110 case CPU_CAVIUM_OCTEON3:
116 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
117 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
118 static bool scratchpad_available(void)
122 static int scratchpad_offset(int i)
125 * CVMSEG starts at address -32768 and extends for
126 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
128 i += 1; /* Kernel use starts at the top and works down. */
129 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
132 static bool scratchpad_available(void)
136 static int scratchpad_offset(int i)
139 /* Really unreachable, but evidently some GCC want this. */
144 * Found by experiment: At least some revisions of the 4kc throw under
145 * some circumstances a machine check exception, triggered by invalid
146 * values in the index register. Delaying the tlbp instruction until
147 * after the next branch, plus adding an additional nop in front of
148 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
149 * why; it's not an issue caused by the core RTL.
152 static int m4kc_tlbp_war(void)
154 return (current_cpu_data.processor_id & 0xffff00) ==
155 (PRID_COMP_MIPS | PRID_IMP_4KC);
158 /* Handle labels (which must be positive integers). */
160 label_second_part = 1,
165 label_split = label_tlbw_hazard_0 + 8,
166 label_tlbl_goaround1,
167 label_tlbl_goaround2,
171 label_smp_pgtable_change,
172 label_r3000_write_probe_fail,
173 label_large_segbits_fault,
174 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
175 label_tlb_huge_update,
179 UASM_L_LA(_second_part)
182 UASM_L_LA(_vmalloc_done)
183 /* _tlbw_hazard_x is handled differently. */
185 UASM_L_LA(_tlbl_goaround1)
186 UASM_L_LA(_tlbl_goaround2)
187 UASM_L_LA(_nopage_tlbl)
188 UASM_L_LA(_nopage_tlbs)
189 UASM_L_LA(_nopage_tlbm)
190 UASM_L_LA(_smp_pgtable_change)
191 UASM_L_LA(_r3000_write_probe_fail)
192 UASM_L_LA(_large_segbits_fault)
193 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
194 UASM_L_LA(_tlb_huge_update)
197 static int hazard_instance;
199 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
203 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
210 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
214 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
222 * pgtable bits are assigned dynamically depending on processor feature
223 * and statically based on kernel configuration. This spits out the actual
224 * values the kernel is using. Required to make sense from disassembled
225 * TLB exception handlers.
227 static void output_pgtable_bits_defines(void)
229 #define pr_define(fmt, ...) \
230 pr_debug("#define " fmt, ##__VA_ARGS__)
232 pr_debug("#include <asm/asm.h>\n");
233 pr_debug("#include <asm/regdef.h>\n");
236 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
237 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
238 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
239 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
240 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
241 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
242 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
243 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
245 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
247 #ifdef _PAGE_NO_EXEC_SHIFT
248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
249 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
253 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
254 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
255 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
256 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
260 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
264 pr_debug("LEAF(%s)\n", symbol);
266 pr_debug("\t.set push\n");
267 pr_debug("\t.set noreorder\n");
269 for (i = 0; i < count; i++)
270 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
272 pr_debug("\t.set\tpop\n");
274 pr_debug("\tEND(%s)\n", symbol);
277 /* The only general purpose registers allowed in TLB handlers. */
281 /* Some CP0 registers */
282 #define C0_INDEX 0, 0
283 #define C0_ENTRYLO0 2, 0
284 #define C0_TCBIND 2, 2
285 #define C0_ENTRYLO1 3, 0
286 #define C0_CONTEXT 4, 0
287 #define C0_PAGEMASK 5, 0
288 #define C0_BADVADDR 8, 0
289 #define C0_ENTRYHI 10, 0
291 #define C0_XCONTEXT 20, 0
294 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
296 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
299 /* The worst case length of the handler is around 18 instructions for
300 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
301 * Maximum space available is 32 instructions for R3000 and 64
302 * instructions for R4000.
304 * We deliberately chose a buffer size of 128, so we won't scribble
305 * over anything important on overflow before we panic.
307 static u32 tlb_handler[128];
309 /* simply assume worst case size for labels and relocs */
310 static struct uasm_label labels[128];
311 static struct uasm_reloc relocs[128];
313 static int check_for_high_segbits;
314 static bool fill_includes_sw_bits;
316 static unsigned int kscratch_used_mask;
318 static inline int __maybe_unused c0_kscratch(void)
320 switch (current_cpu_type()) {
329 static int allocate_kscratch(void)
332 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
339 r--; /* make it zero based */
341 kscratch_used_mask |= (1 << r);
346 static int scratch_reg;
348 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
350 static struct work_registers build_get_work_registers(u32 **p)
352 struct work_registers r;
354 if (scratch_reg >= 0) {
355 /* Save in CPU local C0_KScratch? */
356 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
363 if (num_possible_cpus() > 1) {
364 /* Get smp_processor_id */
365 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
366 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
368 /* handler_reg_save index in K0 */
369 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
371 UASM_i_LA(p, K1, (long)&handler_reg_save);
372 UASM_i_ADDU(p, K0, K0, K1);
374 UASM_i_LA(p, K0, (long)&handler_reg_save);
376 /* K0 now points to save area, save $1 and $2 */
377 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
378 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
386 static void build_restore_work_registers(u32 **p)
388 if (scratch_reg >= 0) {
389 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
392 /* K0 already points to save area, restore $1 and $2 */
393 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
394 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
397 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
400 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
401 * we cannot do r3000 under these circumstances.
403 * Declare pgd_current here instead of including mmu_context.h to avoid type
404 * conflicts for tlbmiss_handler_setup_pgd
406 extern unsigned long pgd_current[];
409 * The R3000 TLB handler is simple.
411 static void build_r3000_tlb_refill_handler(void)
413 long pgdc = (long)pgd_current;
416 memset(tlb_handler, 0, sizeof(tlb_handler));
419 uasm_i_mfc0(&p, K0, C0_BADVADDR);
420 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
421 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
422 uasm_i_srl(&p, K0, K0, 22); /* load delay */
423 uasm_i_sll(&p, K0, K0, 2);
424 uasm_i_addu(&p, K1, K1, K0);
425 uasm_i_mfc0(&p, K0, C0_CONTEXT);
426 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
427 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
428 uasm_i_addu(&p, K1, K1, K0);
429 uasm_i_lw(&p, K0, 0, K1);
430 uasm_i_nop(&p); /* load delay */
431 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
432 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
433 uasm_i_tlbwr(&p); /* cp0 delay */
435 uasm_i_rfe(&p); /* branch delay */
437 if (p > tlb_handler + 32)
438 panic("TLB refill handler space exceeded");
440 pr_debug("Wrote TLB refill handler (%u instructions).\n",
441 (unsigned int)(p - tlb_handler));
443 memcpy((void *)ebase, tlb_handler, 0x80);
444 local_flush_icache_range(ebase, ebase + 0x80);
446 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
448 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
451 * The R4000 TLB handler is much more complicated. We have two
452 * consecutive handler areas with 32 instructions space each.
453 * Since they aren't used at the same time, we can overflow in the
454 * other one.To keep things simple, we first assume linear space,
455 * then we relocate it to the final handler layout as needed.
457 static u32 final_handler[64];
462 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
463 * 2. A timing hazard exists for the TLBP instruction.
465 * stalling_instruction
468 * The JTLB is being read for the TLBP throughout the stall generated by the
469 * previous instruction. This is not really correct as the stalling instruction
470 * can modify the address used to access the JTLB. The failure symptom is that
471 * the TLBP instruction will use an address created for the stalling instruction
472 * and not the address held in C0_ENHI and thus report the wrong results.
474 * The software work-around is to not allow the instruction preceding the TLBP
475 * to stall - make it an NOP or some other instruction guaranteed not to stall.
477 * Errata 2 will not be fixed. This errata is also on the R5000.
479 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
481 static void __maybe_unused build_tlb_probe_entry(u32 **p)
483 switch (current_cpu_type()) {
484 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
500 * Write random or indexed TLB entry, and care about the hazards from
501 * the preceding mtc0 and for the following eret.
503 enum tlb_write_entry { tlb_random, tlb_indexed };
505 static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
506 struct uasm_reloc **r,
507 enum tlb_write_entry wmode)
509 void(*tlbw)(u32 **) = NULL;
512 case tlb_random: tlbw = uasm_i_tlbwr; break;
513 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
516 if (cpu_has_mips_r2_r6) {
517 if (cpu_has_mips_r2_exec_hazard)
523 switch (current_cpu_type()) {
531 * This branch uses up a mtc0 hazard nop slot and saves
532 * two nops after the tlbw instruction.
534 uasm_bgezl_hazard(p, r, hazard_instance);
536 uasm_bgezl_label(l, p, hazard_instance);
550 uasm_i_nop(p); /* QED specifies 2 nops hazard */
551 uasm_i_nop(p); /* QED specifies 2 nops hazard */
625 panic("No TLB refill handler yet (CPU type: %d)",
631 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
634 if (cpu_has_rixi && _PAGE_NO_EXEC) {
635 if (fill_includes_sw_bits) {
636 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
638 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
639 UASM_i_ROTR(p, reg, reg,
640 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
643 #ifdef CONFIG_PHYS_ADDR_T_64BIT
644 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
646 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
651 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
653 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
654 unsigned int tmp, enum label_id lid,
657 if (restore_scratch) {
658 /* Reset default page size */
659 if (PM_DEFAULT_MASK >> 16) {
660 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
661 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
662 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
663 uasm_il_b(p, r, lid);
664 } else if (PM_DEFAULT_MASK) {
665 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
666 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
667 uasm_il_b(p, r, lid);
669 uasm_i_mtc0(p, 0, C0_PAGEMASK);
670 uasm_il_b(p, r, lid);
672 if (scratch_reg >= 0)
673 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
675 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
677 /* Reset default page size */
678 if (PM_DEFAULT_MASK >> 16) {
679 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
680 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
681 uasm_il_b(p, r, lid);
682 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
683 } else if (PM_DEFAULT_MASK) {
684 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
685 uasm_il_b(p, r, lid);
686 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
688 uasm_il_b(p, r, lid);
689 uasm_i_mtc0(p, 0, C0_PAGEMASK);
694 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
695 struct uasm_reloc **r,
697 enum tlb_write_entry wmode,
700 /* Set huge page tlb entry size */
701 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
702 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
703 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
705 build_tlb_write_entry(p, l, r, wmode);
707 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
711 * Check if Huge PTE is present, if so then jump to LABEL.
714 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
715 unsigned int pmd, int lid)
717 UASM_i_LW(p, tmp, 0, pmd);
718 if (use_bbit_insns()) {
719 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
721 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
722 uasm_il_bnez(p, r, tmp, lid);
726 static void build_huge_update_entries(u32 **p, unsigned int pte,
732 * A huge PTE describes an area the size of the
733 * configured huge page size. This is twice the
734 * of the large TLB entry size we intend to use.
735 * A TLB entry half the size of the configured
736 * huge page size is configured into entrylo0
737 * and entrylo1 to cover the contiguous huge PTE
740 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
742 /* We can clobber tmp. It isn't used after this.*/
744 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
746 build_convert_pte_to_entrylo(p, pte);
747 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
748 /* convert to entrylo1 */
750 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
752 UASM_i_ADDU(p, pte, pte, tmp);
754 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
757 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
758 struct uasm_label **l,
764 UASM_i_SC(p, pte, 0, ptr);
765 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
766 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
768 UASM_i_SW(p, pte, 0, ptr);
770 if (cpu_has_ftlb && flush) {
771 BUG_ON(!cpu_has_tlbinv);
773 UASM_i_MFC0(p, ptr, C0_ENTRYHI);
774 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
775 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
776 build_tlb_write_entry(p, l, r, tlb_indexed);
778 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
779 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
780 build_huge_update_entries(p, pte, ptr);
781 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
786 build_huge_update_entries(p, pte, ptr);
787 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
789 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
793 * TMP and PTR are scratch.
794 * TMP will be clobbered, PTR will hold the pmd entry.
797 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
798 unsigned int tmp, unsigned int ptr)
800 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
801 long pgdc = (long)pgd_current;
804 * The vmalloc handling is not in the hotpath.
806 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
808 if (check_for_high_segbits) {
810 * The kernel currently implicitely assumes that the
811 * MIPS SEGBITS parameter for the processor is
812 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
813 * allocate virtual addresses outside the maximum
814 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
815 * that doesn't prevent user code from accessing the
816 * higher xuseg addresses. Here, we make sure that
817 * everything but the lower xuseg addresses goes down
818 * the module_alloc/vmalloc path.
820 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
821 uasm_il_bnez(p, r, ptr, label_vmalloc);
823 uasm_il_bltz(p, r, tmp, label_vmalloc);
825 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
828 /* pgd is in pgd_reg */
829 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
831 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
833 * &pgd << 11 stored in CONTEXT [23..63].
835 UASM_i_MFC0(p, ptr, C0_CONTEXT);
837 /* Clear lower 23 bits of context. */
838 uasm_i_dins(p, ptr, 0, 0, 23);
840 /* 1 0 1 0 1 << 6 xkphys cached */
841 uasm_i_ori(p, ptr, ptr, 0x540);
842 uasm_i_drotr(p, ptr, ptr, 11);
843 #elif defined(CONFIG_SMP)
844 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
845 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
846 UASM_i_LA_mostly(p, tmp, pgdc);
847 uasm_i_daddu(p, ptr, ptr, tmp);
848 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
849 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
851 UASM_i_LA_mostly(p, ptr, pgdc);
852 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
856 uasm_l_vmalloc_done(l, *p);
858 /* get pgd offset in bytes */
859 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
861 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
862 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
863 #ifndef __PAGETABLE_PMD_FOLDED
864 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
865 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
866 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
867 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
868 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
873 * BVADDR is the faulting address, PTR is scratch.
874 * PTR will hold the pgd for vmalloc.
877 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
878 unsigned int bvaddr, unsigned int ptr,
879 enum vmalloc64_mode mode)
881 long swpd = (long)swapper_pg_dir;
882 int single_insn_swpd;
883 int did_vmalloc_branch = 0;
885 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
887 uasm_l_vmalloc(l, *p);
889 if (mode != not_refill && check_for_high_segbits) {
890 if (single_insn_swpd) {
891 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
892 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
893 did_vmalloc_branch = 1;
896 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
899 if (!did_vmalloc_branch) {
900 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
901 uasm_il_b(p, r, label_vmalloc_done);
902 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
904 UASM_i_LA_mostly(p, ptr, swpd);
905 uasm_il_b(p, r, label_vmalloc_done);
906 if (uasm_in_compat_space_p(swpd))
907 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
909 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
912 if (mode != not_refill && check_for_high_segbits) {
913 uasm_l_large_segbits_fault(l, *p);
915 * We get here if we are an xsseg address, or if we are
916 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
918 * Ignoring xsseg (assume disabled so would generate
919 * (address errors?), the only remaining possibility
920 * is the upper xuseg addresses. On processors with
921 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
922 * addresses would have taken an address error. We try
923 * to mimic that here by taking a load/istream page
926 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
929 if (mode == refill_scratch) {
930 if (scratch_reg >= 0)
931 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
933 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
940 #else /* !CONFIG_64BIT */
943 * TMP and PTR are scratch.
944 * TMP will be clobbered, PTR will hold the pgd entry.
946 static void __maybe_unused
947 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
950 /* pgd is in pgd_reg */
951 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
952 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
954 long pgdc = (long)pgd_current;
956 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
958 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
959 UASM_i_LA_mostly(p, tmp, pgdc);
960 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
961 uasm_i_addu(p, ptr, tmp, ptr);
963 UASM_i_LA_mostly(p, ptr, pgdc);
965 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
966 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
968 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
969 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
970 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
973 #endif /* !CONFIG_64BIT */
975 static void build_adjust_context(u32 **p, unsigned int ctx)
977 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
978 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
980 switch (current_cpu_type()) {
997 UASM_i_SRL(p, ctx, ctx, shift);
998 uasm_i_andi(p, ctx, ctx, mask);
1001 static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1004 * Bug workaround for the Nevada. It seems as if under certain
1005 * circumstances the move from cp0_context might produce a
1006 * bogus result when the mfc0 instruction and its consumer are
1007 * in a different cacheline or a load instruction, probably any
1008 * memory reference, is between them.
1010 switch (current_cpu_type()) {
1012 UASM_i_LW(p, ptr, 0, ptr);
1013 GET_CONTEXT(p, tmp); /* get context reg */
1017 GET_CONTEXT(p, tmp); /* get context reg */
1018 UASM_i_LW(p, ptr, 0, ptr);
1022 build_adjust_context(p, tmp);
1023 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1026 static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1029 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1030 * Kernel is a special case. Only a few CPUs use it.
1032 if (config_enabled(CONFIG_PHYS_ADDR_T_64BIT) && !cpu_has_64bits) {
1033 int pte_off_even = sizeof(pte_t) / 2;
1034 int pte_off_odd = pte_off_even + sizeof(pte_t);
1036 const int scratch = 1; /* Our extra working register */
1038 uasm_i_addu(p, scratch, 0, ptep);
1040 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1041 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* odd pte */
1042 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1043 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1044 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1045 UASM_i_MTC0(p, ptep, C0_ENTRYLO1);
1047 uasm_i_lw(p, tmp, 0, scratch);
1048 uasm_i_lw(p, ptep, sizeof(pte_t), scratch);
1049 uasm_i_lui(p, scratch, 0xff);
1050 uasm_i_ori(p, scratch, scratch, 0xffff);
1051 uasm_i_and(p, tmp, scratch, tmp);
1052 uasm_i_and(p, ptep, scratch, ptep);
1053 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1054 uasm_i_mthc0(p, ptep, C0_ENTRYLO1);
1059 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1060 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1061 if (r45k_bvahwbug())
1062 build_tlb_probe_entry(p);
1063 build_convert_pte_to_entrylo(p, tmp);
1064 if (r4k_250MHZhwbug())
1065 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1066 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1067 build_convert_pte_to_entrylo(p, ptep);
1068 if (r45k_bvahwbug())
1069 uasm_i_mfc0(p, tmp, C0_INDEX);
1070 if (r4k_250MHZhwbug())
1071 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1072 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1075 struct mips_huge_tlb_info {
1077 int restore_scratch;
1078 bool need_reload_pte;
1081 static struct mips_huge_tlb_info
1082 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1083 struct uasm_reloc **r, unsigned int tmp,
1084 unsigned int ptr, int c0_scratch_reg)
1086 struct mips_huge_tlb_info rv;
1087 unsigned int even, odd;
1088 int vmalloc_branch_delay_filled = 0;
1089 const int scratch = 1; /* Our extra working register */
1091 rv.huge_pte = scratch;
1092 rv.restore_scratch = 0;
1093 rv.need_reload_pte = false;
1095 if (check_for_high_segbits) {
1096 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1099 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1101 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1103 if (c0_scratch_reg >= 0)
1104 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1106 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1108 uasm_i_dsrl_safe(p, scratch, tmp,
1109 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1110 uasm_il_bnez(p, r, scratch, label_vmalloc);
1112 if (pgd_reg == -1) {
1113 vmalloc_branch_delay_filled = 1;
1114 /* Clear lower 23 bits of context. */
1115 uasm_i_dins(p, ptr, 0, 0, 23);
1119 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1121 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1123 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1125 if (c0_scratch_reg >= 0)
1126 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1128 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1131 /* Clear lower 23 bits of context. */
1132 uasm_i_dins(p, ptr, 0, 0, 23);
1134 uasm_il_bltz(p, r, tmp, label_vmalloc);
1137 if (pgd_reg == -1) {
1138 vmalloc_branch_delay_filled = 1;
1139 /* 1 0 1 0 1 << 6 xkphys cached */
1140 uasm_i_ori(p, ptr, ptr, 0x540);
1141 uasm_i_drotr(p, ptr, ptr, 11);
1144 #ifdef __PAGETABLE_PMD_FOLDED
1145 #define LOC_PTEP scratch
1147 #define LOC_PTEP ptr
1150 if (!vmalloc_branch_delay_filled)
1151 /* get pgd offset in bytes */
1152 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1154 uasm_l_vmalloc_done(l, *p);
1158 * fall-through case = badvaddr *pgd_current
1159 * vmalloc case = badvaddr swapper_pg_dir
1162 if (vmalloc_branch_delay_filled)
1163 /* get pgd offset in bytes */
1164 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1166 #ifdef __PAGETABLE_PMD_FOLDED
1167 GET_CONTEXT(p, tmp); /* get context reg */
1169 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1171 if (use_lwx_insns()) {
1172 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1174 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1175 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1178 #ifndef __PAGETABLE_PMD_FOLDED
1179 /* get pmd offset in bytes */
1180 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1181 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1182 GET_CONTEXT(p, tmp); /* get context reg */
1184 if (use_lwx_insns()) {
1185 UASM_i_LWX(p, scratch, scratch, ptr);
1187 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1188 UASM_i_LW(p, scratch, 0, ptr);
1191 /* Adjust the context during the load latency. */
1192 build_adjust_context(p, tmp);
1194 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1195 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1197 * The in the LWX case we don't want to do the load in the
1198 * delay slot. It cannot issue in the same cycle and may be
1199 * speculative and unneeded.
1201 if (use_lwx_insns())
1203 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1206 /* build_update_entries */
1207 if (use_lwx_insns()) {
1210 UASM_i_LWX(p, even, scratch, tmp);
1211 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1212 UASM_i_LWX(p, odd, scratch, tmp);
1214 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1217 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1218 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1221 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1222 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1223 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1225 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1226 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1227 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1229 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1231 if (c0_scratch_reg >= 0) {
1232 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1233 build_tlb_write_entry(p, l, r, tlb_random);
1234 uasm_l_leave(l, *p);
1235 rv.restore_scratch = 1;
1236 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1237 build_tlb_write_entry(p, l, r, tlb_random);
1238 uasm_l_leave(l, *p);
1239 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1241 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1242 build_tlb_write_entry(p, l, r, tlb_random);
1243 uasm_l_leave(l, *p);
1244 rv.restore_scratch = 1;
1247 uasm_i_eret(p); /* return from trap */
1253 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1254 * because EXL == 0. If we wrap, we can also use the 32 instruction
1255 * slots before the XTLB refill exception handler which belong to the
1256 * unused TLB refill exception.
1258 #define MIPS64_REFILL_INSNS 32
1260 static void build_r4000_tlb_refill_handler(void)
1262 u32 *p = tlb_handler;
1263 struct uasm_label *l = labels;
1264 struct uasm_reloc *r = relocs;
1266 unsigned int final_len;
1267 struct mips_huge_tlb_info htlb_info __maybe_unused;
1268 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1270 memset(tlb_handler, 0, sizeof(tlb_handler));
1271 memset(labels, 0, sizeof(labels));
1272 memset(relocs, 0, sizeof(relocs));
1273 memset(final_handler, 0, sizeof(final_handler));
1275 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1276 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1278 vmalloc_mode = refill_scratch;
1280 htlb_info.huge_pte = K0;
1281 htlb_info.restore_scratch = 0;
1282 htlb_info.need_reload_pte = true;
1283 vmalloc_mode = refill_noscratch;
1285 * create the plain linear handler
1287 if (bcm1250_m3_war()) {
1288 unsigned int segbits = 44;
1290 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1291 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1292 uasm_i_xor(&p, K0, K0, K1);
1293 uasm_i_dsrl_safe(&p, K1, K0, 62);
1294 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1295 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1296 uasm_i_or(&p, K0, K0, K1);
1297 uasm_il_bnez(&p, &r, K0, label_leave);
1298 /* No need for uasm_i_nop */
1302 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1304 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1307 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1308 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1311 build_get_ptep(&p, K0, K1);
1312 build_update_entries(&p, K0, K1);
1313 build_tlb_write_entry(&p, &l, &r, tlb_random);
1314 uasm_l_leave(&l, p);
1315 uasm_i_eret(&p); /* return from trap */
1317 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1318 uasm_l_tlb_huge_update(&l, p);
1319 if (htlb_info.need_reload_pte)
1320 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1321 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1322 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1323 htlb_info.restore_scratch);
1327 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1331 * Overflow check: For the 64bit handler, we need at least one
1332 * free instruction slot for the wrap-around branch. In worst
1333 * case, if the intended insertion point is a delay slot, we
1334 * need three, with the second nop'ed and the third being
1337 switch (boot_cpu_type()) {
1339 if (sizeof(long) == 4) {
1341 /* Loongson2 ebase is different than r4k, we have more space */
1342 if ((p - tlb_handler) > 64)
1343 panic("TLB refill handler space exceeded");
1345 * Now fold the handler in the TLB refill handler space.
1348 /* Simplest case, just copy the handler. */
1349 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1350 final_len = p - tlb_handler;
1353 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1354 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1355 && uasm_insn_has_bdelay(relocs,
1356 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1357 panic("TLB refill handler space exceeded");
1359 * Now fold the handler in the TLB refill handler space.
1361 f = final_handler + MIPS64_REFILL_INSNS;
1362 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1363 /* Just copy the handler. */
1364 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1365 final_len = p - tlb_handler;
1367 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1368 const enum label_id ls = label_tlb_huge_update;
1370 const enum label_id ls = label_vmalloc;
1376 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1378 BUG_ON(i == ARRAY_SIZE(labels));
1379 split = labels[i].addr;
1382 * See if we have overflown one way or the other.
1384 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1385 split < p - MIPS64_REFILL_INSNS)
1390 * Split two instructions before the end. One
1391 * for the branch and one for the instruction
1392 * in the delay slot.
1394 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1397 * If the branch would fall in a delay slot,
1398 * we must back up an additional instruction
1399 * so that it is no longer in a delay slot.
1401 if (uasm_insn_has_bdelay(relocs, split - 1))
1404 /* Copy first part of the handler. */
1405 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1406 f += split - tlb_handler;
1409 /* Insert branch. */
1410 uasm_l_split(&l, final_handler);
1411 uasm_il_b(&f, &r, label_split);
1412 if (uasm_insn_has_bdelay(relocs, split))
1415 uasm_copy_handler(relocs, labels,
1416 split, split + 1, f);
1417 uasm_move_labels(labels, f, f + 1, -1);
1423 /* Copy the rest of the handler. */
1424 uasm_copy_handler(relocs, labels, split, p, final_handler);
1425 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1432 uasm_resolve_relocs(relocs, labels);
1433 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1436 memcpy((void *)ebase, final_handler, 0x100);
1437 local_flush_icache_range(ebase, ebase + 0x100);
1439 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1442 extern u32 handle_tlbl[], handle_tlbl_end[];
1443 extern u32 handle_tlbs[], handle_tlbs_end[];
1444 extern u32 handle_tlbm[], handle_tlbm_end[];
1445 extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
1446 extern u32 tlbmiss_handler_setup_pgd_end[];
1448 static void build_setup_pgd(void)
1451 const int __maybe_unused a1 = 5;
1452 const int __maybe_unused a2 = 6;
1453 u32 *p = tlbmiss_handler_setup_pgd_start;
1454 const int tlbmiss_handler_setup_pgd_size =
1455 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1456 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1457 long pgdc = (long)pgd_current;
1460 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1461 sizeof(tlbmiss_handler_setup_pgd[0]));
1462 memset(labels, 0, sizeof(labels));
1463 memset(relocs, 0, sizeof(relocs));
1464 pgd_reg = allocate_kscratch();
1465 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1466 if (pgd_reg == -1) {
1467 struct uasm_label *l = labels;
1468 struct uasm_reloc *r = relocs;
1470 /* PGD << 11 in c0_Context */
1472 * If it is a ckseg0 address, convert to a physical
1473 * address. Shifting right by 29 and adding 4 will
1474 * result in zero for these addresses.
1477 UASM_i_SRA(&p, a1, a0, 29);
1478 UASM_i_ADDIU(&p, a1, a1, 4);
1479 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1481 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1482 uasm_l_tlbl_goaround1(&l, p);
1483 UASM_i_SLL(&p, a0, a0, 11);
1485 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1487 /* PGD in c0_KScratch */
1489 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1493 /* Save PGD to pgd_current[smp_processor_id()] */
1494 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1495 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1496 UASM_i_LA_mostly(&p, a2, pgdc);
1497 UASM_i_ADDU(&p, a2, a2, a1);
1498 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1500 UASM_i_LA_mostly(&p, a2, pgdc);
1501 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1505 /* if pgd_reg is allocated, save PGD also to scratch register */
1507 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1511 if (p >= tlbmiss_handler_setup_pgd_end)
1512 panic("tlbmiss_handler_setup_pgd space exceeded");
1514 uasm_resolve_relocs(relocs, labels);
1515 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1516 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1518 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1519 tlbmiss_handler_setup_pgd_size);
1523 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1526 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1528 uasm_i_lld(p, pte, 0, ptr);
1531 UASM_i_LL(p, pte, 0, ptr);
1533 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1535 uasm_i_ld(p, pte, 0, ptr);
1538 UASM_i_LW(p, pte, 0, ptr);
1543 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1546 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1547 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1549 if (!cpu_has_64bits) {
1550 const int scratch = 1; /* Our extra working register */
1552 uasm_i_lui(p, scratch, (mode >> 16));
1553 uasm_i_or(p, pte, pte, scratch);
1556 uasm_i_ori(p, pte, pte, mode);
1558 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1560 uasm_i_scd(p, pte, 0, ptr);
1563 UASM_i_SC(p, pte, 0, ptr);
1565 if (r10000_llsc_war())
1566 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1568 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1570 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1571 if (!cpu_has_64bits) {
1572 /* no uasm_i_nop needed */
1573 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1574 uasm_i_ori(p, pte, pte, hwmode);
1575 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1576 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1577 /* no uasm_i_nop needed */
1578 uasm_i_lw(p, pte, 0, ptr);
1585 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1587 uasm_i_sd(p, pte, 0, ptr);
1590 UASM_i_SW(p, pte, 0, ptr);
1592 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1593 if (!cpu_has_64bits) {
1594 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1595 uasm_i_ori(p, pte, pte, hwmode);
1596 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1597 uasm_i_lw(p, pte, 0, ptr);
1604 * Check if PTE is present, if not then jump to LABEL. PTR points to
1605 * the page table where this PTE is located, PTE will be re-loaded
1606 * with it's original value.
1609 build_pte_present(u32 **p, struct uasm_reloc **r,
1610 int pte, int ptr, int scratch, enum label_id lid)
1612 int t = scratch >= 0 ? scratch : pte;
1616 if (use_bbit_insns()) {
1617 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1620 if (_PAGE_PRESENT_SHIFT) {
1621 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1624 uasm_i_andi(p, t, cur, 1);
1625 uasm_il_beqz(p, r, t, lid);
1627 /* You lose the SMP race :-(*/
1628 iPTE_LW(p, pte, ptr);
1631 if (_PAGE_PRESENT_SHIFT) {
1632 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1635 uasm_i_andi(p, t, cur,
1636 (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT);
1637 uasm_i_xori(p, t, t,
1638 (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT);
1639 uasm_il_bnez(p, r, t, lid);
1641 /* You lose the SMP race :-(*/
1642 iPTE_LW(p, pte, ptr);
1646 /* Make PTE valid, store result in PTR. */
1648 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1651 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1653 iPTE_SW(p, r, pte, ptr, mode);
1657 * Check if PTE can be written to, if not branch to LABEL. Regardless
1658 * restore PTE with value from PTR when done.
1661 build_pte_writable(u32 **p, struct uasm_reloc **r,
1662 unsigned int pte, unsigned int ptr, int scratch,
1665 int t = scratch >= 0 ? scratch : pte;
1668 if (_PAGE_PRESENT_SHIFT) {
1669 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1672 uasm_i_andi(p, t, cur,
1673 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1674 uasm_i_xori(p, t, t,
1675 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1676 uasm_il_bnez(p, r, t, lid);
1678 /* You lose the SMP race :-(*/
1679 iPTE_LW(p, pte, ptr);
1684 /* Make PTE writable, update software status bits as well, then store
1688 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1691 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1694 iPTE_SW(p, r, pte, ptr, mode);
1698 * Check if PTE can be modified, if not branch to LABEL. Regardless
1699 * restore PTE with value from PTR when done.
1702 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1703 unsigned int pte, unsigned int ptr, int scratch,
1706 if (use_bbit_insns()) {
1707 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1710 int t = scratch >= 0 ? scratch : pte;
1711 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1712 uasm_i_andi(p, t, t, 1);
1713 uasm_il_beqz(p, r, t, lid);
1715 /* You lose the SMP race :-(*/
1716 iPTE_LW(p, pte, ptr);
1720 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1724 * R3000 style TLB load/store/modify handlers.
1728 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1732 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1734 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1735 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1738 uasm_i_rfe(p); /* branch delay */
1742 * This places the pte into ENTRYLO0 and writes it with tlbwi
1743 * or tlbwr as appropriate. This is because the index register
1744 * may have the probe fail bit set as a result of a trap on a
1745 * kseg2 access, i.e. without refill. Then it returns.
1748 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1749 struct uasm_reloc **r, unsigned int pte,
1752 uasm_i_mfc0(p, tmp, C0_INDEX);
1753 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1754 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1755 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1756 uasm_i_tlbwi(p); /* cp0 delay */
1758 uasm_i_rfe(p); /* branch delay */
1759 uasm_l_r3000_write_probe_fail(l, *p);
1760 uasm_i_tlbwr(p); /* cp0 delay */
1762 uasm_i_rfe(p); /* branch delay */
1766 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1769 long pgdc = (long)pgd_current;
1771 uasm_i_mfc0(p, pte, C0_BADVADDR);
1772 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1773 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1774 uasm_i_srl(p, pte, pte, 22); /* load delay */
1775 uasm_i_sll(p, pte, pte, 2);
1776 uasm_i_addu(p, ptr, ptr, pte);
1777 uasm_i_mfc0(p, pte, C0_CONTEXT);
1778 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1779 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1780 uasm_i_addu(p, ptr, ptr, pte);
1781 uasm_i_lw(p, pte, 0, ptr);
1782 uasm_i_tlbp(p); /* load delay */
1785 static void build_r3000_tlb_load_handler(void)
1787 u32 *p = handle_tlbl;
1788 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1789 struct uasm_label *l = labels;
1790 struct uasm_reloc *r = relocs;
1792 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1793 memset(labels, 0, sizeof(labels));
1794 memset(relocs, 0, sizeof(relocs));
1796 build_r3000_tlbchange_handler_head(&p, K0, K1);
1797 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1798 uasm_i_nop(&p); /* load delay */
1799 build_make_valid(&p, &r, K0, K1);
1800 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1802 uasm_l_nopage_tlbl(&l, p);
1803 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1806 if (p >= handle_tlbl_end)
1807 panic("TLB load handler fastpath space exceeded");
1809 uasm_resolve_relocs(relocs, labels);
1810 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1811 (unsigned int)(p - handle_tlbl));
1813 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1816 static void build_r3000_tlb_store_handler(void)
1818 u32 *p = handle_tlbs;
1819 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1820 struct uasm_label *l = labels;
1821 struct uasm_reloc *r = relocs;
1823 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1824 memset(labels, 0, sizeof(labels));
1825 memset(relocs, 0, sizeof(relocs));
1827 build_r3000_tlbchange_handler_head(&p, K0, K1);
1828 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1829 uasm_i_nop(&p); /* load delay */
1830 build_make_write(&p, &r, K0, K1);
1831 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1833 uasm_l_nopage_tlbs(&l, p);
1834 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1837 if (p >= handle_tlbs_end)
1838 panic("TLB store handler fastpath space exceeded");
1840 uasm_resolve_relocs(relocs, labels);
1841 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1842 (unsigned int)(p - handle_tlbs));
1844 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1847 static void build_r3000_tlb_modify_handler(void)
1849 u32 *p = handle_tlbm;
1850 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1851 struct uasm_label *l = labels;
1852 struct uasm_reloc *r = relocs;
1854 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1855 memset(labels, 0, sizeof(labels));
1856 memset(relocs, 0, sizeof(relocs));
1858 build_r3000_tlbchange_handler_head(&p, K0, K1);
1859 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1860 uasm_i_nop(&p); /* load delay */
1861 build_make_write(&p, &r, K0, K1);
1862 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1864 uasm_l_nopage_tlbm(&l, p);
1865 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1868 if (p >= handle_tlbm_end)
1869 panic("TLB modify handler fastpath space exceeded");
1871 uasm_resolve_relocs(relocs, labels);
1872 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1873 (unsigned int)(p - handle_tlbm));
1875 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1877 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1880 * R4000 style TLB load/store/modify handlers.
1882 static struct work_registers
1883 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1884 struct uasm_reloc **r)
1886 struct work_registers wr = build_get_work_registers(p);
1889 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1891 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1894 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1896 * For huge tlb entries, pmd doesn't contain an address but
1897 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1898 * see if we need to jump to huge tlb processing.
1900 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1903 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1904 UASM_i_LW(p, wr.r2, 0, wr.r2);
1905 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1906 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1907 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1910 uasm_l_smp_pgtable_change(l, *p);
1912 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1913 if (!m4kc_tlbp_war()) {
1914 build_tlb_probe_entry(p);
1916 /* race condition happens, leaving */
1918 uasm_i_mfc0(p, wr.r3, C0_INDEX);
1919 uasm_il_bltz(p, r, wr.r3, label_leave);
1927 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1928 struct uasm_reloc **r, unsigned int tmp,
1931 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1932 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1933 build_update_entries(p, tmp, ptr);
1934 build_tlb_write_entry(p, l, r, tlb_indexed);
1935 uasm_l_leave(l, *p);
1936 build_restore_work_registers(p);
1937 uasm_i_eret(p); /* return from trap */
1940 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1944 static void build_r4000_tlb_load_handler(void)
1946 u32 *p = handle_tlbl;
1947 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1948 struct uasm_label *l = labels;
1949 struct uasm_reloc *r = relocs;
1950 struct work_registers wr;
1952 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1953 memset(labels, 0, sizeof(labels));
1954 memset(relocs, 0, sizeof(relocs));
1956 if (bcm1250_m3_war()) {
1957 unsigned int segbits = 44;
1959 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1960 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1961 uasm_i_xor(&p, K0, K0, K1);
1962 uasm_i_dsrl_safe(&p, K1, K0, 62);
1963 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1964 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1965 uasm_i_or(&p, K0, K0, K1);
1966 uasm_il_bnez(&p, &r, K0, label_leave);
1967 /* No need for uasm_i_nop */
1970 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1971 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1972 if (m4kc_tlbp_war())
1973 build_tlb_probe_entry(&p);
1975 if (cpu_has_rixi && !cpu_has_rixiex) {
1977 * If the page is not _PAGE_VALID, RI or XI could not
1978 * have triggered it. Skip the expensive test..
1980 if (use_bbit_insns()) {
1981 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1982 label_tlbl_goaround1);
1984 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1985 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1991 switch (current_cpu_type()) {
1993 if (cpu_has_mips_r2_exec_hazard) {
1996 case CPU_CAVIUM_OCTEON:
1997 case CPU_CAVIUM_OCTEON_PLUS:
1998 case CPU_CAVIUM_OCTEON2:
2003 /* Examine entrylo 0 or 1 based on ptr. */
2004 if (use_bbit_insns()) {
2005 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2007 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2008 uasm_i_beqz(&p, wr.r3, 8);
2010 /* load it in the delay slot*/
2011 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2012 /* load it if ptr is odd */
2013 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2015 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2016 * XI must have triggered it.
2018 if (use_bbit_insns()) {
2019 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2021 uasm_l_tlbl_goaround1(&l, p);
2023 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2024 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2027 uasm_l_tlbl_goaround1(&l, p);
2029 build_make_valid(&p, &r, wr.r1, wr.r2);
2030 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2032 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2034 * This is the entry point when build_r4000_tlbchange_handler_head
2035 * spots a huge page.
2037 uasm_l_tlb_huge_update(&l, p);
2038 iPTE_LW(&p, wr.r1, wr.r2);
2039 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2040 build_tlb_probe_entry(&p);
2042 if (cpu_has_rixi && !cpu_has_rixiex) {
2044 * If the page is not _PAGE_VALID, RI or XI could not
2045 * have triggered it. Skip the expensive test..
2047 if (use_bbit_insns()) {
2048 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2049 label_tlbl_goaround2);
2051 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2052 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2058 switch (current_cpu_type()) {
2060 if (cpu_has_mips_r2_exec_hazard) {
2063 case CPU_CAVIUM_OCTEON:
2064 case CPU_CAVIUM_OCTEON_PLUS:
2065 case CPU_CAVIUM_OCTEON2:
2070 /* Examine entrylo 0 or 1 based on ptr. */
2071 if (use_bbit_insns()) {
2072 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2074 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2075 uasm_i_beqz(&p, wr.r3, 8);
2077 /* load it in the delay slot*/
2078 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2079 /* load it if ptr is odd */
2080 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2082 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2083 * XI must have triggered it.
2085 if (use_bbit_insns()) {
2086 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2088 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2089 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2091 if (PM_DEFAULT_MASK == 0)
2094 * We clobbered C0_PAGEMASK, restore it. On the other branch
2095 * it is restored in build_huge_tlb_write_entry.
2097 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2099 uasm_l_tlbl_goaround2(&l, p);
2101 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2102 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2105 uasm_l_nopage_tlbl(&l, p);
2106 build_restore_work_registers(&p);
2107 #ifdef CONFIG_CPU_MICROMIPS
2108 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2109 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2110 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2114 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2117 if (p >= handle_tlbl_end)
2118 panic("TLB load handler fastpath space exceeded");
2120 uasm_resolve_relocs(relocs, labels);
2121 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2122 (unsigned int)(p - handle_tlbl));
2124 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2127 static void build_r4000_tlb_store_handler(void)
2129 u32 *p = handle_tlbs;
2130 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2131 struct uasm_label *l = labels;
2132 struct uasm_reloc *r = relocs;
2133 struct work_registers wr;
2135 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2136 memset(labels, 0, sizeof(labels));
2137 memset(relocs, 0, sizeof(relocs));
2139 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2140 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2141 if (m4kc_tlbp_war())
2142 build_tlb_probe_entry(&p);
2143 build_make_write(&p, &r, wr.r1, wr.r2);
2144 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2146 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2148 * This is the entry point when
2149 * build_r4000_tlbchange_handler_head spots a huge page.
2151 uasm_l_tlb_huge_update(&l, p);
2152 iPTE_LW(&p, wr.r1, wr.r2);
2153 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2154 build_tlb_probe_entry(&p);
2155 uasm_i_ori(&p, wr.r1, wr.r1,
2156 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2157 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2160 uasm_l_nopage_tlbs(&l, p);
2161 build_restore_work_registers(&p);
2162 #ifdef CONFIG_CPU_MICROMIPS
2163 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2164 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2165 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2169 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2172 if (p >= handle_tlbs_end)
2173 panic("TLB store handler fastpath space exceeded");
2175 uasm_resolve_relocs(relocs, labels);
2176 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2177 (unsigned int)(p - handle_tlbs));
2179 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2182 static void build_r4000_tlb_modify_handler(void)
2184 u32 *p = handle_tlbm;
2185 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2186 struct uasm_label *l = labels;
2187 struct uasm_reloc *r = relocs;
2188 struct work_registers wr;
2190 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2191 memset(labels, 0, sizeof(labels));
2192 memset(relocs, 0, sizeof(relocs));
2194 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2195 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2196 if (m4kc_tlbp_war())
2197 build_tlb_probe_entry(&p);
2198 /* Present and writable bits set, set accessed and dirty bits. */
2199 build_make_write(&p, &r, wr.r1, wr.r2);
2200 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2202 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2204 * This is the entry point when
2205 * build_r4000_tlbchange_handler_head spots a huge page.
2207 uasm_l_tlb_huge_update(&l, p);
2208 iPTE_LW(&p, wr.r1, wr.r2);
2209 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2210 build_tlb_probe_entry(&p);
2211 uasm_i_ori(&p, wr.r1, wr.r1,
2212 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2213 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
2216 uasm_l_nopage_tlbm(&l, p);
2217 build_restore_work_registers(&p);
2218 #ifdef CONFIG_CPU_MICROMIPS
2219 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2220 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2221 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2225 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2228 if (p >= handle_tlbm_end)
2229 panic("TLB modify handler fastpath space exceeded");
2231 uasm_resolve_relocs(relocs, labels);
2232 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2233 (unsigned int)(p - handle_tlbm));
2235 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2238 static void flush_tlb_handlers(void)
2240 local_flush_icache_range((unsigned long)handle_tlbl,
2241 (unsigned long)handle_tlbl_end);
2242 local_flush_icache_range((unsigned long)handle_tlbs,
2243 (unsigned long)handle_tlbs_end);
2244 local_flush_icache_range((unsigned long)handle_tlbm,
2245 (unsigned long)handle_tlbm_end);
2246 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2247 (unsigned long)tlbmiss_handler_setup_pgd_end);
2250 static void print_htw_config(void)
2252 unsigned long config;
2254 const int field = 2 * sizeof(unsigned long);
2256 config = read_c0_pwfield();
2257 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2259 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2260 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2261 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2262 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2263 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2265 config = read_c0_pwsize();
2266 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2268 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2269 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2270 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2271 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2272 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2274 pwctl = read_c0_pwctl();
2275 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2277 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2278 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2279 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2280 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2283 static void config_htw_params(void)
2285 unsigned long pwfield, pwsize, ptei;
2286 unsigned int config;
2289 * We are using 2-level page tables, so we only need to
2290 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2291 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2292 * write values less than 0xc in these fields because the entire
2293 * write will be dropped. As a result of which, we must preserve
2294 * the original reset values and overwrite only what we really want.
2297 pwfield = read_c0_pwfield();
2298 /* re-initialize the GDI field */
2299 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2300 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2301 /* re-initialize the PTI field including the even/odd bit */
2302 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2303 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2304 if (CONFIG_PGTABLE_LEVELS >= 3) {
2305 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2306 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2308 /* Set the PTEI right shift */
2309 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2311 write_c0_pwfield(pwfield);
2312 /* Check whether the PTEI value is supported */
2313 back_to_back_c0_hazard();
2314 pwfield = read_c0_pwfield();
2315 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2317 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2320 * Drop option to avoid HTW being enabled via another path
2323 current_cpu_data.options &= ~MIPS_CPU_HTW;
2327 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2328 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2329 if (CONFIG_PGTABLE_LEVELS >= 3)
2330 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2332 pwsize |= ilog2(sizeof(pte_t)/4) << MIPS_PWSIZE_PTEW_SHIFT;
2334 write_c0_pwsize(pwsize);
2336 /* Make sure everything is set before we enable the HTW */
2337 back_to_back_c0_hazard();
2339 /* Enable HTW and disable the rest of the pwctl fields */
2340 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2341 write_c0_pwctl(config);
2342 pr_info("Hardware Page Table Walker enabled\n");
2347 static void config_xpa_params(void)
2350 unsigned int pagegrain;
2352 if (mips_xpa_disabled) {
2353 pr_info("Extended Physical Addressing (XPA) disabled\n");
2357 pagegrain = read_c0_pagegrain();
2358 write_c0_pagegrain(pagegrain | PG_ELPA);
2359 back_to_back_c0_hazard();
2360 pagegrain = read_c0_pagegrain();
2362 if (pagegrain & PG_ELPA)
2363 pr_info("Extended Physical Addressing (XPA) enabled\n");
2365 panic("Extended Physical Addressing (XPA) disabled");
2369 static void check_pabits(void)
2371 unsigned long entry;
2372 unsigned pabits, fillbits;
2374 if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2376 * We'll only be making use of the fact that we can rotate bits
2377 * into the fill if the CPU supports RIXI, so don't bother
2378 * probing this for CPUs which don't.
2383 write_c0_entrylo0(~0ul);
2384 back_to_back_c0_hazard();
2385 entry = read_c0_entrylo0();
2387 /* clear all non-PFN bits */
2388 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2389 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2391 /* find a lower bound on PABITS, and upper bound on fill bits */
2392 pabits = fls_long(entry) + 6;
2393 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2395 /* minus the RI & XI bits */
2396 fillbits -= min_t(unsigned, fillbits, 2);
2398 if (fillbits >= ilog2(_PAGE_NO_EXEC))
2399 fill_includes_sw_bits = true;
2401 pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2404 void build_tlb_refill_handler(void)
2407 * The refill handler is generated per-CPU, multi-node systems
2408 * may have local storage for it. The other handlers are only
2411 static int run_once = 0;
2413 output_pgtable_bits_defines();
2417 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2420 switch (current_cpu_type()) {
2428 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2429 if (cpu_has_local_ebase)
2430 build_r3000_tlb_refill_handler();
2432 if (!cpu_has_local_ebase)
2433 build_r3000_tlb_refill_handler();
2435 build_r3000_tlb_load_handler();
2436 build_r3000_tlb_store_handler();
2437 build_r3000_tlb_modify_handler();
2438 flush_tlb_handlers();
2442 panic("No R3000 TLB refill handler");
2448 panic("No R6000 TLB refill handler yet");
2452 panic("No R8000 TLB refill handler yet");
2457 scratch_reg = allocate_kscratch();
2459 build_r4000_tlb_load_handler();
2460 build_r4000_tlb_store_handler();
2461 build_r4000_tlb_modify_handler();
2462 if (!cpu_has_local_ebase)
2463 build_r4000_tlb_refill_handler();
2464 flush_tlb_handlers();
2467 if (cpu_has_local_ebase)
2468 build_r4000_tlb_refill_handler();
2470 config_xpa_params();
2472 config_htw_params();