2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 Maciej W. Rozycki
8 * Copyright (C) 2008 Thiemo Seufer
9 * Copyright (C) 2012 MIPS Technologies, Inc.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/smp.h>
15 #include <linux/proc_fs.h>
18 #include <asm/cacheops.h>
19 #include <asm/cpu-type.h>
23 #include <asm/prefetch.h>
24 #include <asm/bootinfo.h>
25 #include <asm/mipsregs.h>
26 #include <asm/mmu_context.h>
29 #ifdef CONFIG_SIBYTE_DMA_PAGEOPS
30 #include <asm/sibyte/sb1250.h>
31 #include <asm/sibyte/sb1250_regs.h>
32 #include <asm/sibyte/sb1250_dma.h>
37 /* Registers used in the assembled routines. */
50 /* Handle labels (which must be positive integers). */
52 label_clear_nopref = 1,
56 label_copy_pref_store,
59 UASM_L_LA(_clear_nopref)
60 UASM_L_LA(_clear_pref)
61 UASM_L_LA(_copy_nopref)
62 UASM_L_LA(_copy_pref_both)
63 UASM_L_LA(_copy_pref_store)
65 /* We need one branch and therefore one relocation per target label. */
66 static struct uasm_label labels[5];
67 static struct uasm_reloc relocs[5];
69 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
70 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
73 * R6 has a limited offset of the pref instruction.
74 * Skip it if the offset is more than 9 bits.
76 #define _uasm_i_pref(a, b, c, d) \
78 if (cpu_has_mips_r6) { \
79 if (c <= 0xff && c >= -0x100) \
80 uasm_i_pref(a, b, c, d);\
82 uasm_i_pref(a, b, c, d); \
86 static int pref_bias_clear_store;
87 static int pref_bias_copy_load;
88 static int pref_bias_copy_store;
90 static u32 pref_src_mode;
91 static u32 pref_dst_mode;
93 static int clear_word_size;
94 static int copy_word_size;
96 static int half_clear_loop_size;
97 static int half_copy_loop_size;
99 static int cache_line_size;
100 #define cache_line_mask() (cache_line_size - 1)
103 pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
105 if (cpu_has_64bit_gp_regs &&
106 IS_ENABLED(CONFIG_CPU_DADDI_WORKAROUNDS) &&
109 uasm_i_lui(buf, T9, uasm_rel_hi(off));
110 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
112 uasm_i_addiu(buf, T9, ZERO, off);
113 uasm_i_daddu(buf, reg1, reg2, T9);
116 uasm_i_lui(buf, T9, uasm_rel_hi(off));
117 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
118 UASM_i_ADDU(buf, reg1, reg2, T9);
120 UASM_i_ADDIU(buf, reg1, reg2, off);
124 static void set_prefetch_parameters(void)
126 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg)
131 if (cpu_has_64bit_gp_regs)
137 * The pref's used here are using "streaming" hints, which cause the
138 * copied data to be kicked out of the cache sooner. A page copy often
139 * ends up copying a lot more data than is commonly used, so this seems
140 * to make sense in terms of reducing cache pollution, but I've no real
141 * performance data to back this up.
143 if (cpu_has_prefetch) {
145 * XXX: Most prefetch bias values in here are based on
148 cache_line_size = cpu_dcache_line_size();
149 switch (current_cpu_type()) {
152 /* These processors only support the Pref_Load. */
153 pref_bias_copy_load = 256;
161 * Those values have been experimentally tuned for an
164 pref_bias_clear_store = 512;
165 pref_bias_copy_load = 256;
166 pref_bias_copy_store = 256;
167 pref_src_mode = Pref_LoadStreamed;
168 pref_dst_mode = Pref_StoreStreamed;
173 pref_bias_clear_store = 128;
174 pref_bias_copy_load = 128;
175 pref_bias_copy_store = 128;
177 * SB1 pass1 Pref_LoadStreamed/Pref_StoreStreamed
180 if (current_cpu_type() == CPU_SB1 &&
181 (current_cpu_data.processor_id & 0xff) < 0x02) {
182 pref_src_mode = Pref_Load;
183 pref_dst_mode = Pref_Store;
185 pref_src_mode = Pref_LoadStreamed;
186 pref_dst_mode = Pref_StoreStreamed;
191 /* Loongson-3 only support the Pref_Load/Pref_Store. */
192 pref_bias_clear_store = 128;
193 pref_bias_copy_load = 128;
194 pref_bias_copy_store = 128;
195 pref_src_mode = Pref_Load;
196 pref_dst_mode = Pref_Store;
200 pref_bias_clear_store = 128;
201 pref_bias_copy_load = 256;
202 pref_bias_copy_store = 128;
203 pref_src_mode = Pref_LoadStreamed;
206 * Bit 30 (Pref_PrepareForStore) has been
207 * removed from MIPS R6. Use bit 5
208 * (Pref_StoreStreamed).
210 pref_dst_mode = Pref_StoreStreamed;
212 pref_dst_mode = Pref_PrepareForStore;
216 if (cpu_has_cache_cdex_s)
217 cache_line_size = cpu_scache_line_size();
218 else if (cpu_has_cache_cdex_p)
219 cache_line_size = cpu_dcache_line_size();
222 * Too much unrolling will overflow the available space in
223 * clear_space_array / copy_page_array.
225 half_clear_loop_size = min(16 * clear_word_size,
226 max(cache_line_size >> 1,
227 4 * clear_word_size));
228 half_copy_loop_size = min(16 * copy_word_size,
229 max(cache_line_size >> 1,
230 4 * copy_word_size));
233 static void build_clear_store(u32 **buf, int off)
235 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) {
236 uasm_i_sd(buf, ZERO, off, A0);
238 uasm_i_sw(buf, ZERO, off, A0);
242 static inline void build_clear_pref(u32 **buf, int off)
244 if (off & cache_line_mask())
247 if (pref_bias_clear_store) {
248 _uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off,
250 } else if (cache_line_size == (half_clear_loop_size << 1)) {
251 if (cpu_has_cache_cdex_s) {
252 uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
253 } else if (cpu_has_cache_cdex_p) {
254 if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
255 cpu_is_r4600_v1_x()) {
262 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
264 uasm_i_lw(buf, ZERO, ZERO, AT);
266 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
271 extern u32 __clear_page_start;
272 extern u32 __clear_page_end;
273 extern u32 __copy_page_start;
274 extern u32 __copy_page_end;
276 void build_clear_page(void)
279 u32 *buf = &__clear_page_start;
280 struct uasm_label *l = labels;
281 struct uasm_reloc *r = relocs;
283 static atomic_t run_once = ATOMIC_INIT(0);
285 if (atomic_xchg(&run_once, 1)) {
289 memset(labels, 0, sizeof(labels));
290 memset(relocs, 0, sizeof(relocs));
292 set_prefetch_parameters();
295 * This algorithm makes the following assumptions:
296 * - The prefetch bias is a multiple of 2 words.
297 * - The prefetch bias is less than one page.
299 BUG_ON(pref_bias_clear_store % (2 * clear_word_size));
300 BUG_ON(PAGE_SIZE < pref_bias_clear_store);
302 off = PAGE_SIZE - pref_bias_clear_store;
303 if (off > 0xffff || !pref_bias_clear_store)
304 pg_addiu(&buf, A2, A0, off);
306 uasm_i_ori(&buf, A2, A0, off);
308 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
309 uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
311 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
312 * cache_line_size : 0;
314 build_clear_pref(&buf, -off);
315 off -= cache_line_size;
317 uasm_l_clear_pref(&l, buf);
319 build_clear_pref(&buf, off);
320 build_clear_store(&buf, off);
321 off += clear_word_size;
322 } while (off < half_clear_loop_size);
323 pg_addiu(&buf, A0, A0, 2 * off);
326 build_clear_pref(&buf, off);
327 if (off == -clear_word_size)
328 uasm_il_bne(&buf, &r, A0, A2, label_clear_pref);
329 build_clear_store(&buf, off);
330 off += clear_word_size;
333 if (pref_bias_clear_store) {
334 pg_addiu(&buf, A2, A0, pref_bias_clear_store);
335 uasm_l_clear_nopref(&l, buf);
338 build_clear_store(&buf, off);
339 off += clear_word_size;
340 } while (off < half_clear_loop_size);
341 pg_addiu(&buf, A0, A0, 2 * off);
344 if (off == -clear_word_size)
345 uasm_il_bne(&buf, &r, A0, A2,
347 build_clear_store(&buf, off);
348 off += clear_word_size;
355 BUG_ON(buf > &__clear_page_end);
357 uasm_resolve_relocs(relocs, labels);
359 pr_debug("Synthesized clear page handler (%u instructions).\n",
360 (u32)(buf - &__clear_page_start));
362 pr_debug("\t.set push\n");
363 pr_debug("\t.set noreorder\n");
364 for (i = 0; i < (buf - &__clear_page_start); i++)
365 pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
366 pr_debug("\t.set pop\n");
369 static void build_copy_load(u32 **buf, int reg, int off)
371 if (cpu_has_64bit_gp_regs) {
372 uasm_i_ld(buf, reg, off, A1);
374 uasm_i_lw(buf, reg, off, A1);
378 static void build_copy_store(u32 **buf, int reg, int off)
380 if (cpu_has_64bit_gp_regs) {
381 uasm_i_sd(buf, reg, off, A0);
383 uasm_i_sw(buf, reg, off, A0);
387 static inline void build_copy_load_pref(u32 **buf, int off)
389 if (off & cache_line_mask())
392 if (pref_bias_copy_load)
393 _uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1);
396 static inline void build_copy_store_pref(u32 **buf, int off)
398 if (off & cache_line_mask())
401 if (pref_bias_copy_store) {
402 _uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off,
404 } else if (cache_line_size == (half_copy_loop_size << 1)) {
405 if (cpu_has_cache_cdex_s) {
406 uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
407 } else if (cpu_has_cache_cdex_p) {
408 if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
409 cpu_is_r4600_v1_x()) {
416 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
418 uasm_i_lw(buf, ZERO, ZERO, AT);
420 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
425 void build_copy_page(void)
428 u32 *buf = &__copy_page_start;
429 struct uasm_label *l = labels;
430 struct uasm_reloc *r = relocs;
432 static atomic_t run_once = ATOMIC_INIT(0);
434 if (atomic_xchg(&run_once, 1)) {
438 memset(labels, 0, sizeof(labels));
439 memset(relocs, 0, sizeof(relocs));
441 set_prefetch_parameters();
444 * This algorithm makes the following assumptions:
445 * - All prefetch biases are multiples of 8 words.
446 * - The prefetch biases are less than one page.
447 * - The store prefetch bias isn't greater than the load
450 BUG_ON(pref_bias_copy_load % (8 * copy_word_size));
451 BUG_ON(pref_bias_copy_store % (8 * copy_word_size));
452 BUG_ON(PAGE_SIZE < pref_bias_copy_load);
453 BUG_ON(pref_bias_copy_store > pref_bias_copy_load);
455 off = PAGE_SIZE - pref_bias_copy_load;
456 if (off > 0xffff || !pref_bias_copy_load)
457 pg_addiu(&buf, A2, A0, off);
459 uasm_i_ori(&buf, A2, A0, off);
461 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
462 uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
464 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
467 build_copy_load_pref(&buf, -off);
468 off -= cache_line_size;
470 off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) *
473 build_copy_store_pref(&buf, -off);
474 off -= cache_line_size;
476 uasm_l_copy_pref_both(&l, buf);
478 build_copy_load_pref(&buf, off);
479 build_copy_load(&buf, T0, off);
480 build_copy_load_pref(&buf, off + copy_word_size);
481 build_copy_load(&buf, T1, off + copy_word_size);
482 build_copy_load_pref(&buf, off + 2 * copy_word_size);
483 build_copy_load(&buf, T2, off + 2 * copy_word_size);
484 build_copy_load_pref(&buf, off + 3 * copy_word_size);
485 build_copy_load(&buf, T3, off + 3 * copy_word_size);
486 build_copy_store_pref(&buf, off);
487 build_copy_store(&buf, T0, off);
488 build_copy_store_pref(&buf, off + copy_word_size);
489 build_copy_store(&buf, T1, off + copy_word_size);
490 build_copy_store_pref(&buf, off + 2 * copy_word_size);
491 build_copy_store(&buf, T2, off + 2 * copy_word_size);
492 build_copy_store_pref(&buf, off + 3 * copy_word_size);
493 build_copy_store(&buf, T3, off + 3 * copy_word_size);
494 off += 4 * copy_word_size;
495 } while (off < half_copy_loop_size);
496 pg_addiu(&buf, A1, A1, 2 * off);
497 pg_addiu(&buf, A0, A0, 2 * off);
500 build_copy_load_pref(&buf, off);
501 build_copy_load(&buf, T0, off);
502 build_copy_load_pref(&buf, off + copy_word_size);
503 build_copy_load(&buf, T1, off + copy_word_size);
504 build_copy_load_pref(&buf, off + 2 * copy_word_size);
505 build_copy_load(&buf, T2, off + 2 * copy_word_size);
506 build_copy_load_pref(&buf, off + 3 * copy_word_size);
507 build_copy_load(&buf, T3, off + 3 * copy_word_size);
508 build_copy_store_pref(&buf, off);
509 build_copy_store(&buf, T0, off);
510 build_copy_store_pref(&buf, off + copy_word_size);
511 build_copy_store(&buf, T1, off + copy_word_size);
512 build_copy_store_pref(&buf, off + 2 * copy_word_size);
513 build_copy_store(&buf, T2, off + 2 * copy_word_size);
514 build_copy_store_pref(&buf, off + 3 * copy_word_size);
515 if (off == -(4 * copy_word_size))
516 uasm_il_bne(&buf, &r, A2, A0, label_copy_pref_both);
517 build_copy_store(&buf, T3, off + 3 * copy_word_size);
518 off += 4 * copy_word_size;
521 if (pref_bias_copy_load - pref_bias_copy_store) {
522 pg_addiu(&buf, A2, A0,
523 pref_bias_copy_load - pref_bias_copy_store);
524 uasm_l_copy_pref_store(&l, buf);
527 build_copy_load(&buf, T0, off);
528 build_copy_load(&buf, T1, off + copy_word_size);
529 build_copy_load(&buf, T2, off + 2 * copy_word_size);
530 build_copy_load(&buf, T3, off + 3 * copy_word_size);
531 build_copy_store_pref(&buf, off);
532 build_copy_store(&buf, T0, off);
533 build_copy_store_pref(&buf, off + copy_word_size);
534 build_copy_store(&buf, T1, off + copy_word_size);
535 build_copy_store_pref(&buf, off + 2 * copy_word_size);
536 build_copy_store(&buf, T2, off + 2 * copy_word_size);
537 build_copy_store_pref(&buf, off + 3 * copy_word_size);
538 build_copy_store(&buf, T3, off + 3 * copy_word_size);
539 off += 4 * copy_word_size;
540 } while (off < half_copy_loop_size);
541 pg_addiu(&buf, A1, A1, 2 * off);
542 pg_addiu(&buf, A0, A0, 2 * off);
545 build_copy_load(&buf, T0, off);
546 build_copy_load(&buf, T1, off + copy_word_size);
547 build_copy_load(&buf, T2, off + 2 * copy_word_size);
548 build_copy_load(&buf, T3, off + 3 * copy_word_size);
549 build_copy_store_pref(&buf, off);
550 build_copy_store(&buf, T0, off);
551 build_copy_store_pref(&buf, off + copy_word_size);
552 build_copy_store(&buf, T1, off + copy_word_size);
553 build_copy_store_pref(&buf, off + 2 * copy_word_size);
554 build_copy_store(&buf, T2, off + 2 * copy_word_size);
555 build_copy_store_pref(&buf, off + 3 * copy_word_size);
556 if (off == -(4 * copy_word_size))
557 uasm_il_bne(&buf, &r, A2, A0,
558 label_copy_pref_store);
559 build_copy_store(&buf, T3, off + 3 * copy_word_size);
560 off += 4 * copy_word_size;
564 if (pref_bias_copy_store) {
565 pg_addiu(&buf, A2, A0, pref_bias_copy_store);
566 uasm_l_copy_nopref(&l, buf);
569 build_copy_load(&buf, T0, off);
570 build_copy_load(&buf, T1, off + copy_word_size);
571 build_copy_load(&buf, T2, off + 2 * copy_word_size);
572 build_copy_load(&buf, T3, off + 3 * copy_word_size);
573 build_copy_store(&buf, T0, off);
574 build_copy_store(&buf, T1, off + copy_word_size);
575 build_copy_store(&buf, T2, off + 2 * copy_word_size);
576 build_copy_store(&buf, T3, off + 3 * copy_word_size);
577 off += 4 * copy_word_size;
578 } while (off < half_copy_loop_size);
579 pg_addiu(&buf, A1, A1, 2 * off);
580 pg_addiu(&buf, A0, A0, 2 * off);
583 build_copy_load(&buf, T0, off);
584 build_copy_load(&buf, T1, off + copy_word_size);
585 build_copy_load(&buf, T2, off + 2 * copy_word_size);
586 build_copy_load(&buf, T3, off + 3 * copy_word_size);
587 build_copy_store(&buf, T0, off);
588 build_copy_store(&buf, T1, off + copy_word_size);
589 build_copy_store(&buf, T2, off + 2 * copy_word_size);
590 if (off == -(4 * copy_word_size))
591 uasm_il_bne(&buf, &r, A2, A0,
593 build_copy_store(&buf, T3, off + 3 * copy_word_size);
594 off += 4 * copy_word_size;
601 BUG_ON(buf > &__copy_page_end);
603 uasm_resolve_relocs(relocs, labels);
605 pr_debug("Synthesized copy page handler (%u instructions).\n",
606 (u32)(buf - &__copy_page_start));
608 pr_debug("\t.set push\n");
609 pr_debug("\t.set noreorder\n");
610 for (i = 0; i < (buf - &__copy_page_start); i++)
611 pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
612 pr_debug("\t.set pop\n");
615 #ifdef CONFIG_SIBYTE_DMA_PAGEOPS
616 extern void clear_page_cpu(void *page);
617 extern void copy_page_cpu(void *to, void *from);
620 * Pad descriptors to cacheline, since each is exclusively owned by a
628 } ____cacheline_aligned_in_smp page_descr[DM_NUM_CHANNELS];
630 void clear_page(void *page)
632 u64 to_phys = CPHYSADDR((unsigned long)page);
633 unsigned int cpu = smp_processor_id();
635 /* if the page is not in KSEG0, use old way */
636 if ((long)KSEGX((unsigned long)page) != (long)CKSEG0)
637 return clear_page_cpu(page);
639 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
640 M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
641 page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
642 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
645 * Don't really want to do it this way, but there's no
646 * reliable way to delay completion detection.
648 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
649 & M_DM_DSCR_BASE_INTERRUPT))
651 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
653 EXPORT_SYMBOL(clear_page);
655 void copy_page(void *to, void *from)
657 u64 from_phys = CPHYSADDR((unsigned long)from);
658 u64 to_phys = CPHYSADDR((unsigned long)to);
659 unsigned int cpu = smp_processor_id();
661 /* if any page is not in KSEG0, use old way */
662 if ((long)KSEGX((unsigned long)to) != (long)CKSEG0
663 || (long)KSEGX((unsigned long)from) != (long)CKSEG0)
664 return copy_page_cpu(to, from);
666 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
667 M_DM_DSCRA_INTERRUPT;
668 page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
669 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
672 * Don't really want to do it this way, but there's no
673 * reliable way to delay completion detection.
675 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
676 & M_DM_DSCR_BASE_INTERRUPT))
678 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
680 EXPORT_SYMBOL(copy_page);
682 #endif /* CONFIG_SIBYTE_DMA_PAGEOPS */