arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/cpu_pm.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/init.h>
  13 #include <linux/highmem.h>
  14 #include <linux/kernel.h>
  15 #include <linux/linkage.h>
  16 #include <linux/preempt.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/mm.h>
  20 #include <linux/export.h>
  21 #include <linux/bitops.h>
  22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
  23
  24 #include <asm/bcache.h>
  25 #include <asm/bootinfo.h>
  26 #include <asm/cache.h>
  27 #include <asm/cacheops.h>
  28 #include <asm/cpu.h>
  29 #include <asm/cpu-features.h>
  30 #include <asm/cpu-type.h>
  31 #include <asm/io.h>
  32 #include <asm/page.h>
  33 #include <asm/r4kcache.h>
  34 #include <asm/sections.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/cacheflush.h> /* for run_uncached() */
  37 #include <asm/traps.h>
  38 #include <asm/mips-cps.h>
  39
  40 /*
  41  * Bits describing what cache ops an SMP callback function may perform.
  42  *
  43  * R4K_HIT   -  Virtual user or kernel address based cache operations. The
  44  *              active_mm must be checked before using user addresses, falling
  45  *              back to kmap.
  46  * R4K_INDEX -  Index based cache operations.
  47  */
  48
  49 #define R4K_HIT         BIT(0)
  50 #define R4K_INDEX       BIT(1)
  51
  52 /**
  53  * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
  54  * @type:       Type of cache operations (R4K_HIT or R4K_INDEX).
  55  *
  56  * Decides whether a cache op needs to be performed on every core in the system.
  57  * This may change depending on the @type of cache operation, as well as the set
  58  * of online CPUs, so preemption should be disabled by the caller to prevent CPU
  59  * hotplug from changing the result.
  60  *
  61  * Returns:     1 if the cache operation @type should be done on every core in
  62  *              the system.
  63  *              0 if the cache operation @type is globalized and only needs to
  64  *              be performed on a simple CPU.
  65  */
  66 static inline bool r4k_op_needs_ipi(unsigned int type)
  67 {
  68         /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
  69         if (type == R4K_HIT && mips_cm_present())
  70                 return false;
  71
  72         /*
  73          * Hardware doesn't globalize the required cache ops, so SMP calls may
  74          * be needed, but only if there are foreign CPUs (non-siblings with
  75          * separate caches).
  76          */
  77         /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
  78 #ifdef CONFIG_SMP
  79         return !cpumask_empty(&cpu_foreign_map[0]);
  80 #else
  81         return false;
  82 #endif
  83 }
  84
  85 /*
  86  * Special Variant of smp_call_function for use by cache functions:
  87  *
  88  *  o No return value
  89  *  o collapses to normal function call on UP kernels
  90  *  o collapses to normal function call on systems with a single shared
  91  *    primary cache.
  92  *  o doesn't disable interrupts on the local CPU
  93  */
  94 static inline void r4k_on_each_cpu(unsigned int type,
  95                                    void (*func)(void *info), void *info)
  96 {
  97         preempt_disable();
  98         if (r4k_op_needs_ipi(type))
  99                 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
 100                                        func, info, 1);
 101         func(info);
 102         preempt_enable();
 103 }
 104
 105 /*
 106  * Must die.
 107  */
 108 static unsigned long icache_size __read_mostly;
 109 static unsigned long dcache_size __read_mostly;
 110 static unsigned long vcache_size __read_mostly;
 111 static unsigned long scache_size __read_mostly;
 112
 113 /*
 114  * Dummy cache handling routines for machines without boardcaches
 115  */
 116 static void cache_noop(void) {}
 117
 118 static struct bcache_ops no_sc_ops = {
 119         .bc_enable = (void *)cache_noop,
 120         .bc_disable = (void *)cache_noop,
 121         .bc_wback_inv = (void *)cache_noop,
 122         .bc_inv = (void *)cache_noop
 123 };
 124
 125 struct bcache_ops *bcops = &no_sc_ops;
 126
 127 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
 128 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 129
 130 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
 131 do {                                                                    \
 132         if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&              \
 133             cpu_is_r4600_v2_x())                                        \
 134                 *(volatile unsigned long *)CKSEG1;                      \
 135         if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP))                                        \
 136                 __asm__ __volatile__("nop;nop;nop;nop");                \
 137 } while (0)
 138
 139 static void (*r4k_blast_dcache_page)(unsigned long addr);
 140
 141 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 142 {
 143         R4600_HIT_CACHEOP_WAR_IMPL;
 144         blast_dcache32_page(addr);
 145 }
 146
 147 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 148 {
 149         blast_dcache64_page(addr);
 150 }
 151
 152 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
 153 {
 154         blast_dcache128_page(addr);
 155 }
 156
 157 static void r4k_blast_dcache_page_setup(void)
 158 {
 159         unsigned long  dc_lsize = cpu_dcache_line_size();
 160
 161         switch (dc_lsize) {
 162         case 0:
 163                 r4k_blast_dcache_page = (void *)cache_noop;
 164                 break;
 165         case 16:
 166                 r4k_blast_dcache_page = blast_dcache16_page;
 167                 break;
 168         case 32:
 169                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 170                 break;
 171         case 64:
 172                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 173                 break;
 174         case 128:
 175                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
 176                 break;
 177         default:
 178                 break;
 179         }
 180 }
 181
 182 #ifndef CONFIG_EVA
 183 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
 184 #else
 185
 186 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
 187
 188 static void r4k_blast_dcache_user_page_setup(void)
 189 {
 190         unsigned long  dc_lsize = cpu_dcache_line_size();
 191
 192         if (dc_lsize == 0)
 193                 r4k_blast_dcache_user_page = (void *)cache_noop;
 194         else if (dc_lsize == 16)
 195                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
 196         else if (dc_lsize == 32)
 197                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
 198         else if (dc_lsize == 64)
 199                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
 200 }
 201
 202 #endif
 203
 204 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 205
 206 static void r4k_blast_dcache_page_indexed_setup(void)
 207 {
 208         unsigned long dc_lsize = cpu_dcache_line_size();
 209
 210         if (dc_lsize == 0)
 211                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 212         else if (dc_lsize == 16)
 213                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 214         else if (dc_lsize == 32)
 215                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 216         else if (dc_lsize == 64)
 217                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 218         else if (dc_lsize == 128)
 219                 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
 220 }
 221
 222 void (* r4k_blast_dcache)(void);
 223 EXPORT_SYMBOL(r4k_blast_dcache);
 224
 225 static void r4k_blast_dcache_setup(void)
 226 {
 227         unsigned long dc_lsize = cpu_dcache_line_size();
 228
 229         if (dc_lsize == 0)
 230                 r4k_blast_dcache = (void *)cache_noop;
 231         else if (dc_lsize == 16)
 232                 r4k_blast_dcache = blast_dcache16;
 233         else if (dc_lsize == 32)
 234                 r4k_blast_dcache = blast_dcache32;
 235         else if (dc_lsize == 64)
 236                 r4k_blast_dcache = blast_dcache64;
 237         else if (dc_lsize == 128)
 238                 r4k_blast_dcache = blast_dcache128;
 239 }
 240
 241 /* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
 242 #define JUMP_TO_ALIGN(order) \
 243         __asm__ __volatile__( \
 244                 "b\t1f\n\t" \
 245                 ".align\t" #order "\n\t" \
 246                 "1:\n\t" \
 247                 )
 248 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 249 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 250
 251 static inline void blast_r4600_v1_icache32(void)
 252 {
 253         unsigned long flags;
 254
 255         local_irq_save(flags);
 256         blast_icache32();
 257         local_irq_restore(flags);
 258 }
 259
 260 static inline void tx49_blast_icache32(void)
 261 {
 262         unsigned long start = INDEX_BASE;
 263         unsigned long end = start + current_cpu_data.icache.waysize;
 264         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 265         unsigned long ws_end = current_cpu_data.icache.ways <<
 266                                current_cpu_data.icache.waybit;
 267         unsigned long ws, addr;
 268
 269         CACHE32_UNROLL32_ALIGN2;
 270         /* I'm in even chunk.  blast odd chunks */
 271         for (ws = 0; ws < ws_end; ws += ws_inc)
 272                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 273                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 274                                      addr | ws, 32);
 275         CACHE32_UNROLL32_ALIGN;
 276         /* I'm in odd chunk.  blast even chunks */
 277         for (ws = 0; ws < ws_end; ws += ws_inc)
 278                 for (addr = start; addr < end; addr += 0x400 * 2)
 279                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 280                                      addr | ws, 32);
 281 }
 282
 283 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 284 {
 285         unsigned long flags;
 286
 287         local_irq_save(flags);
 288         blast_icache32_page_indexed(page);
 289         local_irq_restore(flags);
 290 }
 291
 292 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 293 {
 294         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 295         unsigned long start = INDEX_BASE + (page & indexmask);
 296         unsigned long end = start + PAGE_SIZE;
 297         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 298         unsigned long ws_end = current_cpu_data.icache.ways <<
 299                                current_cpu_data.icache.waybit;
 300         unsigned long ws, addr;
 301
 302         CACHE32_UNROLL32_ALIGN2;
 303         /* I'm in even chunk.  blast odd chunks */
 304         for (ws = 0; ws < ws_end; ws += ws_inc)
 305                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 306                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 307                                      addr | ws, 32);
 308         CACHE32_UNROLL32_ALIGN;
 309         /* I'm in odd chunk.  blast even chunks */
 310         for (ws = 0; ws < ws_end; ws += ws_inc)
 311                 for (addr = start; addr < end; addr += 0x400 * 2)
 312                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 313                                      addr | ws, 32);
 314 }
 315
 316 static void (* r4k_blast_icache_page)(unsigned long addr);
 317
 318 static void r4k_blast_icache_page_setup(void)
 319 {
 320         unsigned long ic_lsize = cpu_icache_line_size();
 321
 322         if (ic_lsize == 0)
 323                 r4k_blast_icache_page = (void *)cache_noop;
 324         else if (ic_lsize == 16)
 325                 r4k_blast_icache_page = blast_icache16_page;
 326         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
 327                 r4k_blast_icache_page = loongson2_blast_icache32_page;
 328         else if (ic_lsize == 32)
 329                 r4k_blast_icache_page = blast_icache32_page;
 330         else if (ic_lsize == 64)
 331                 r4k_blast_icache_page = blast_icache64_page;
 332         else if (ic_lsize == 128)
 333                 r4k_blast_icache_page = blast_icache128_page;
 334 }
 335
 336 #ifndef CONFIG_EVA
 337 #define r4k_blast_icache_user_page  r4k_blast_icache_page
 338 #else
 339
 340 static void (*r4k_blast_icache_user_page)(unsigned long addr);
 341
 342 static void r4k_blast_icache_user_page_setup(void)
 343 {
 344         unsigned long ic_lsize = cpu_icache_line_size();
 345
 346         if (ic_lsize == 0)
 347                 r4k_blast_icache_user_page = (void *)cache_noop;
 348         else if (ic_lsize == 16)
 349                 r4k_blast_icache_user_page = blast_icache16_user_page;
 350         else if (ic_lsize == 32)
 351                 r4k_blast_icache_user_page = blast_icache32_user_page;
 352         else if (ic_lsize == 64)
 353                 r4k_blast_icache_user_page = blast_icache64_user_page;
 354 }
 355
 356 #endif
 357
 358 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 359
 360 static void r4k_blast_icache_page_indexed_setup(void)
 361 {
 362         unsigned long ic_lsize = cpu_icache_line_size();
 363
 364         if (ic_lsize == 0)
 365                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 366         else if (ic_lsize == 16)
 367                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 368         else if (ic_lsize == 32) {
 369                 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
 370                     cpu_is_r4600_v1_x())
 371                         r4k_blast_icache_page_indexed =
 372                                 blast_icache32_r4600_v1_page_indexed;
 373                 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
 374                         r4k_blast_icache_page_indexed =
 375                                 tx49_blast_icache32_page_indexed;
 376                 else if (current_cpu_type() == CPU_LOONGSON2EF)
 377                         r4k_blast_icache_page_indexed =
 378                                 loongson2_blast_icache32_page_indexed;
 379                 else
 380                         r4k_blast_icache_page_indexed =
 381                                 blast_icache32_page_indexed;
 382         } else if (ic_lsize == 64)
 383                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 384 }
 385
 386 void (* r4k_blast_icache)(void);
 387 EXPORT_SYMBOL(r4k_blast_icache);
 388
 389 static void r4k_blast_icache_setup(void)
 390 {
 391         unsigned long ic_lsize = cpu_icache_line_size();
 392
 393         if (ic_lsize == 0)
 394                 r4k_blast_icache = (void *)cache_noop;
 395         else if (ic_lsize == 16)
 396                 r4k_blast_icache = blast_icache16;
 397         else if (ic_lsize == 32) {
 398                 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
 399                     cpu_is_r4600_v1_x())
 400                         r4k_blast_icache = blast_r4600_v1_icache32;
 401                 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
 402                         r4k_blast_icache = tx49_blast_icache32;
 403                 else if (current_cpu_type() == CPU_LOONGSON2EF)
 404                         r4k_blast_icache = loongson2_blast_icache32;
 405                 else
 406                         r4k_blast_icache = blast_icache32;
 407         } else if (ic_lsize == 64)
 408                 r4k_blast_icache = blast_icache64;
 409         else if (ic_lsize == 128)
 410                 r4k_blast_icache = blast_icache128;
 411 }
 412
 413 static void (* r4k_blast_scache_page)(unsigned long addr);
 414
 415 static void r4k_blast_scache_page_setup(void)
 416 {
 417         unsigned long sc_lsize = cpu_scache_line_size();
 418
 419         if (scache_size == 0)
 420                 r4k_blast_scache_page = (void *)cache_noop;
 421         else if (sc_lsize == 16)
 422                 r4k_blast_scache_page = blast_scache16_page;
 423         else if (sc_lsize == 32)
 424                 r4k_blast_scache_page = blast_scache32_page;
 425         else if (sc_lsize == 64)
 426                 r4k_blast_scache_page = blast_scache64_page;
 427         else if (sc_lsize == 128)
 428                 r4k_blast_scache_page = blast_scache128_page;
 429 }
 430
 431 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 432
 433 static void r4k_blast_scache_page_indexed_setup(void)
 434 {
 435         unsigned long sc_lsize = cpu_scache_line_size();
 436
 437         if (scache_size == 0)
 438                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 439         else if (sc_lsize == 16)
 440                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 441         else if (sc_lsize == 32)
 442                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 443         else if (sc_lsize == 64)
 444                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 445         else if (sc_lsize == 128)
 446                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 447 }
 448
 449 static void (* r4k_blast_scache)(void);
 450
 451 static void r4k_blast_scache_setup(void)
 452 {
 453         unsigned long sc_lsize = cpu_scache_line_size();
 454
 455         if (scache_size == 0)
 456                 r4k_blast_scache = (void *)cache_noop;
 457         else if (sc_lsize == 16)
 458                 r4k_blast_scache = blast_scache16;
 459         else if (sc_lsize == 32)
 460                 r4k_blast_scache = blast_scache32;
 461         else if (sc_lsize == 64)
 462                 r4k_blast_scache = blast_scache64;
 463         else if (sc_lsize == 128)
 464                 r4k_blast_scache = blast_scache128;
 465 }
 466
 467 static void (*r4k_blast_scache_node)(long node);
 468
 469 static void r4k_blast_scache_node_setup(void)
 470 {
 471         unsigned long sc_lsize = cpu_scache_line_size();
 472
 473         if (current_cpu_type() != CPU_LOONGSON64)
 474                 r4k_blast_scache_node = (void *)cache_noop;
 475         else if (sc_lsize == 16)
 476                 r4k_blast_scache_node = blast_scache16_node;
 477         else if (sc_lsize == 32)
 478                 r4k_blast_scache_node = blast_scache32_node;
 479         else if (sc_lsize == 64)
 480                 r4k_blast_scache_node = blast_scache64_node;
 481         else if (sc_lsize == 128)
 482                 r4k_blast_scache_node = blast_scache128_node;
 483 }
 484
 485 static inline void local_r4k___flush_cache_all(void * args)
 486 {
 487         switch (current_cpu_type()) {
 488         case CPU_LOONGSON2EF:
 489         case CPU_R4000SC:
 490         case CPU_R4000MC:
 491         case CPU_R4400SC:
 492         case CPU_R4400MC:
 493         case CPU_R10000:
 494         case CPU_R12000:
 495         case CPU_R14000:
 496         case CPU_R16000:
 497                 /*
 498                  * These caches are inclusive caches, that is, if something
 499                  * is not cached in the S-cache, we know it also won't be
 500                  * in one of the primary caches.
 501                  */
 502                 r4k_blast_scache();
 503                 break;
 504
 505         case CPU_LOONGSON64:
 506                 /* Use get_ebase_cpunum() for both NUMA=y/n */
 507                 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
 508                 break;
 509
 510         case CPU_BMIPS5000:
 511                 r4k_blast_scache();
 512                 __sync();
 513                 break;
 514
 515         default:
 516                 r4k_blast_dcache();
 517                 r4k_blast_icache();
 518                 break;
 519         }
 520 }
 521
 522 static void r4k___flush_cache_all(void)
 523 {
 524         r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
 525 }
 526
 527 /**
 528  * has_valid_asid() - Determine if an mm already has an ASID.
 529  * @mm:         Memory map.
 530  * @type:       R4K_HIT or R4K_INDEX, type of cache op.
 531  *
 532  * Determines whether @mm already has an ASID on any of the CPUs which cache ops
 533  * of type @type within an r4k_on_each_cpu() call will affect. If
 534  * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
 535  * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
 536  * will need to be checked.
 537  *
 538  * Must be called in non-preemptive context.
 539  *
 540  * Returns:     1 if the CPUs affected by @type cache ops have an ASID for @mm.
 541  *              0 otherwise.
 542  */
 543 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
 544 {
 545         unsigned int i;
 546         const cpumask_t *mask = cpu_present_mask;
 547
 548         if (cpu_has_mmid)
 549                 return cpu_context(0, mm) != 0;
 550
 551         /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
 552 #ifdef CONFIG_SMP
 553         /*
 554          * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
 555          * each foreign core, so we only need to worry about siblings.
 556          * Otherwise we need to worry about all present CPUs.
 557          */
 558         if (r4k_op_needs_ipi(type))
 559                 mask = &cpu_sibling_map[smp_processor_id()];
 560 #endif
 561         for_each_cpu(i, mask)
 562                 if (cpu_context(i, mm))
 563                         return 1;
 564         return 0;
 565 }
 566
 567 static void r4k__flush_cache_vmap(void)
 568 {
 569         r4k_blast_dcache();
 570 }
 571
 572 static void r4k__flush_cache_vunmap(void)
 573 {
 574         r4k_blast_dcache();
 575 }
 576
 577 /*
 578  * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
 579  * whole caches when vma is executable.
 580  */
 581 static inline void local_r4k_flush_cache_range(void * args)
 582 {
 583         struct vm_area_struct *vma = args;
 584         int exec = vma->vm_flags & VM_EXEC;
 585
 586         if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
 587                 return;
 588
 589         /*
 590          * If dcache can alias, we must blast it since mapping is changing.
 591          * If executable, we must ensure any dirty lines are written back far
 592          * enough to be visible to icache.
 593          */
 594         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 595                 r4k_blast_dcache();
 596         /* If executable, blast stale lines from icache */
 597         if (exec)
 598                 r4k_blast_icache();
 599 }
 600
 601 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 602         unsigned long start, unsigned long end)
 603 {
 604         int exec = vma->vm_flags & VM_EXEC;
 605
 606         if (cpu_has_dc_aliases || exec)
 607                 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
 608 }
 609
 610 static inline void local_r4k_flush_cache_mm(void * args)
 611 {
 612         struct mm_struct *mm = args;
 613
 614         if (!has_valid_asid(mm, R4K_INDEX))
 615                 return;
 616
 617         /*
 618          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 619          * only flush the primary caches but R1x000 behave sane ...
 620          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 621          * caches, so we can bail out early.
 622          */
 623         if (current_cpu_type() == CPU_R4000SC ||
 624             current_cpu_type() == CPU_R4000MC ||
 625             current_cpu_type() == CPU_R4400SC ||
 626             current_cpu_type() == CPU_R4400MC) {
 627                 r4k_blast_scache();
 628                 return;
 629         }
 630
 631         r4k_blast_dcache();
 632 }
 633
 634 static void r4k_flush_cache_mm(struct mm_struct *mm)
 635 {
 636         if (!cpu_has_dc_aliases)
 637                 return;
 638
 639         r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
 640 }
 641
 642 struct flush_cache_page_args {
 643         struct vm_area_struct *vma;
 644         unsigned long addr;
 645         unsigned long pfn;
 646 };
 647
 648 static inline void local_r4k_flush_cache_page(void *args)
 649 {
 650         struct flush_cache_page_args *fcp_args = args;
 651         struct vm_area_struct *vma = fcp_args->vma;
 652         unsigned long addr = fcp_args->addr;
 653         struct page *page = pfn_to_page(fcp_args->pfn);
 654         int exec = vma->vm_flags & VM_EXEC;
 655         struct mm_struct *mm = vma->vm_mm;
 656         int map_coherent = 0;
 657         pmd_t *pmdp;
 658         pte_t *ptep;
 659         void *vaddr;
 660
 661         /*
 662          * If owns no valid ASID yet, cannot possibly have gotten
 663          * this page into the cache.
 664          */
 665         if (!has_valid_asid(mm, R4K_HIT))
 666                 return;
 667
 668         addr &= PAGE_MASK;
 669         pmdp = pmd_off(mm, addr);
 670         ptep = pte_offset_kernel(pmdp, addr);
 671
 672         /*
 673          * If the page isn't marked valid, the page cannot possibly be
 674          * in the cache.
 675          */
 676         if (!(pte_present(*ptep)))
 677                 return;
 678
 679         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 680                 vaddr = NULL;
 681         else {
 682                 /*
 683                  * Use kmap_coherent or kmap_atomic to do flushes for
 684                  * another ASID than the current one.
 685                  */
 686                 map_coherent = (cpu_has_dc_aliases &&
 687                                 page_mapcount(page) &&
 688                                 !Page_dcache_dirty(page));
 689                 if (map_coherent)
 690                         vaddr = kmap_coherent(page, addr);
 691                 else
 692                         vaddr = kmap_atomic(page);
 693                 addr = (unsigned long)vaddr;
 694         }
 695
 696         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 697                 vaddr ? r4k_blast_dcache_page(addr) :
 698                         r4k_blast_dcache_user_page(addr);
 699                 if (exec && !cpu_icache_snoops_remote_store)
 700                         r4k_blast_scache_page(addr);
 701         }
 702         if (exec) {
 703                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 704                         drop_mmu_context(mm);
 705                 } else
 706                         vaddr ? r4k_blast_icache_page(addr) :
 707                                 r4k_blast_icache_user_page(addr);
 708         }
 709
 710         if (vaddr) {
 711                 if (map_coherent)
 712                         kunmap_coherent();
 713                 else
 714                         kunmap_atomic(vaddr);
 715         }
 716 }
 717
 718 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 719         unsigned long addr, unsigned long pfn)
 720 {
 721         struct flush_cache_page_args args;
 722
 723         args.vma = vma;
 724         args.addr = addr;
 725         args.pfn = pfn;
 726
 727         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
 728 }
 729
 730 static inline void local_r4k_flush_data_cache_page(void * addr)
 731 {
 732         r4k_blast_dcache_page((unsigned long) addr);
 733 }
 734
 735 static void r4k_flush_data_cache_page(unsigned long addr)
 736 {
 737         if (in_atomic())
 738                 local_r4k_flush_data_cache_page((void *)addr);
 739         else
 740                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
 741                                 (void *) addr);
 742 }
 743
 744 struct flush_icache_range_args {
 745         unsigned long start;
 746         unsigned long end;
 747         unsigned int type;
 748         bool user;
 749 };
 750
 751 static inline void __local_r4k_flush_icache_range(unsigned long start,
 752                                                   unsigned long end,
 753                                                   unsigned int type,
 754                                                   bool user)
 755 {
 756         if (!cpu_has_ic_fills_f_dc) {
 757                 if (type == R4K_INDEX ||
 758                     (type & R4K_INDEX && end - start >= dcache_size)) {
 759                         r4k_blast_dcache();
 760                 } else {
 761                         R4600_HIT_CACHEOP_WAR_IMPL;
 762                         if (user)
 763                                 protected_blast_dcache_range(start, end);
 764                         else
 765                                 blast_dcache_range(start, end);
 766                 }
 767         }
 768
 769         if (type == R4K_INDEX ||
 770             (type & R4K_INDEX && end - start > icache_size))
 771                 r4k_blast_icache();
 772         else {
 773                 switch (boot_cpu_type()) {
 774                 case CPU_LOONGSON2EF:
 775                         protected_loongson2_blast_icache_range(start, end);
 776                         break;
 777
 778                 default:
 779                         if (user)
 780                                 protected_blast_icache_range(start, end);
 781                         else
 782                                 blast_icache_range(start, end);
 783                         break;
 784                 }
 785         }
 786 }
 787
 788 static inline void local_r4k_flush_icache_range(unsigned long start,
 789                                                 unsigned long end)
 790 {
 791         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
 792 }
 793
 794 static inline void local_r4k_flush_icache_user_range(unsigned long start,
 795                                                      unsigned long end)
 796 {
 797         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
 798 }
 799
 800 static inline void local_r4k_flush_icache_range_ipi(void *args)
 801 {
 802         struct flush_icache_range_args *fir_args = args;
 803         unsigned long start = fir_args->start;
 804         unsigned long end = fir_args->end;
 805         unsigned int type = fir_args->type;
 806         bool user = fir_args->user;
 807
 808         __local_r4k_flush_icache_range(start, end, type, user);
 809 }
 810
 811 static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
 812                                      bool user)
 813 {
 814         struct flush_icache_range_args args;
 815         unsigned long size, cache_size;
 816
 817         args.start = start;
 818         args.end = end;
 819         args.type = R4K_HIT | R4K_INDEX;
 820         args.user = user;
 821
 822         /*
 823          * Indexed cache ops require an SMP call.
 824          * Consider if that can or should be avoided.
 825          */
 826         preempt_disable();
 827         if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
 828                 /*
 829                  * If address-based cache ops don't require an SMP call, then
 830                  * use them exclusively for small flushes.
 831                  */
 832                 size = end - start;
 833                 cache_size = icache_size;
 834                 if (!cpu_has_ic_fills_f_dc) {
 835                         size *= 2;
 836                         cache_size += dcache_size;
 837                 }
 838                 if (size <= cache_size)
 839                         args.type &= ~R4K_INDEX;
 840         }
 841         r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
 842         preempt_enable();
 843         instruction_hazard();
 844 }
 845
 846 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 847 {
 848         return __r4k_flush_icache_range(start, end, false);
 849 }
 850
 851 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
 852 {
 853         return __r4k_flush_icache_range(start, end, true);
 854 }
 855
 856 #ifdef CONFIG_DMA_NONCOHERENT
 857
 858 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 859 {
 860         /* Catch bad driver code */
 861         if (WARN_ON(size == 0))
 862                 return;
 863
 864         preempt_disable();
 865         if (cpu_has_inclusive_pcaches) {
 866                 if (size >= scache_size) {
 867                         if (current_cpu_type() != CPU_LOONGSON64)
 868                                 r4k_blast_scache();
 869                         else
 870                                 r4k_blast_scache_node(pa_to_nid(addr));
 871                 } else {
 872                         blast_scache_range(addr, addr + size);
 873                 }
 874                 preempt_enable();
 875                 __sync();
 876                 return;
 877         }
 878
 879         /*
 880          * Either no secondary cache or the available caches don't have the
 881          * subset property so we have to flush the primary caches
 882          * explicitly.
 883          * If we would need IPI to perform an INDEX-type operation, then
 884          * we have to use the HIT-type alternative as IPI cannot be used
 885          * here due to interrupts possibly being disabled.
 886          */
 887         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
 888                 r4k_blast_dcache();
 889         } else {
 890                 R4600_HIT_CACHEOP_WAR_IMPL;
 891                 blast_dcache_range(addr, addr + size);
 892         }
 893         preempt_enable();
 894
 895         bc_wback_inv(addr, size);
 896         __sync();
 897 }
 898
 899 static void prefetch_cache_inv(unsigned long addr, unsigned long size)
 900 {
 901         unsigned int linesz = cpu_scache_line_size();
 902         unsigned long addr0 = addr, addr1;
 903
 904         addr0 &= ~(linesz - 1);
 905         addr1 = (addr0 + size - 1) & ~(linesz - 1);
 906
 907         protected_writeback_scache_line(addr0);
 908         if (likely(addr1 != addr0))
 909                 protected_writeback_scache_line(addr1);
 910         else
 911                 return;
 912
 913         addr0 += linesz;
 914         if (likely(addr1 != addr0))
 915                 protected_writeback_scache_line(addr0);
 916         else
 917                 return;
 918
 919         addr1 -= linesz;
 920         if (likely(addr1 > addr0))
 921                 protected_writeback_scache_line(addr0);
 922 }
 923
 924 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 925 {
 926         /* Catch bad driver code */
 927         if (WARN_ON(size == 0))
 928                 return;
 929
 930         preempt_disable();
 931
 932         if (current_cpu_type() == CPU_BMIPS5000)
 933                 prefetch_cache_inv(addr, size);
 934
 935         if (cpu_has_inclusive_pcaches) {
 936                 if (size >= scache_size) {
 937                         if (current_cpu_type() != CPU_LOONGSON64)
 938                                 r4k_blast_scache();
 939                         else
 940                                 r4k_blast_scache_node(pa_to_nid(addr));
 941                 } else {
 942                         /*
 943                          * There is no clearly documented alignment requirement
 944                          * for the cache instruction on MIPS processors and
 945                          * some processors, among them the RM5200 and RM7000
 946                          * QED processors will throw an address error for cache
 947                          * hit ops with insufficient alignment.  Solved by
 948                          * aligning the address to cache line size.
 949                          */
 950                         blast_inv_scache_range(addr, addr + size);
 951                 }
 952                 preempt_enable();
 953                 __sync();
 954                 return;
 955         }
 956
 957         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
 958                 r4k_blast_dcache();
 959         } else {
 960                 R4600_HIT_CACHEOP_WAR_IMPL;
 961                 blast_inv_dcache_range(addr, addr + size);
 962         }
 963         preempt_enable();
 964
 965         bc_inv(addr, size);
 966         __sync();
 967 }
 968 #endif /* CONFIG_DMA_NONCOHERENT */
 969
 970 static void r4k_flush_icache_all(void)
 971 {
 972         if (cpu_has_vtag_icache)
 973                 r4k_blast_icache();
 974 }
 975
 976 struct flush_kernel_vmap_range_args {
 977         unsigned long   vaddr;
 978         int             size;
 979 };
 980
 981 static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
 982 {
 983         /*
 984          * Aliases only affect the primary caches so don't bother with
 985          * S-caches or T-caches.
 986          */
 987         r4k_blast_dcache();
 988 }
 989
 990 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 991 {
 992         struct flush_kernel_vmap_range_args *vmra = args;
 993         unsigned long vaddr = vmra->vaddr;
 994         int size = vmra->size;
 995
 996         /*
 997          * Aliases only affect the primary caches so don't bother with
 998          * S-caches or T-caches.
 999          */
1000         R4600_HIT_CACHEOP_WAR_IMPL;
1001         blast_dcache_range(vaddr, vaddr + size);
1002 }
1003
1004 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1005 {
1006         struct flush_kernel_vmap_range_args args;
1007
1008         args.vaddr = (unsigned long) vaddr;
1009         args.size = size;
1010
1011         if (size >= dcache_size)
1012                 r4k_on_each_cpu(R4K_INDEX,
1013                                 local_r4k_flush_kernel_vmap_range_index, NULL);
1014         else
1015                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1016                                 &args);
1017 }
1018
1019 static inline void rm7k_erratum31(void)
1020 {
1021         const unsigned long ic_lsize = 32;
1022         unsigned long addr;
1023
1024         /* RM7000 erratum #31. The icache is screwed at startup. */
1025         write_c0_taglo(0);
1026         write_c0_taghi(0);
1027
1028         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1029                 __asm__ __volatile__ (
1030                         ".set push\n\t"
1031                         ".set noreorder\n\t"
1032                         ".set mips3\n\t"
1033                         "cache\t%1, 0(%0)\n\t"
1034                         "cache\t%1, 0x1000(%0)\n\t"
1035                         "cache\t%1, 0x2000(%0)\n\t"
1036                         "cache\t%1, 0x3000(%0)\n\t"
1037                         "cache\t%2, 0(%0)\n\t"
1038                         "cache\t%2, 0x1000(%0)\n\t"
1039                         "cache\t%2, 0x2000(%0)\n\t"
1040                         "cache\t%2, 0x3000(%0)\n\t"
1041                         "cache\t%1, 0(%0)\n\t"
1042                         "cache\t%1, 0x1000(%0)\n\t"
1043                         "cache\t%1, 0x2000(%0)\n\t"
1044                         "cache\t%1, 0x3000(%0)\n\t"
1045                         ".set pop\n"
1046                         :
1047                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
1048         }
1049 }
1050
1051 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
1052 {
1053         unsigned int imp = c->processor_id & PRID_IMP_MASK;
1054         unsigned int rev = c->processor_id & PRID_REV_MASK;
1055         int present = 0;
1056
1057         /*
1058          * Early versions of the 74K do not update the cache tags on a
1059          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
1060          * aliases.  In this case it is better to treat the cache as always
1061          * having aliases.  Also disable the synonym tag update feature
1062          * where available.  In this case no opportunistic tag update will
1063          * happen where a load causes a virtual address miss but a physical
1064          * address hit during a D-cache look-up.
1065          */
1066         switch (imp) {
1067         case PRID_IMP_74K:
1068                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1069                         present = 1;
1070                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1071                         write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
1072                 break;
1073         case PRID_IMP_1074K:
1074                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1075                         present = 1;
1076                         write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
1077                 }
1078                 break;
1079         default:
1080                 BUG();
1081         }
1082
1083         return present;
1084 }
1085
1086 static void b5k_instruction_hazard(void)
1087 {
1088         __sync();
1089         __sync();
1090         __asm__ __volatile__(
1091         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1092         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1093         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1094         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1095         : : : "memory");
1096 }
1097
1098 static char *way_string[] = { NULL, "direct mapped", "2-way",
1099         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1100         "9-way", "10-way", "11-way", "12-way",
1101         "13-way", "14-way", "15-way", "16-way",
1102 };
1103
1104 static void probe_pcache(void)
1105 {
1106         struct cpuinfo_mips *c = &current_cpu_data;
1107         unsigned int config = read_c0_config();
1108         unsigned int prid = read_c0_prid();
1109         int has_74k_erratum = 0;
1110         unsigned long config1;
1111         unsigned int lsize;
1112
1113         switch (current_cpu_type()) {
1114         case CPU_R4600:                 /* QED style two way caches? */
1115         case CPU_R4700:
1116         case CPU_R5000:
1117         case CPU_NEVADA:
1118                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1119                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1120                 c->icache.ways = 2;
1121                 c->icache.waybit = __ffs(icache_size/2);
1122
1123                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1124                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1125                 c->dcache.ways = 2;
1126                 c->dcache.waybit= __ffs(dcache_size/2);
1127
1128                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1129                 break;
1130
1131         case CPU_R5500:
1132                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1133                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1134                 c->icache.ways = 2;
1135                 c->icache.waybit= 0;
1136
1137                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1138                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1139                 c->dcache.ways = 2;
1140                 c->dcache.waybit = 0;
1141
1142                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1143                 break;
1144
1145         case CPU_TX49XX:
1146                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1147                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1148                 c->icache.ways = 4;
1149                 c->icache.waybit= 0;
1150
1151                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1152                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1153                 c->dcache.ways = 4;
1154                 c->dcache.waybit = 0;
1155
1156                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1157                 c->options |= MIPS_CPU_PREFETCH;
1158                 break;
1159
1160         case CPU_R4000PC:
1161         case CPU_R4000SC:
1162         case CPU_R4000MC:
1163         case CPU_R4400PC:
1164         case CPU_R4400SC:
1165         case CPU_R4400MC:
1166         case CPU_R4300:
1167                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1168                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1169                 c->icache.ways = 1;
1170                 c->icache.waybit = 0;   /* doesn't matter */
1171
1172                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1173                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1174                 c->dcache.ways = 1;
1175                 c->dcache.waybit = 0;   /* does not matter */
1176
1177                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1178                 break;
1179
1180         case CPU_R10000:
1181         case CPU_R12000:
1182         case CPU_R14000:
1183         case CPU_R16000:
1184                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1185                 c->icache.linesz = 64;
1186                 c->icache.ways = 2;
1187                 c->icache.waybit = 0;
1188
1189                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1190                 c->dcache.linesz = 32;
1191                 c->dcache.ways = 2;
1192                 c->dcache.waybit = 0;
1193
1194                 c->options |= MIPS_CPU_PREFETCH;
1195                 break;
1196
1197         case CPU_RM7000:
1198                 rm7k_erratum31();
1199
1200                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1201                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1202                 c->icache.ways = 4;
1203                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1204
1205                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1206                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1207                 c->dcache.ways = 4;
1208                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1209
1210                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1211                 c->options |= MIPS_CPU_PREFETCH;
1212                 break;
1213
1214         case CPU_LOONGSON2EF:
1215                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1216                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1217                 if (prid & 0x3)
1218                         c->icache.ways = 4;
1219                 else
1220                         c->icache.ways = 2;
1221                 c->icache.waybit = 0;
1222
1223                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1224                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1225                 if (prid & 0x3)
1226                         c->dcache.ways = 4;
1227                 else
1228                         c->dcache.ways = 2;
1229                 c->dcache.waybit = 0;
1230                 break;
1231
1232         case CPU_LOONGSON64:
1233                 config1 = read_c0_config1();
1234                 lsize = (config1 >> 19) & 7;
1235                 if (lsize)
1236                         c->icache.linesz = 2 << lsize;
1237                 else
1238                         c->icache.linesz = 0;
1239                 c->icache.sets = 64 << ((config1 >> 22) & 7);
1240                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1241                 icache_size = c->icache.sets *
1242                                           c->icache.ways *
1243                                           c->icache.linesz;
1244                 c->icache.waybit = 0;
1245
1246                 lsize = (config1 >> 10) & 7;
1247                 if (lsize)
1248                         c->dcache.linesz = 2 << lsize;
1249                 else
1250                         c->dcache.linesz = 0;
1251                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1252                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1253                 dcache_size = c->dcache.sets *
1254                                           c->dcache.ways *
1255                                           c->dcache.linesz;
1256                 c->dcache.waybit = 0;
1257                 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
1258                                 (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
1259                                 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1260                         c->options |= MIPS_CPU_PREFETCH;
1261                 break;
1262
1263         case CPU_CAVIUM_OCTEON3:
1264                 /* For now lie about the number of ways. */
1265                 c->icache.linesz = 128;
1266                 c->icache.sets = 16;
1267                 c->icache.ways = 8;
1268                 c->icache.flags |= MIPS_CACHE_VTAG;
1269                 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1270
1271                 c->dcache.linesz = 128;
1272                 c->dcache.ways = 8;
1273                 c->dcache.sets = 8;
1274                 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1275                 c->options |= MIPS_CPU_PREFETCH;
1276                 break;
1277
1278         default:
1279                 if (!(config & MIPS_CONF_M))
1280                         panic("Don't know how to probe P-caches on this cpu.");
1281
1282                 /*
1283                  * So we seem to be a MIPS32 or MIPS64 CPU
1284                  * So let's probe the I-cache ...
1285                  */
1286                 config1 = read_c0_config1();
1287
1288                 lsize = (config1 >> 19) & 7;
1289
1290                 /* IL == 7 is reserved */
1291                 if (lsize == 7)
1292                         panic("Invalid icache line size");
1293
1294                 c->icache.linesz = lsize ? 2 << lsize : 0;
1295
1296                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1297                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1298
1299                 icache_size = c->icache.sets *
1300                               c->icache.ways *
1301                               c->icache.linesz;
1302                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1303
1304                 if (config & MIPS_CONF_VI)
1305                         c->icache.flags |= MIPS_CACHE_VTAG;
1306
1307                 /*
1308                  * Now probe the MIPS32 / MIPS64 data cache.
1309                  */
1310                 c->dcache.flags = 0;
1311
1312                 lsize = (config1 >> 10) & 7;
1313
1314                 /* DL == 7 is reserved */
1315                 if (lsize == 7)
1316                         panic("Invalid dcache line size");
1317
1318                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1319
1320                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1321                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1322
1323                 dcache_size = c->dcache.sets *
1324                               c->dcache.ways *
1325                               c->dcache.linesz;
1326                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1327
1328                 c->options |= MIPS_CPU_PREFETCH;
1329                 break;
1330         }
1331
1332         /*
1333          * Processor configuration sanity check for the R4000SC erratum
1334          * #5.  With page sizes larger than 32kB there is no possibility
1335          * to get a VCE exception anymore so we don't care about this
1336          * misconfiguration.  The case is rather theoretical anyway;
1337          * presumably no vendor is shipping his hardware in the "bad"
1338          * configuration.
1339          */
1340         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1341             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1342             !(config & CONF_SC) && c->icache.linesz != 16 &&
1343             PAGE_SIZE <= 0x8000)
1344                 panic("Improper R4000SC processor configuration detected");
1345
1346         /* compute a couple of other cache variables */
1347         c->icache.waysize = icache_size / c->icache.ways;
1348         c->dcache.waysize = dcache_size / c->dcache.ways;
1349
1350         c->icache.sets = c->icache.linesz ?
1351                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1352         c->dcache.sets = c->dcache.linesz ?
1353                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1354
1355         /*
1356          * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
1357          * virtually indexed so normally would suffer from aliases.  So
1358          * normally they'd suffer from aliases but magic in the hardware deals
1359          * with that for us so we don't need to take care ourselves.
1360          */
1361         switch (current_cpu_type()) {
1362         case CPU_20KC:
1363         case CPU_25KF:
1364         case CPU_I6400:
1365         case CPU_I6500:
1366         case CPU_SB1:
1367         case CPU_SB1A:
1368                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1369                 break;
1370
1371         case CPU_R10000:
1372         case CPU_R12000:
1373         case CPU_R14000:
1374         case CPU_R16000:
1375                 break;
1376
1377         case CPU_74K:
1378         case CPU_1074K:
1379                 has_74k_erratum = alias_74k_erratum(c);
1380                 fallthrough;
1381         case CPU_M14KC:
1382         case CPU_M14KEC:
1383         case CPU_24K:
1384         case CPU_34K:
1385         case CPU_1004K:
1386         case CPU_INTERAPTIV:
1387         case CPU_P5600:
1388         case CPU_PROAPTIV:
1389         case CPU_M5150:
1390         case CPU_QEMU_GENERIC:
1391         case CPU_P6600:
1392         case CPU_M6250:
1393                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1394                     (c->icache.waysize > PAGE_SIZE))
1395                         c->icache.flags |= MIPS_CACHE_ALIASES;
1396                 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1397                         /*
1398                          * Effectively physically indexed dcache,
1399                          * thus no virtual aliases.
1400                         */
1401                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1402                         break;
1403                 }
1404                 fallthrough;
1405         default:
1406                 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1407                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1408         }
1409
1410         /* Physically indexed caches don't suffer from virtual aliasing */
1411         if (c->dcache.flags & MIPS_CACHE_PINDEX)
1412                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1413
1414         /*
1415          * In systems with CM the icache fills from L2 or closer caches, and
1416          * thus sees remote stores without needing to write them back any
1417          * further than that.
1418          */
1419         if (mips_cm_present())
1420                 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1421
1422         switch (current_cpu_type()) {
1423         case CPU_20KC:
1424                 /*
1425                  * Some older 20Kc chips doesn't have the 'VI' bit in
1426                  * the config register.
1427                  */
1428                 c->icache.flags |= MIPS_CACHE_VTAG;
1429                 break;
1430
1431         case CPU_ALCHEMY:
1432         case CPU_I6400:
1433         case CPU_I6500:
1434                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1435                 break;
1436
1437         case CPU_BMIPS5000:
1438                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1439                 /* Cache aliases are handled in hardware; allow HIGHMEM */
1440                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1441                 break;
1442
1443         case CPU_LOONGSON2EF:
1444                 /*
1445                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1446                  * one op will act on all 4 ways
1447                  */
1448                 c->icache.ways = 1;
1449         }
1450
1451         pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1452                 icache_size >> 10,
1453                 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1454                 way_string[c->icache.ways], c->icache.linesz);
1455
1456         pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1457                 dcache_size >> 10, way_string[c->dcache.ways],
1458                 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1459                 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1460                         "cache aliases" : "no aliases",
1461                 c->dcache.linesz);
1462 }
1463
1464 static void probe_vcache(void)
1465 {
1466         struct cpuinfo_mips *c = &current_cpu_data;
1467         unsigned int config2, lsize;
1468
1469         if (current_cpu_type() != CPU_LOONGSON64)
1470                 return;
1471
1472         config2 = read_c0_config2();
1473         if ((lsize = ((config2 >> 20) & 15)))
1474                 c->vcache.linesz = 2 << lsize;
1475         else
1476                 c->vcache.linesz = lsize;
1477
1478         c->vcache.sets = 64 << ((config2 >> 24) & 15);
1479         c->vcache.ways = 1 + ((config2 >> 16) & 15);
1480
1481         vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1482
1483         c->vcache.waybit = 0;
1484         c->vcache.waysize = vcache_size / c->vcache.ways;
1485
1486         pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1487                 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1488 }
1489
1490 /*
1491  * If you even _breathe_ on this function, look at the gcc output and make sure
1492  * it does not pop things on and off the stack for the cache sizing loop that
1493  * executes in KSEG1 space or else you will crash and burn badly.  You have
1494  * been warned.
1495  */
1496 static int probe_scache(void)
1497 {
1498         unsigned long flags, addr, begin, end, pow2;
1499         unsigned int config = read_c0_config();
1500         struct cpuinfo_mips *c = &current_cpu_data;
1501
1502         if (config & CONF_SC)
1503                 return 0;
1504
1505         begin = (unsigned long) &_stext;
1506         begin &= ~((4 * 1024 * 1024) - 1);
1507         end = begin + (4 * 1024 * 1024);
1508
1509         /*
1510          * This is such a bitch, you'd think they would make it easy to do
1511          * this.  Away you daemons of stupidity!
1512          */
1513         local_irq_save(flags);
1514
1515         /* Fill each size-multiple cache line with a valid tag. */
1516         pow2 = (64 * 1024);
1517         for (addr = begin; addr < end; addr = (begin + pow2)) {
1518                 unsigned long *p = (unsigned long *) addr;
1519                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1520                 pow2 <<= 1;
1521         }
1522
1523         /* Load first line with zero (therefore invalid) tag. */
1524         write_c0_taglo(0);
1525         write_c0_taghi(0);
1526         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1527         cache_op(Index_Store_Tag_I, begin);
1528         cache_op(Index_Store_Tag_D, begin);
1529         cache_op(Index_Store_Tag_SD, begin);
1530
1531         /* Now search for the wrap around point. */
1532         pow2 = (128 * 1024);
1533         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1534                 cache_op(Index_Load_Tag_SD, addr);
1535                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1536                 if (!read_c0_taglo())
1537                         break;
1538                 pow2 <<= 1;
1539         }
1540         local_irq_restore(flags);
1541         addr -= begin;
1542
1543         scache_size = addr;
1544         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1545         c->scache.ways = 1;
1546         c->scache.waybit = 0;           /* does not matter */
1547
1548         return 1;
1549 }
1550
1551 static void loongson2_sc_init(void)
1552 {
1553         struct cpuinfo_mips *c = &current_cpu_data;
1554
1555         scache_size = 512*1024;
1556         c->scache.linesz = 32;
1557         c->scache.ways = 4;
1558         c->scache.waybit = 0;
1559         c->scache.waysize = scache_size / (c->scache.ways);
1560         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1561         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1562                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1563
1564         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1565 }
1566
1567 static void loongson3_sc_init(void)
1568 {
1569         struct cpuinfo_mips *c = &current_cpu_data;
1570         unsigned int config2, lsize;
1571
1572         config2 = read_c0_config2();
1573         lsize = (config2 >> 4) & 15;
1574         if (lsize)
1575                 c->scache.linesz = 2 << lsize;
1576         else
1577                 c->scache.linesz = 0;
1578         c->scache.sets = 64 << ((config2 >> 8) & 15);
1579         c->scache.ways = 1 + (config2 & 15);
1580
1581         /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
1582         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1583                 c->scache.sets *= 2;
1584         else
1585                 c->scache.sets *= 4;
1586
1587         scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
1588
1589         c->scache.waybit = 0;
1590         c->scache.waysize = scache_size / c->scache.ways;
1591         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1592                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1593         if (scache_size)
1594                 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1595         return;
1596 }
1597
1598 extern int r5k_sc_init(void);
1599 extern int rm7k_sc_init(void);
1600 extern int mips_sc_init(void);
1601
1602 static void setup_scache(void)
1603 {
1604         struct cpuinfo_mips *c = &current_cpu_data;
1605         unsigned int config = read_c0_config();
1606         int sc_present = 0;
1607
1608         /*
1609          * Do the probing thing on R4000SC and R4400SC processors.  Other
1610          * processors don't have a S-cache that would be relevant to the
1611          * Linux memory management.
1612          */
1613         switch (current_cpu_type()) {
1614         case CPU_R4000SC:
1615         case CPU_R4000MC:
1616         case CPU_R4400SC:
1617         case CPU_R4400MC:
1618                 sc_present = run_uncached(probe_scache);
1619                 if (sc_present)
1620                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1621                 break;
1622
1623         case CPU_R10000:
1624         case CPU_R12000:
1625         case CPU_R14000:
1626         case CPU_R16000:
1627                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1628                 c->scache.linesz = 64 << ((config >> 13) & 1);
1629                 c->scache.ways = 2;
1630                 c->scache.waybit= 0;
1631                 sc_present = 1;
1632                 break;
1633
1634         case CPU_R5000:
1635         case CPU_NEVADA:
1636 #ifdef CONFIG_R5000_CPU_SCACHE
1637                 r5k_sc_init();
1638 #endif
1639                 return;
1640
1641         case CPU_RM7000:
1642 #ifdef CONFIG_RM7000_CPU_SCACHE
1643                 rm7k_sc_init();
1644 #endif
1645                 return;
1646
1647         case CPU_LOONGSON2EF:
1648                 loongson2_sc_init();
1649                 return;
1650
1651         case CPU_LOONGSON64:
1652                 loongson3_sc_init();
1653                 return;
1654
1655         case CPU_CAVIUM_OCTEON3:
1656                 /* don't need to worry about L2, fully coherent */
1657                 return;
1658
1659         default:
1660                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1661                                     MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1662                                     MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
1663                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1664 #ifdef CONFIG_MIPS_CPU_SCACHE
1665                         if (mips_sc_init ()) {
1666                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1667                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1668                                        scache_size >> 10,
1669                                        way_string[c->scache.ways], c->scache.linesz);
1670
1671                                 if (current_cpu_type() == CPU_BMIPS5000)
1672                                         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1673                         }
1674
1675 #else
1676                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1677                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1678 #endif
1679                         return;
1680                 }
1681                 sc_present = 0;
1682         }
1683
1684         if (!sc_present)
1685                 return;
1686
1687         /* compute a couple of other cache variables */
1688         c->scache.waysize = scache_size / c->scache.ways;
1689
1690         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1691
1692         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1693                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1694
1695         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1696 }
1697
1698 void au1x00_fixup_config_od(void)
1699 {
1700         /*
1701          * c0_config.od (bit 19) was write only (and read as 0)
1702          * on the early revisions of Alchemy SOCs.  It disables the bus
1703          * transaction overlapping and needs to be set to fix various errata.
1704          */
1705         switch (read_c0_prid()) {
1706         case 0x00030100: /* Au1000 DA */
1707         case 0x00030201: /* Au1000 HA */
1708         case 0x00030202: /* Au1000 HB */
1709         case 0x01030200: /* Au1500 AB */
1710         /*
1711          * Au1100 errata actually keeps silence about this bit, so we set it
1712          * just in case for those revisions that require it to be set according
1713          * to the (now gone) cpu table.
1714          */
1715         case 0x02030200: /* Au1100 AB */
1716         case 0x02030201: /* Au1100 BA */
1717         case 0x02030202: /* Au1100 BC */
1718                 set_c0_config(1 << 19);
1719                 break;
1720         }
1721 }
1722
1723 /* CP0 hazard avoidance. */
1724 #define NXP_BARRIER()                                                   \
1725          __asm__ __volatile__(                                          \
1726         ".set noreorder\n\t"                                            \
1727         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1728         ".set reorder\n\t")
1729
1730 static void nxp_pr4450_fixup_config(void)
1731 {
1732         unsigned long config0;
1733
1734         config0 = read_c0_config();
1735
1736         /* clear all three cache coherency fields */
1737         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1738         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1739                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1740                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1741         write_c0_config(config0);
1742         NXP_BARRIER();
1743 }
1744
1745 static int cca = -1;
1746
1747 static int __init cca_setup(char *str)
1748 {
1749         get_option(&str, &cca);
1750
1751         return 0;
1752 }
1753
1754 early_param("cca", cca_setup);
1755
1756 static void coherency_setup(void)
1757 {
1758         if (cca < 0 || cca > 7)
1759                 cca = read_c0_config() & CONF_CM_CMASK;
1760         _page_cachable_default = cca << _CACHE_SHIFT;
1761
1762         pr_debug("Using cache attribute %d\n", cca);
1763         change_c0_config(CONF_CM_CMASK, cca);
1764
1765         /*
1766          * c0_status.cu=0 specifies that updates by the sc instruction use
1767          * the coherency mode specified by the TLB; 1 means cachable
1768          * coherent update on write will be used.  Not all processors have
1769          * this bit and; some wire it to zero, others like Toshiba had the
1770          * silly idea of putting something else there ...
1771          */
1772         switch (current_cpu_type()) {
1773         case CPU_R4000PC:
1774         case CPU_R4000SC:
1775         case CPU_R4000MC:
1776         case CPU_R4400PC:
1777         case CPU_R4400SC:
1778         case CPU_R4400MC:
1779                 clear_c0_config(CONF_CU);
1780                 break;
1781         /*
1782          * We need to catch the early Alchemy SOCs with
1783          * the write-only co_config.od bit and set it back to one on:
1784          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1785          */
1786         case CPU_ALCHEMY:
1787                 au1x00_fixup_config_od();
1788                 break;
1789
1790         case PRID_IMP_PR4450:
1791                 nxp_pr4450_fixup_config();
1792                 break;
1793         }
1794 }
1795
1796 static void r4k_cache_error_setup(void)
1797 {
1798         extern char __weak except_vec2_generic;
1799         extern char __weak except_vec2_sb1;
1800
1801         switch (current_cpu_type()) {
1802         case CPU_SB1:
1803         case CPU_SB1A:
1804                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1805                 break;
1806
1807         default:
1808                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1809                 break;
1810         }
1811 }
1812
1813 void r4k_cache_init(void)
1814 {
1815         extern void build_clear_page(void);
1816         extern void build_copy_page(void);
1817         struct cpuinfo_mips *c = &current_cpu_data;
1818
1819         probe_pcache();
1820         probe_vcache();
1821         setup_scache();
1822
1823         r4k_blast_dcache_page_setup();
1824         r4k_blast_dcache_page_indexed_setup();
1825         r4k_blast_dcache_setup();
1826         r4k_blast_icache_page_setup();
1827         r4k_blast_icache_page_indexed_setup();
1828         r4k_blast_icache_setup();
1829         r4k_blast_scache_page_setup();
1830         r4k_blast_scache_page_indexed_setup();
1831         r4k_blast_scache_setup();
1832         r4k_blast_scache_node_setup();
1833 #ifdef CONFIG_EVA
1834         r4k_blast_dcache_user_page_setup();
1835         r4k_blast_icache_user_page_setup();
1836 #endif
1837
1838         /*
1839          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1840          * This code supports virtually indexed processors and will be
1841          * unnecessarily inefficient on physically indexed processors.
1842          */
1843         if (c->dcache.linesz && cpu_has_dc_aliases)
1844                 shm_align_mask = max_t( unsigned long,
1845                                         c->dcache.sets * c->dcache.linesz - 1,
1846                                         PAGE_SIZE - 1);
1847         else
1848                 shm_align_mask = PAGE_SIZE-1;
1849
1850         __flush_cache_vmap      = r4k__flush_cache_vmap;
1851         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1852
1853         flush_cache_all         = cache_noop;
1854         __flush_cache_all       = r4k___flush_cache_all;
1855         flush_cache_mm          = r4k_flush_cache_mm;
1856         flush_cache_page        = r4k_flush_cache_page;
1857         flush_cache_range       = r4k_flush_cache_range;
1858
1859         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1860
1861         flush_icache_all        = r4k_flush_icache_all;
1862         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1863         flush_data_cache_page   = r4k_flush_data_cache_page;
1864         flush_icache_range      = r4k_flush_icache_range;
1865         local_flush_icache_range        = local_r4k_flush_icache_range;
1866         __flush_icache_user_range       = r4k_flush_icache_user_range;
1867         __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1868
1869 #ifdef CONFIG_DMA_NONCOHERENT
1870         if (dma_default_coherent) {
1871                 _dma_cache_wback_inv    = (void *)cache_noop;
1872                 _dma_cache_wback        = (void *)cache_noop;
1873                 _dma_cache_inv          = (void *)cache_noop;
1874         } else {
1875                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1876                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1877                 _dma_cache_inv          = r4k_dma_cache_inv;
1878         }
1879 #endif /* CONFIG_DMA_NONCOHERENT */
1880
1881         build_clear_page();
1882         build_copy_page();
1883
1884         /*
1885          * We want to run CMP kernels on core with and without coherent
1886          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1887          * or not to flush caches.
1888          */
1889         local_r4k___flush_cache_all(NULL);
1890
1891         coherency_setup();
1892         board_cache_error_setup = r4k_cache_error_setup;
1893
1894         /*
1895          * Per-CPU overrides
1896          */
1897         switch (current_cpu_type()) {
1898         case CPU_BMIPS4350:
1899         case CPU_BMIPS4380:
1900                 /* No IPI is needed because all CPUs share the same D$ */
1901                 flush_data_cache_page = r4k_blast_dcache_page;
1902                 break;
1903         case CPU_BMIPS5000:
1904                 /* We lose our superpowers if L2 is disabled */
1905                 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1906                         break;
1907
1908                 /* I$ fills from D$ just by emptying the write buffers */
1909                 flush_cache_page = (void *)b5k_instruction_hazard;
1910                 flush_cache_range = (void *)b5k_instruction_hazard;
1911                 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1912                 flush_data_cache_page = (void *)b5k_instruction_hazard;
1913                 flush_icache_range = (void *)b5k_instruction_hazard;
1914                 local_flush_icache_range = (void *)b5k_instruction_hazard;
1915
1916
1917                 /* Optimization: an L2 flush implicitly flushes the L1 */
1918                 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1919                 break;
1920         case CPU_LOONGSON64:
1921                 /* Loongson-3 maintains cache coherency by hardware */
1922                 __flush_cache_all       = cache_noop;
1923                 __flush_cache_vmap      = cache_noop;
1924                 __flush_cache_vunmap    = cache_noop;
1925                 __flush_kernel_vmap_range = (void *)cache_noop;
1926                 flush_cache_mm          = (void *)cache_noop;
1927                 flush_cache_page        = (void *)cache_noop;
1928                 flush_cache_range       = (void *)cache_noop;
1929                 flush_icache_all        = (void *)cache_noop;
1930                 flush_data_cache_page   = (void *)cache_noop;
1931                 local_flush_data_cache_page     = (void *)cache_noop;
1932                 break;
1933         }
1934 }
1935
1936 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1937                                void *v)
1938 {
1939         switch (cmd) {
1940         case CPU_PM_ENTER_FAILED:
1941         case CPU_PM_EXIT:
1942                 coherency_setup();
1943                 break;
1944         }
1945
1946         return NOTIFY_OK;
1947 }
1948
1949 static struct notifier_block r4k_cache_pm_notifier_block = {
1950         .notifier_call = r4k_cache_pm_notifier,
1951 };
1952
1953 int __init r4k_cache_init_pm(void)
1954 {
1955         return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1956 }
1957 arch_initcall(r4k_cache_init_pm);