arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/cpu_pm.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/init.h>
  13 #include <linux/highmem.h>
  14 #include <linux/kernel.h>
  15 #include <linux/linkage.h>
  16 #include <linux/preempt.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/mm.h>
  20 #include <linux/export.h>
  21 #include <linux/bitops.h>
  22
  23 #include <asm/bcache.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/cache.h>
  26 #include <asm/cacheops.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpu-features.h>
  29 #include <asm/cpu-type.h>
  30 #include <asm/io.h>
  31 #include <asm/page.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/r4kcache.h>
  34 #include <asm/sections.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/war.h>
  37 #include <asm/cacheflush.h> /* for run_uncached() */
  38 #include <asm/traps.h>
  39 #include <asm/dma-coherence.h>
  40 #include <asm/mips-cps.h>
  41
  42 /*
  43  * Bits describing what cache ops an SMP callback function may perform.
  44  *
  45  * R4K_HIT   -  Virtual user or kernel address based cache operations. The
  46  *              active_mm must be checked before using user addresses, falling
  47  *              back to kmap.
  48  * R4K_INDEX -  Index based cache operations.
  49  */
  50
  51 #define R4K_HIT         BIT(0)
  52 #define R4K_INDEX       BIT(1)
  53
  54 /**
  55  * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
  56  * @type:       Type of cache operations (R4K_HIT or R4K_INDEX).
  57  *
  58  * Decides whether a cache op needs to be performed on every core in the system.
  59  * This may change depending on the @type of cache operation, as well as the set
  60  * of online CPUs, so preemption should be disabled by the caller to prevent CPU
  61  * hotplug from changing the result.
  62  *
  63  * Returns:     1 if the cache operation @type should be done on every core in
  64  *              the system.
  65  *              0 if the cache operation @type is globalized and only needs to
  66  *              be performed on a simple CPU.
  67  */
  68 static inline bool r4k_op_needs_ipi(unsigned int type)
  69 {
  70         /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
  71         if (type == R4K_HIT && mips_cm_present())
  72                 return false;
  73
  74         /*
  75          * Hardware doesn't globalize the required cache ops, so SMP calls may
  76          * be needed, but only if there are foreign CPUs (non-siblings with
  77          * separate caches).
  78          */
  79         /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
  80 #ifdef CONFIG_SMP
  81         return !cpumask_empty(&cpu_foreign_map[0]);
  82 #else
  83         return false;
  84 #endif
  85 }
  86
  87 /*
  88  * Special Variant of smp_call_function for use by cache functions:
  89  *
  90  *  o No return value
  91  *  o collapses to normal function call on UP kernels
  92  *  o collapses to normal function call on systems with a single shared
  93  *    primary cache.
  94  *  o doesn't disable interrupts on the local CPU
  95  */
  96 static inline void r4k_on_each_cpu(unsigned int type,
  97                                    void (*func)(void *info), void *info)
  98 {
  99         preempt_disable();
 100         if (r4k_op_needs_ipi(type))
 101                 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
 102                                        func, info, 1);
 103         func(info);
 104         preempt_enable();
 105 }
 106
 107 /*
 108  * Must die.
 109  */
 110 static unsigned long icache_size __read_mostly;
 111 static unsigned long dcache_size __read_mostly;
 112 static unsigned long vcache_size __read_mostly;
 113 static unsigned long scache_size __read_mostly;
 114
 115 /*
 116  * Dummy cache handling routines for machines without boardcaches
 117  */
 118 static void cache_noop(void) {}
 119
 120 static struct bcache_ops no_sc_ops = {
 121         .bc_enable = (void *)cache_noop,
 122         .bc_disable = (void *)cache_noop,
 123         .bc_wback_inv = (void *)cache_noop,
 124         .bc_inv = (void *)cache_noop
 125 };
 126
 127 struct bcache_ops *bcops = &no_sc_ops;
 128
 129 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
 130 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 131
 132 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
 133 do {                                                                    \
 134         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
 135                 *(volatile unsigned long *)CKSEG1;                      \
 136         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
 137                 __asm__ __volatile__("nop;nop;nop;nop");                \
 138 } while (0)
 139
 140 static void (*r4k_blast_dcache_page)(unsigned long addr);
 141
 142 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 143 {
 144         R4600_HIT_CACHEOP_WAR_IMPL;
 145         blast_dcache32_page(addr);
 146 }
 147
 148 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 149 {
 150         blast_dcache64_page(addr);
 151 }
 152
 153 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
 154 {
 155         blast_dcache128_page(addr);
 156 }
 157
 158 static void r4k_blast_dcache_page_setup(void)
 159 {
 160         unsigned long  dc_lsize = cpu_dcache_line_size();
 161
 162         switch (dc_lsize) {
 163         case 0:
 164                 r4k_blast_dcache_page = (void *)cache_noop;
 165                 break;
 166         case 16:
 167                 r4k_blast_dcache_page = blast_dcache16_page;
 168                 break;
 169         case 32:
 170                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 171                 break;
 172         case 64:
 173                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 174                 break;
 175         case 128:
 176                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
 177                 break;
 178         default:
 179                 break;
 180         }
 181 }
 182
 183 #ifndef CONFIG_EVA
 184 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
 185 #else
 186
 187 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
 188
 189 static void r4k_blast_dcache_user_page_setup(void)
 190 {
 191         unsigned long  dc_lsize = cpu_dcache_line_size();
 192
 193         if (dc_lsize == 0)
 194                 r4k_blast_dcache_user_page = (void *)cache_noop;
 195         else if (dc_lsize == 16)
 196                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
 197         else if (dc_lsize == 32)
 198                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
 199         else if (dc_lsize == 64)
 200                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
 201 }
 202
 203 #endif
 204
 205 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 206
 207 static void r4k_blast_dcache_page_indexed_setup(void)
 208 {
 209         unsigned long dc_lsize = cpu_dcache_line_size();
 210
 211         if (dc_lsize == 0)
 212                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 213         else if (dc_lsize == 16)
 214                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 215         else if (dc_lsize == 32)
 216                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 217         else if (dc_lsize == 64)
 218                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 219         else if (dc_lsize == 128)
 220                 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
 221 }
 222
 223 void (* r4k_blast_dcache)(void);
 224 EXPORT_SYMBOL(r4k_blast_dcache);
 225
 226 static void r4k_blast_dcache_setup(void)
 227 {
 228         unsigned long dc_lsize = cpu_dcache_line_size();
 229
 230         if (dc_lsize == 0)
 231                 r4k_blast_dcache = (void *)cache_noop;
 232         else if (dc_lsize == 16)
 233                 r4k_blast_dcache = blast_dcache16;
 234         else if (dc_lsize == 32)
 235                 r4k_blast_dcache = blast_dcache32;
 236         else if (dc_lsize == 64)
 237                 r4k_blast_dcache = blast_dcache64;
 238         else if (dc_lsize == 128)
 239                 r4k_blast_dcache = blast_dcache128;
 240 }
 241
 242 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 243 #define JUMP_TO_ALIGN(order) \
 244         __asm__ __volatile__( \
 245                 "b\t1f\n\t" \
 246                 ".align\t" #order "\n\t" \
 247                 "1:\n\t" \
 248                 )
 249 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 250 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 251
 252 static inline void blast_r4600_v1_icache32(void)
 253 {
 254         unsigned long flags;
 255
 256         local_irq_save(flags);
 257         blast_icache32();
 258         local_irq_restore(flags);
 259 }
 260
 261 static inline void tx49_blast_icache32(void)
 262 {
 263         unsigned long start = INDEX_BASE;
 264         unsigned long end = start + current_cpu_data.icache.waysize;
 265         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 266         unsigned long ws_end = current_cpu_data.icache.ways <<
 267                                current_cpu_data.icache.waybit;
 268         unsigned long ws, addr;
 269
 270         CACHE32_UNROLL32_ALIGN2;
 271         /* I'm in even chunk.  blast odd chunks */
 272         for (ws = 0; ws < ws_end; ws += ws_inc)
 273                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 274                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 275         CACHE32_UNROLL32_ALIGN;
 276         /* I'm in odd chunk.  blast even chunks */
 277         for (ws = 0; ws < ws_end; ws += ws_inc)
 278                 for (addr = start; addr < end; addr += 0x400 * 2)
 279                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 280 }
 281
 282 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 283 {
 284         unsigned long flags;
 285
 286         local_irq_save(flags);
 287         blast_icache32_page_indexed(page);
 288         local_irq_restore(flags);
 289 }
 290
 291 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 292 {
 293         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 294         unsigned long start = INDEX_BASE + (page & indexmask);
 295         unsigned long end = start + PAGE_SIZE;
 296         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 297         unsigned long ws_end = current_cpu_data.icache.ways <<
 298                                current_cpu_data.icache.waybit;
 299         unsigned long ws, addr;
 300
 301         CACHE32_UNROLL32_ALIGN2;
 302         /* I'm in even chunk.  blast odd chunks */
 303         for (ws = 0; ws < ws_end; ws += ws_inc)
 304                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 305                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 306         CACHE32_UNROLL32_ALIGN;
 307         /* I'm in odd chunk.  blast even chunks */
 308         for (ws = 0; ws < ws_end; ws += ws_inc)
 309                 for (addr = start; addr < end; addr += 0x400 * 2)
 310                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 311 }
 312
 313 static void (* r4k_blast_icache_page)(unsigned long addr);
 314
 315 static void r4k_blast_icache_page_setup(void)
 316 {
 317         unsigned long ic_lsize = cpu_icache_line_size();
 318
 319         if (ic_lsize == 0)
 320                 r4k_blast_icache_page = (void *)cache_noop;
 321         else if (ic_lsize == 16)
 322                 r4k_blast_icache_page = blast_icache16_page;
 323         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
 324                 r4k_blast_icache_page = loongson2_blast_icache32_page;
 325         else if (ic_lsize == 32)
 326                 r4k_blast_icache_page = blast_icache32_page;
 327         else if (ic_lsize == 64)
 328                 r4k_blast_icache_page = blast_icache64_page;
 329         else if (ic_lsize == 128)
 330                 r4k_blast_icache_page = blast_icache128_page;
 331 }
 332
 333 #ifndef CONFIG_EVA
 334 #define r4k_blast_icache_user_page  r4k_blast_icache_page
 335 #else
 336
 337 static void (*r4k_blast_icache_user_page)(unsigned long addr);
 338
 339 static void r4k_blast_icache_user_page_setup(void)
 340 {
 341         unsigned long ic_lsize = cpu_icache_line_size();
 342
 343         if (ic_lsize == 0)
 344                 r4k_blast_icache_user_page = (void *)cache_noop;
 345         else if (ic_lsize == 16)
 346                 r4k_blast_icache_user_page = blast_icache16_user_page;
 347         else if (ic_lsize == 32)
 348                 r4k_blast_icache_user_page = blast_icache32_user_page;
 349         else if (ic_lsize == 64)
 350                 r4k_blast_icache_user_page = blast_icache64_user_page;
 351 }
 352
 353 #endif
 354
 355 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 356
 357 static void r4k_blast_icache_page_indexed_setup(void)
 358 {
 359         unsigned long ic_lsize = cpu_icache_line_size();
 360
 361         if (ic_lsize == 0)
 362                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 363         else if (ic_lsize == 16)
 364                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 365         else if (ic_lsize == 32) {
 366                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 367                         r4k_blast_icache_page_indexed =
 368                                 blast_icache32_r4600_v1_page_indexed;
 369                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 370                         r4k_blast_icache_page_indexed =
 371                                 tx49_blast_icache32_page_indexed;
 372                 else if (current_cpu_type() == CPU_LOONGSON2)
 373                         r4k_blast_icache_page_indexed =
 374                                 loongson2_blast_icache32_page_indexed;
 375                 else
 376                         r4k_blast_icache_page_indexed =
 377                                 blast_icache32_page_indexed;
 378         } else if (ic_lsize == 64)
 379                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 380 }
 381
 382 void (* r4k_blast_icache)(void);
 383 EXPORT_SYMBOL(r4k_blast_icache);
 384
 385 static void r4k_blast_icache_setup(void)
 386 {
 387         unsigned long ic_lsize = cpu_icache_line_size();
 388
 389         if (ic_lsize == 0)
 390                 r4k_blast_icache = (void *)cache_noop;
 391         else if (ic_lsize == 16)
 392                 r4k_blast_icache = blast_icache16;
 393         else if (ic_lsize == 32) {
 394                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 395                         r4k_blast_icache = blast_r4600_v1_icache32;
 396                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 397                         r4k_blast_icache = tx49_blast_icache32;
 398                 else if (current_cpu_type() == CPU_LOONGSON2)
 399                         r4k_blast_icache = loongson2_blast_icache32;
 400                 else
 401                         r4k_blast_icache = blast_icache32;
 402         } else if (ic_lsize == 64)
 403                 r4k_blast_icache = blast_icache64;
 404         else if (ic_lsize == 128)
 405                 r4k_blast_icache = blast_icache128;
 406 }
 407
 408 static void (* r4k_blast_scache_page)(unsigned long addr);
 409
 410 static void r4k_blast_scache_page_setup(void)
 411 {
 412         unsigned long sc_lsize = cpu_scache_line_size();
 413
 414         if (scache_size == 0)
 415                 r4k_blast_scache_page = (void *)cache_noop;
 416         else if (sc_lsize == 16)
 417                 r4k_blast_scache_page = blast_scache16_page;
 418         else if (sc_lsize == 32)
 419                 r4k_blast_scache_page = blast_scache32_page;
 420         else if (sc_lsize == 64)
 421                 r4k_blast_scache_page = blast_scache64_page;
 422         else if (sc_lsize == 128)
 423                 r4k_blast_scache_page = blast_scache128_page;
 424 }
 425
 426 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 427
 428 static void r4k_blast_scache_page_indexed_setup(void)
 429 {
 430         unsigned long sc_lsize = cpu_scache_line_size();
 431
 432         if (scache_size == 0)
 433                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 434         else if (sc_lsize == 16)
 435                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 436         else if (sc_lsize == 32)
 437                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 438         else if (sc_lsize == 64)
 439                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 440         else if (sc_lsize == 128)
 441                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 442 }
 443
 444 static void (* r4k_blast_scache)(void);
 445
 446 static void r4k_blast_scache_setup(void)
 447 {
 448         unsigned long sc_lsize = cpu_scache_line_size();
 449
 450         if (scache_size == 0)
 451                 r4k_blast_scache = (void *)cache_noop;
 452         else if (sc_lsize == 16)
 453                 r4k_blast_scache = blast_scache16;
 454         else if (sc_lsize == 32)
 455                 r4k_blast_scache = blast_scache32;
 456         else if (sc_lsize == 64)
 457                 r4k_blast_scache = blast_scache64;
 458         else if (sc_lsize == 128)
 459                 r4k_blast_scache = blast_scache128;
 460 }
 461
 462 static void (*r4k_blast_scache_node)(long node);
 463
 464 static void r4k_blast_scache_node_setup(void)
 465 {
 466         unsigned long sc_lsize = cpu_scache_line_size();
 467
 468         if (current_cpu_type() != CPU_LOONGSON3)
 469                 r4k_blast_scache_node = (void *)cache_noop;
 470         else if (sc_lsize == 16)
 471                 r4k_blast_scache_node = blast_scache16_node;
 472         else if (sc_lsize == 32)
 473                 r4k_blast_scache_node = blast_scache32_node;
 474         else if (sc_lsize == 64)
 475                 r4k_blast_scache_node = blast_scache64_node;
 476         else if (sc_lsize == 128)
 477                 r4k_blast_scache_node = blast_scache128_node;
 478 }
 479
 480 static inline void local_r4k___flush_cache_all(void * args)
 481 {
 482         switch (current_cpu_type()) {
 483         case CPU_LOONGSON2:
 484         case CPU_R4000SC:
 485         case CPU_R4000MC:
 486         case CPU_R4400SC:
 487         case CPU_R4400MC:
 488         case CPU_R10000:
 489         case CPU_R12000:
 490         case CPU_R14000:
 491         case CPU_R16000:
 492                 /*
 493                  * These caches are inclusive caches, that is, if something
 494                  * is not cached in the S-cache, we know it also won't be
 495                  * in one of the primary caches.
 496                  */
 497                 r4k_blast_scache();
 498                 break;
 499
 500         case CPU_LOONGSON3:
 501                 /* Use get_ebase_cpunum() for both NUMA=y/n */
 502                 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
 503                 break;
 504
 505         case CPU_BMIPS5000:
 506                 r4k_blast_scache();
 507                 __sync();
 508                 break;
 509
 510         default:
 511                 r4k_blast_dcache();
 512                 r4k_blast_icache();
 513                 break;
 514         }
 515 }
 516
 517 static void r4k___flush_cache_all(void)
 518 {
 519         r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
 520 }
 521
 522 /**
 523  * has_valid_asid() - Determine if an mm already has an ASID.
 524  * @mm:         Memory map.
 525  * @type:       R4K_HIT or R4K_INDEX, type of cache op.
 526  *
 527  * Determines whether @mm already has an ASID on any of the CPUs which cache ops
 528  * of type @type within an r4k_on_each_cpu() call will affect. If
 529  * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
 530  * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
 531  * will need to be checked.
 532  *
 533  * Must be called in non-preemptive context.
 534  *
 535  * Returns:     1 if the CPUs affected by @type cache ops have an ASID for @mm.
 536  *              0 otherwise.
 537  */
 538 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
 539 {
 540         unsigned int i;
 541         const cpumask_t *mask = cpu_present_mask;
 542
 543         /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
 544 #ifdef CONFIG_SMP
 545         /*
 546          * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
 547          * each foreign core, so we only need to worry about siblings.
 548          * Otherwise we need to worry about all present CPUs.
 549          */
 550         if (r4k_op_needs_ipi(type))
 551                 mask = &cpu_sibling_map[smp_processor_id()];
 552 #endif
 553         for_each_cpu(i, mask)
 554                 if (cpu_context(i, mm))
 555                         return 1;
 556         return 0;
 557 }
 558
 559 static void r4k__flush_cache_vmap(void)
 560 {
 561         r4k_blast_dcache();
 562 }
 563
 564 static void r4k__flush_cache_vunmap(void)
 565 {
 566         r4k_blast_dcache();
 567 }
 568
 569 /*
 570  * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
 571  * whole caches when vma is executable.
 572  */
 573 static inline void local_r4k_flush_cache_range(void * args)
 574 {
 575         struct vm_area_struct *vma = args;
 576         int exec = vma->vm_flags & VM_EXEC;
 577
 578         if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
 579                 return;
 580
 581         /*
 582          * If dcache can alias, we must blast it since mapping is changing.
 583          * If executable, we must ensure any dirty lines are written back far
 584          * enough to be visible to icache.
 585          */
 586         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 587                 r4k_blast_dcache();
 588         /* If executable, blast stale lines from icache */
 589         if (exec)
 590                 r4k_blast_icache();
 591 }
 592
 593 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 594         unsigned long start, unsigned long end)
 595 {
 596         int exec = vma->vm_flags & VM_EXEC;
 597
 598         if (cpu_has_dc_aliases || exec)
 599                 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
 600 }
 601
 602 static inline void local_r4k_flush_cache_mm(void * args)
 603 {
 604         struct mm_struct *mm = args;
 605
 606         if (!has_valid_asid(mm, R4K_INDEX))
 607                 return;
 608
 609         /*
 610          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 611          * only flush the primary caches but R1x000 behave sane ...
 612          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 613          * caches, so we can bail out early.
 614          */
 615         if (current_cpu_type() == CPU_R4000SC ||
 616             current_cpu_type() == CPU_R4000MC ||
 617             current_cpu_type() == CPU_R4400SC ||
 618             current_cpu_type() == CPU_R4400MC) {
 619                 r4k_blast_scache();
 620                 return;
 621         }
 622
 623         r4k_blast_dcache();
 624 }
 625
 626 static void r4k_flush_cache_mm(struct mm_struct *mm)
 627 {
 628         if (!cpu_has_dc_aliases)
 629                 return;
 630
 631         r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
 632 }
 633
 634 struct flush_cache_page_args {
 635         struct vm_area_struct *vma;
 636         unsigned long addr;
 637         unsigned long pfn;
 638 };
 639
 640 static inline void local_r4k_flush_cache_page(void *args)
 641 {
 642         struct flush_cache_page_args *fcp_args = args;
 643         struct vm_area_struct *vma = fcp_args->vma;
 644         unsigned long addr = fcp_args->addr;
 645         struct page *page = pfn_to_page(fcp_args->pfn);
 646         int exec = vma->vm_flags & VM_EXEC;
 647         struct mm_struct *mm = vma->vm_mm;
 648         int map_coherent = 0;
 649         pgd_t *pgdp;
 650         pud_t *pudp;
 651         pmd_t *pmdp;
 652         pte_t *ptep;
 653         void *vaddr;
 654
 655         /*
 656          * If owns no valid ASID yet, cannot possibly have gotten
 657          * this page into the cache.
 658          */
 659         if (!has_valid_asid(mm, R4K_HIT))
 660                 return;
 661
 662         addr &= PAGE_MASK;
 663         pgdp = pgd_offset(mm, addr);
 664         pudp = pud_offset(pgdp, addr);
 665         pmdp = pmd_offset(pudp, addr);
 666         ptep = pte_offset(pmdp, addr);
 667
 668         /*
 669          * If the page isn't marked valid, the page cannot possibly be
 670          * in the cache.
 671          */
 672         if (!(pte_present(*ptep)))
 673                 return;
 674
 675         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 676                 vaddr = NULL;
 677         else {
 678                 /*
 679                  * Use kmap_coherent or kmap_atomic to do flushes for
 680                  * another ASID than the current one.
 681                  */
 682                 map_coherent = (cpu_has_dc_aliases &&
 683                                 page_mapcount(page) &&
 684                                 !Page_dcache_dirty(page));
 685                 if (map_coherent)
 686                         vaddr = kmap_coherent(page, addr);
 687                 else
 688                         vaddr = kmap_atomic(page);
 689                 addr = (unsigned long)vaddr;
 690         }
 691
 692         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 693                 vaddr ? r4k_blast_dcache_page(addr) :
 694                         r4k_blast_dcache_user_page(addr);
 695                 if (exec && !cpu_icache_snoops_remote_store)
 696                         r4k_blast_scache_page(addr);
 697         }
 698         if (exec) {
 699                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 700                         int cpu = smp_processor_id();
 701
 702                         if (cpu_context(cpu, mm) != 0)
 703                                 drop_mmu_context(mm, cpu);
 704                 } else
 705                         vaddr ? r4k_blast_icache_page(addr) :
 706                                 r4k_blast_icache_user_page(addr);
 707         }
 708
 709         if (vaddr) {
 710                 if (map_coherent)
 711                         kunmap_coherent();
 712                 else
 713                         kunmap_atomic(vaddr);
 714         }
 715 }
 716
 717 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 718         unsigned long addr, unsigned long pfn)
 719 {
 720         struct flush_cache_page_args args;
 721
 722         args.vma = vma;
 723         args.addr = addr;
 724         args.pfn = pfn;
 725
 726         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
 727 }
 728
 729 static inline void local_r4k_flush_data_cache_page(void * addr)
 730 {
 731         r4k_blast_dcache_page((unsigned long) addr);
 732 }
 733
 734 static void r4k_flush_data_cache_page(unsigned long addr)
 735 {
 736         if (in_atomic())
 737                 local_r4k_flush_data_cache_page((void *)addr);
 738         else
 739                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
 740                                 (void *) addr);
 741 }
 742
 743 struct flush_icache_range_args {
 744         unsigned long start;
 745         unsigned long end;
 746         unsigned int type;
 747         bool user;
 748 };
 749
 750 static inline void __local_r4k_flush_icache_range(unsigned long start,
 751                                                   unsigned long end,
 752                                                   unsigned int type,
 753                                                   bool user)
 754 {
 755         if (!cpu_has_ic_fills_f_dc) {
 756                 if (type == R4K_INDEX ||
 757                     (type & R4K_INDEX && end - start >= dcache_size)) {
 758                         r4k_blast_dcache();
 759                 } else {
 760                         R4600_HIT_CACHEOP_WAR_IMPL;
 761                         if (user)
 762                                 protected_blast_dcache_range(start, end);
 763                         else
 764                                 blast_dcache_range(start, end);
 765                 }
 766         }
 767
 768         if (type == R4K_INDEX ||
 769             (type & R4K_INDEX && end - start > icache_size))
 770                 r4k_blast_icache();
 771         else {
 772                 switch (boot_cpu_type()) {
 773                 case CPU_LOONGSON2:
 774                         protected_loongson2_blast_icache_range(start, end);
 775                         break;
 776
 777                 default:
 778                         if (user)
 779                                 protected_blast_icache_range(start, end);
 780                         else
 781                                 blast_icache_range(start, end);
 782                         break;
 783                 }
 784         }
 785 }
 786
 787 static inline void local_r4k_flush_icache_range(unsigned long start,
 788                                                 unsigned long end)
 789 {
 790         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
 791 }
 792
 793 static inline void local_r4k_flush_icache_user_range(unsigned long start,
 794                                                      unsigned long end)
 795 {
 796         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
 797 }
 798
 799 static inline void local_r4k_flush_icache_range_ipi(void *args)
 800 {
 801         struct flush_icache_range_args *fir_args = args;
 802         unsigned long start = fir_args->start;
 803         unsigned long end = fir_args->end;
 804         unsigned int type = fir_args->type;
 805         bool user = fir_args->user;
 806
 807         __local_r4k_flush_icache_range(start, end, type, user);
 808 }
 809
 810 static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
 811                                      bool user)
 812 {
 813         struct flush_icache_range_args args;
 814         unsigned long size, cache_size;
 815
 816         args.start = start;
 817         args.end = end;
 818         args.type = R4K_HIT | R4K_INDEX;
 819         args.user = user;
 820
 821         /*
 822          * Indexed cache ops require an SMP call.
 823          * Consider if that can or should be avoided.
 824          */
 825         preempt_disable();
 826         if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
 827                 /*
 828                  * If address-based cache ops don't require an SMP call, then
 829                  * use them exclusively for small flushes.
 830                  */
 831                 size = end - start;
 832                 cache_size = icache_size;
 833                 if (!cpu_has_ic_fills_f_dc) {
 834                         size *= 2;
 835                         cache_size += dcache_size;
 836                 }
 837                 if (size <= cache_size)
 838                         args.type &= ~R4K_INDEX;
 839         }
 840         r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
 841         preempt_enable();
 842         instruction_hazard();
 843 }
 844
 845 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 846 {
 847         return __r4k_flush_icache_range(start, end, false);
 848 }
 849
 850 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
 851 {
 852         return __r4k_flush_icache_range(start, end, true);
 853 }
 854
 855 #ifdef CONFIG_DMA_NONCOHERENT
 856
 857 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 858 {
 859         /* Catch bad driver code */
 860         if (WARN_ON(size == 0))
 861                 return;
 862
 863         preempt_disable();
 864         if (cpu_has_inclusive_pcaches) {
 865                 if (size >= scache_size) {
 866                         if (current_cpu_type() != CPU_LOONGSON3)
 867                                 r4k_blast_scache();
 868                         else
 869                                 r4k_blast_scache_node(pa_to_nid(addr));
 870                 } else {
 871                         blast_scache_range(addr, addr + size);
 872                 }
 873                 preempt_enable();
 874                 __sync();
 875                 return;
 876         }
 877
 878         /*
 879          * Either no secondary cache or the available caches don't have the
 880          * subset property so we have to flush the primary caches
 881          * explicitly.
 882          * If we would need IPI to perform an INDEX-type operation, then
 883          * we have to use the HIT-type alternative as IPI cannot be used
 884          * here due to interrupts possibly being disabled.
 885          */
 886         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
 887                 r4k_blast_dcache();
 888         } else {
 889                 R4600_HIT_CACHEOP_WAR_IMPL;
 890                 blast_dcache_range(addr, addr + size);
 891         }
 892         preempt_enable();
 893
 894         bc_wback_inv(addr, size);
 895         __sync();
 896 }
 897
 898 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 899 {
 900         /* Catch bad driver code */
 901         if (WARN_ON(size == 0))
 902                 return;
 903
 904         preempt_disable();
 905         if (cpu_has_inclusive_pcaches) {
 906                 if (size >= scache_size) {
 907                         if (current_cpu_type() != CPU_LOONGSON3)
 908                                 r4k_blast_scache();
 909                         else
 910                                 r4k_blast_scache_node(pa_to_nid(addr));
 911                 } else {
 912                         /*
 913                          * There is no clearly documented alignment requirement
 914                          * for the cache instruction on MIPS processors and
 915                          * some processors, among them the RM5200 and RM7000
 916                          * QED processors will throw an address error for cache
 917                          * hit ops with insufficient alignment.  Solved by
 918                          * aligning the address to cache line size.
 919                          */
 920                         blast_inv_scache_range(addr, addr + size);
 921                 }
 922                 preempt_enable();
 923                 __sync();
 924                 return;
 925         }
 926
 927         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
 928                 r4k_blast_dcache();
 929         } else {
 930                 R4600_HIT_CACHEOP_WAR_IMPL;
 931                 blast_inv_dcache_range(addr, addr + size);
 932         }
 933         preempt_enable();
 934
 935         bc_inv(addr, size);
 936         __sync();
 937 }
 938 #endif /* CONFIG_DMA_NONCOHERENT */
 939
 940 struct flush_cache_sigtramp_args {
 941         struct mm_struct *mm;
 942         struct page *page;
 943         unsigned long addr;
 944 };
 945
 946 /*
 947  * While we're protected against bad userland addresses we don't care
 948  * very much about what happens in that case.  Usually a segmentation
 949  * fault will dump the process later on anyway ...
 950  */
 951 static void local_r4k_flush_cache_sigtramp(void *args)
 952 {
 953         struct flush_cache_sigtramp_args *fcs_args = args;
 954         unsigned long addr = fcs_args->addr;
 955         struct page *page = fcs_args->page;
 956         struct mm_struct *mm = fcs_args->mm;
 957         int map_coherent = 0;
 958         void *vaddr;
 959
 960         unsigned long ic_lsize = cpu_icache_line_size();
 961         unsigned long dc_lsize = cpu_dcache_line_size();
 962         unsigned long sc_lsize = cpu_scache_line_size();
 963
 964         /*
 965          * If owns no valid ASID yet, cannot possibly have gotten
 966          * this page into the cache.
 967          */
 968         if (!has_valid_asid(mm, R4K_HIT))
 969                 return;
 970
 971         if (mm == current->active_mm) {
 972                 vaddr = NULL;
 973         } else {
 974                 /*
 975                  * Use kmap_coherent or kmap_atomic to do flushes for
 976                  * another ASID than the current one.
 977                  */
 978                 map_coherent = (cpu_has_dc_aliases &&
 979                                 page_mapcount(page) &&
 980                                 !Page_dcache_dirty(page));
 981                 if (map_coherent)
 982                         vaddr = kmap_coherent(page, addr);
 983                 else
 984                         vaddr = kmap_atomic(page);
 985                 addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
 986         }
 987
 988         R4600_HIT_CACHEOP_WAR_IMPL;
 989         if (!cpu_has_ic_fills_f_dc) {
 990                 if (dc_lsize)
 991                         vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
 992                               : protected_writeback_dcache_line(
 993                                                         addr & ~(dc_lsize - 1));
 994                 if (!cpu_icache_snoops_remote_store && scache_size)
 995                         vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
 996                               : protected_writeback_scache_line(
 997                                                         addr & ~(sc_lsize - 1));
 998         }
 999         if (ic_lsize)
1000                 vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
1001                       : protected_flush_icache_line(addr & ~(ic_lsize - 1));
1002
1003         if (vaddr) {
1004                 if (map_coherent)
1005                         kunmap_coherent();
1006                 else
1007                         kunmap_atomic(vaddr);
1008         }
1009
1010         if (MIPS4K_ICACHE_REFILL_WAR) {
1011                 __asm__ __volatile__ (
1012                         ".set push\n\t"
1013                         ".set noat\n\t"
1014                         ".set "MIPS_ISA_LEVEL"\n\t"
1015 #ifdef CONFIG_32BIT
1016                         "la     $at,1f\n\t"
1017 #endif
1018 #ifdef CONFIG_64BIT
1019                         "dla    $at,1f\n\t"
1020 #endif
1021                         "cache  %0,($at)\n\t"
1022                         "nop; nop; nop\n"
1023                         "1:\n\t"
1024                         ".set pop"
1025                         :
1026                         : "i" (Hit_Invalidate_I));
1027         }
1028         if (MIPS_CACHE_SYNC_WAR)
1029                 __asm__ __volatile__ ("sync");
1030 }
1031
1032 static void r4k_flush_cache_sigtramp(unsigned long addr)
1033 {
1034         struct flush_cache_sigtramp_args args;
1035         int npages;
1036
1037         down_read(&current->mm->mmap_sem);
1038
1039         npages = get_user_pages_fast(addr, 1, 0, &args.page);
1040         if (npages < 1)
1041                 goto out;
1042
1043         args.mm = current->mm;
1044         args.addr = addr;
1045
1046         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
1047
1048         put_page(args.page);
1049 out:
1050         up_read(&current->mm->mmap_sem);
1051 }
1052
1053 static void r4k_flush_icache_all(void)
1054 {
1055         if (cpu_has_vtag_icache)
1056                 r4k_blast_icache();
1057 }
1058
1059 struct flush_kernel_vmap_range_args {
1060         unsigned long   vaddr;
1061         int             size;
1062 };
1063
1064 static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
1065 {
1066         /*
1067          * Aliases only affect the primary caches so don't bother with
1068          * S-caches or T-caches.
1069          */
1070         r4k_blast_dcache();
1071 }
1072
1073 static inline void local_r4k_flush_kernel_vmap_range(void *args)
1074 {
1075         struct flush_kernel_vmap_range_args *vmra = args;
1076         unsigned long vaddr = vmra->vaddr;
1077         int size = vmra->size;
1078
1079         /*
1080          * Aliases only affect the primary caches so don't bother with
1081          * S-caches or T-caches.
1082          */
1083         R4600_HIT_CACHEOP_WAR_IMPL;
1084         blast_dcache_range(vaddr, vaddr + size);
1085 }
1086
1087 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1088 {
1089         struct flush_kernel_vmap_range_args args;
1090
1091         args.vaddr = (unsigned long) vaddr;
1092         args.size = size;
1093
1094         if (size >= dcache_size)
1095                 r4k_on_each_cpu(R4K_INDEX,
1096                                 local_r4k_flush_kernel_vmap_range_index, NULL);
1097         else
1098                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1099                                 &args);
1100 }
1101
1102 static inline void rm7k_erratum31(void)
1103 {
1104         const unsigned long ic_lsize = 32;
1105         unsigned long addr;
1106
1107         /* RM7000 erratum #31. The icache is screwed at startup. */
1108         write_c0_taglo(0);
1109         write_c0_taghi(0);
1110
1111         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1112                 __asm__ __volatile__ (
1113                         ".set push\n\t"
1114                         ".set noreorder\n\t"
1115                         ".set mips3\n\t"
1116                         "cache\t%1, 0(%0)\n\t"
1117                         "cache\t%1, 0x1000(%0)\n\t"
1118                         "cache\t%1, 0x2000(%0)\n\t"
1119                         "cache\t%1, 0x3000(%0)\n\t"
1120                         "cache\t%2, 0(%0)\n\t"
1121                         "cache\t%2, 0x1000(%0)\n\t"
1122                         "cache\t%2, 0x2000(%0)\n\t"
1123                         "cache\t%2, 0x3000(%0)\n\t"
1124                         "cache\t%1, 0(%0)\n\t"
1125                         "cache\t%1, 0x1000(%0)\n\t"
1126                         "cache\t%1, 0x2000(%0)\n\t"
1127                         "cache\t%1, 0x3000(%0)\n\t"
1128                         ".set pop\n"
1129                         :
1130                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
1131         }
1132 }
1133
1134 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
1135 {
1136         unsigned int imp = c->processor_id & PRID_IMP_MASK;
1137         unsigned int rev = c->processor_id & PRID_REV_MASK;
1138         int present = 0;
1139
1140         /*
1141          * Early versions of the 74K do not update the cache tags on a
1142          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
1143          * aliases.  In this case it is better to treat the cache as always
1144          * having aliases.  Also disable the synonym tag update feature
1145          * where available.  In this case no opportunistic tag update will
1146          * happen where a load causes a virtual address miss but a physical
1147          * address hit during a D-cache look-up.
1148          */
1149         switch (imp) {
1150         case PRID_IMP_74K:
1151                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1152                         present = 1;
1153                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1154                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1155                 break;
1156         case PRID_IMP_1074K:
1157                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1158                         present = 1;
1159                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1160                 }
1161                 break;
1162         default:
1163                 BUG();
1164         }
1165
1166         return present;
1167 }
1168
1169 static void b5k_instruction_hazard(void)
1170 {
1171         __sync();
1172         __sync();
1173         __asm__ __volatile__(
1174         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1175         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1176         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1177         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1178         : : : "memory");
1179 }
1180
1181 static char *way_string[] = { NULL, "direct mapped", "2-way",
1182         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1183         "9-way", "10-way", "11-way", "12-way",
1184         "13-way", "14-way", "15-way", "16-way",
1185 };
1186
1187 static void probe_pcache(void)
1188 {
1189         struct cpuinfo_mips *c = &current_cpu_data;
1190         unsigned int config = read_c0_config();
1191         unsigned int prid = read_c0_prid();
1192         int has_74k_erratum = 0;
1193         unsigned long config1;
1194         unsigned int lsize;
1195
1196         switch (current_cpu_type()) {
1197         case CPU_R4600:                 /* QED style two way caches? */
1198         case CPU_R4700:
1199         case CPU_R5000:
1200         case CPU_NEVADA:
1201                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1202                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1203                 c->icache.ways = 2;
1204                 c->icache.waybit = __ffs(icache_size/2);
1205
1206                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1207                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1208                 c->dcache.ways = 2;
1209                 c->dcache.waybit= __ffs(dcache_size/2);
1210
1211                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1212                 break;
1213
1214         case CPU_R5432:
1215         case CPU_R5500:
1216                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1217                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1218                 c->icache.ways = 2;
1219                 c->icache.waybit= 0;
1220
1221                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1222                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1223                 c->dcache.ways = 2;
1224                 c->dcache.waybit = 0;
1225
1226                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1227                 break;
1228
1229         case CPU_TX49XX:
1230                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1231                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1232                 c->icache.ways = 4;
1233                 c->icache.waybit= 0;
1234
1235                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1236                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1237                 c->dcache.ways = 4;
1238                 c->dcache.waybit = 0;
1239
1240                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1241                 c->options |= MIPS_CPU_PREFETCH;
1242                 break;
1243
1244         case CPU_R4000PC:
1245         case CPU_R4000SC:
1246         case CPU_R4000MC:
1247         case CPU_R4400PC:
1248         case CPU_R4400SC:
1249         case CPU_R4400MC:
1250         case CPU_R4300:
1251                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1252                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1253                 c->icache.ways = 1;
1254                 c->icache.waybit = 0;   /* doesn't matter */
1255
1256                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1257                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1258                 c->dcache.ways = 1;
1259                 c->dcache.waybit = 0;   /* does not matter */
1260
1261                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1262                 break;
1263
1264         case CPU_R10000:
1265         case CPU_R12000:
1266         case CPU_R14000:
1267         case CPU_R16000:
1268                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1269                 c->icache.linesz = 64;
1270                 c->icache.ways = 2;
1271                 c->icache.waybit = 0;
1272
1273                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1274                 c->dcache.linesz = 32;
1275                 c->dcache.ways = 2;
1276                 c->dcache.waybit = 0;
1277
1278                 c->options |= MIPS_CPU_PREFETCH;
1279                 break;
1280
1281         case CPU_VR4133:
1282                 write_c0_config(config & ~VR41_CONF_P4K);
1283         case CPU_VR4131:
1284                 /* Workaround for cache instruction bug of VR4131 */
1285                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1286                     c->processor_id == 0x0c82U) {
1287                         config |= 0x00400000U;
1288                         if (c->processor_id == 0x0c80U)
1289                                 config |= VR41_CONF_BP;
1290                         write_c0_config(config);
1291                 } else
1292                         c->options |= MIPS_CPU_CACHE_CDEX_P;
1293
1294                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1295                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1296                 c->icache.ways = 2;
1297                 c->icache.waybit = __ffs(icache_size/2);
1298
1299                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1300                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1301                 c->dcache.ways = 2;
1302                 c->dcache.waybit = __ffs(dcache_size/2);
1303                 break;
1304
1305         case CPU_VR41XX:
1306         case CPU_VR4111:
1307         case CPU_VR4121:
1308         case CPU_VR4122:
1309         case CPU_VR4181:
1310         case CPU_VR4181A:
1311                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1312                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1313                 c->icache.ways = 1;
1314                 c->icache.waybit = 0;   /* doesn't matter */
1315
1316                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1317                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1318                 c->dcache.ways = 1;
1319                 c->dcache.waybit = 0;   /* does not matter */
1320
1321                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1322                 break;
1323
1324         case CPU_RM7000:
1325                 rm7k_erratum31();
1326
1327                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1328                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1329                 c->icache.ways = 4;
1330                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1331
1332                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1333                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1334                 c->dcache.ways = 4;
1335                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1336
1337                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1338                 c->options |= MIPS_CPU_PREFETCH;
1339                 break;
1340
1341         case CPU_LOONGSON2:
1342                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1343                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1344                 if (prid & 0x3)
1345                         c->icache.ways = 4;
1346                 else
1347                         c->icache.ways = 2;
1348                 c->icache.waybit = 0;
1349
1350                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1351                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1352                 if (prid & 0x3)
1353                         c->dcache.ways = 4;
1354                 else
1355                         c->dcache.ways = 2;
1356                 c->dcache.waybit = 0;
1357                 break;
1358
1359         case CPU_LOONGSON3:
1360                 config1 = read_c0_config1();
1361                 lsize = (config1 >> 19) & 7;
1362                 if (lsize)
1363                         c->icache.linesz = 2 << lsize;
1364                 else
1365                         c->icache.linesz = 0;
1366                 c->icache.sets = 64 << ((config1 >> 22) & 7);
1367                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1368                 icache_size = c->icache.sets *
1369                                           c->icache.ways *
1370                                           c->icache.linesz;
1371                 c->icache.waybit = 0;
1372
1373                 lsize = (config1 >> 10) & 7;
1374                 if (lsize)
1375                         c->dcache.linesz = 2 << lsize;
1376                 else
1377                         c->dcache.linesz = 0;
1378                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1379                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1380                 dcache_size = c->dcache.sets *
1381                                           c->dcache.ways *
1382                                           c->dcache.linesz;
1383                 c->dcache.waybit = 0;
1384                 if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
1385                         c->options |= MIPS_CPU_PREFETCH;
1386                 break;
1387
1388         case CPU_CAVIUM_OCTEON3:
1389                 /* For now lie about the number of ways. */
1390                 c->icache.linesz = 128;
1391                 c->icache.sets = 16;
1392                 c->icache.ways = 8;
1393                 c->icache.flags |= MIPS_CACHE_VTAG;
1394                 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1395
1396                 c->dcache.linesz = 128;
1397                 c->dcache.ways = 8;
1398                 c->dcache.sets = 8;
1399                 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1400                 c->options |= MIPS_CPU_PREFETCH;
1401                 break;
1402
1403         default:
1404                 if (!(config & MIPS_CONF_M))
1405                         panic("Don't know how to probe P-caches on this cpu.");
1406
1407                 /*
1408                  * So we seem to be a MIPS32 or MIPS64 CPU
1409                  * So let's probe the I-cache ...
1410                  */
1411                 config1 = read_c0_config1();
1412
1413                 lsize = (config1 >> 19) & 7;
1414
1415                 /* IL == 7 is reserved */
1416                 if (lsize == 7)
1417                         panic("Invalid icache line size");
1418
1419                 c->icache.linesz = lsize ? 2 << lsize : 0;
1420
1421                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1422                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1423
1424                 icache_size = c->icache.sets *
1425                               c->icache.ways *
1426                               c->icache.linesz;
1427                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1428
1429                 if (config & MIPS_CONF_VI)
1430                         c->icache.flags |= MIPS_CACHE_VTAG;
1431
1432                 /*
1433                  * Now probe the MIPS32 / MIPS64 data cache.
1434                  */
1435                 c->dcache.flags = 0;
1436
1437                 lsize = (config1 >> 10) & 7;
1438
1439                 /* DL == 7 is reserved */
1440                 if (lsize == 7)
1441                         panic("Invalid dcache line size");
1442
1443                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1444
1445                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1446                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1447
1448                 dcache_size = c->dcache.sets *
1449                               c->dcache.ways *
1450                               c->dcache.linesz;
1451                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1452
1453                 c->options |= MIPS_CPU_PREFETCH;
1454                 break;
1455         }
1456
1457         /*
1458          * Processor configuration sanity check for the R4000SC erratum
1459          * #5.  With page sizes larger than 32kB there is no possibility
1460          * to get a VCE exception anymore so we don't care about this
1461          * misconfiguration.  The case is rather theoretical anyway;
1462          * presumably no vendor is shipping his hardware in the "bad"
1463          * configuration.
1464          */
1465         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1466             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1467             !(config & CONF_SC) && c->icache.linesz != 16 &&
1468             PAGE_SIZE <= 0x8000)
1469                 panic("Improper R4000SC processor configuration detected");
1470
1471         /* compute a couple of other cache variables */
1472         c->icache.waysize = icache_size / c->icache.ways;
1473         c->dcache.waysize = dcache_size / c->dcache.ways;
1474
1475         c->icache.sets = c->icache.linesz ?
1476                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1477         c->dcache.sets = c->dcache.linesz ?
1478                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1479
1480         /*
1481          * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
1482          * virtually indexed so normally would suffer from aliases.  So
1483          * normally they'd suffer from aliases but magic in the hardware deals
1484          * with that for us so we don't need to take care ourselves.
1485          */
1486         switch (current_cpu_type()) {
1487         case CPU_20KC:
1488         case CPU_25KF:
1489         case CPU_I6400:
1490         case CPU_I6500:
1491         case CPU_SB1:
1492         case CPU_SB1A:
1493         case CPU_XLR:
1494                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1495                 break;
1496
1497         case CPU_R10000:
1498         case CPU_R12000:
1499         case CPU_R14000:
1500         case CPU_R16000:
1501                 break;
1502
1503         case CPU_74K:
1504         case CPU_1074K:
1505                 has_74k_erratum = alias_74k_erratum(c);
1506                 /* Fall through. */
1507         case CPU_M14KC:
1508         case CPU_M14KEC:
1509         case CPU_24K:
1510         case CPU_34K:
1511         case CPU_1004K:
1512         case CPU_INTERAPTIV:
1513         case CPU_P5600:
1514         case CPU_PROAPTIV:
1515         case CPU_M5150:
1516         case CPU_QEMU_GENERIC:
1517         case CPU_P6600:
1518         case CPU_M6250:
1519                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1520                     (c->icache.waysize > PAGE_SIZE))
1521                         c->icache.flags |= MIPS_CACHE_ALIASES;
1522                 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1523                         /*
1524                          * Effectively physically indexed dcache,
1525                          * thus no virtual aliases.
1526                         */
1527                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1528                         break;
1529                 }
1530         default:
1531                 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1532                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1533         }
1534
1535         /* Physically indexed caches don't suffer from virtual aliasing */
1536         if (c->dcache.flags & MIPS_CACHE_PINDEX)
1537                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1538
1539         /*
1540          * In systems with CM the icache fills from L2 or closer caches, and
1541          * thus sees remote stores without needing to write them back any
1542          * further than that.
1543          */
1544         if (mips_cm_present())
1545                 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1546
1547         switch (current_cpu_type()) {
1548         case CPU_20KC:
1549                 /*
1550                  * Some older 20Kc chips doesn't have the 'VI' bit in
1551                  * the config register.
1552                  */
1553                 c->icache.flags |= MIPS_CACHE_VTAG;
1554                 break;
1555
1556         case CPU_ALCHEMY:
1557         case CPU_I6400:
1558         case CPU_I6500:
1559                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1560                 break;
1561
1562         case CPU_BMIPS5000:
1563                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1564                 /* Cache aliases are handled in hardware; allow HIGHMEM */
1565                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1566                 break;
1567
1568         case CPU_LOONGSON2:
1569                 /*
1570                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1571                  * one op will act on all 4 ways
1572                  */
1573                 c->icache.ways = 1;
1574         }
1575
1576         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1577                icache_size >> 10,
1578                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1579                way_string[c->icache.ways], c->icache.linesz);
1580
1581         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1582                dcache_size >> 10, way_string[c->dcache.ways],
1583                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1584                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1585                         "cache aliases" : "no aliases",
1586                c->dcache.linesz);
1587 }
1588
1589 static void probe_vcache(void)
1590 {
1591         struct cpuinfo_mips *c = &current_cpu_data;
1592         unsigned int config2, lsize;
1593
1594         if (current_cpu_type() != CPU_LOONGSON3)
1595                 return;
1596
1597         config2 = read_c0_config2();
1598         if ((lsize = ((config2 >> 20) & 15)))
1599                 c->vcache.linesz = 2 << lsize;
1600         else
1601                 c->vcache.linesz = lsize;
1602
1603         c->vcache.sets = 64 << ((config2 >> 24) & 15);
1604         c->vcache.ways = 1 + ((config2 >> 16) & 15);
1605
1606         vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1607
1608         c->vcache.waybit = 0;
1609         c->vcache.waysize = vcache_size / c->vcache.ways;
1610
1611         pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1612                 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1613 }
1614
1615 /*
1616  * If you even _breathe_ on this function, look at the gcc output and make sure
1617  * it does not pop things on and off the stack for the cache sizing loop that
1618  * executes in KSEG1 space or else you will crash and burn badly.  You have
1619  * been warned.
1620  */
1621 static int probe_scache(void)
1622 {
1623         unsigned long flags, addr, begin, end, pow2;
1624         unsigned int config = read_c0_config();
1625         struct cpuinfo_mips *c = &current_cpu_data;
1626
1627         if (config & CONF_SC)
1628                 return 0;
1629
1630         begin = (unsigned long) &_stext;
1631         begin &= ~((4 * 1024 * 1024) - 1);
1632         end = begin + (4 * 1024 * 1024);
1633
1634         /*
1635          * This is such a bitch, you'd think they would make it easy to do
1636          * this.  Away you daemons of stupidity!
1637          */
1638         local_irq_save(flags);
1639
1640         /* Fill each size-multiple cache line with a valid tag. */
1641         pow2 = (64 * 1024);
1642         for (addr = begin; addr < end; addr = (begin + pow2)) {
1643                 unsigned long *p = (unsigned long *) addr;
1644                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1645                 pow2 <<= 1;
1646         }
1647
1648         /* Load first line with zero (therefore invalid) tag. */
1649         write_c0_taglo(0);
1650         write_c0_taghi(0);
1651         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1652         cache_op(Index_Store_Tag_I, begin);
1653         cache_op(Index_Store_Tag_D, begin);
1654         cache_op(Index_Store_Tag_SD, begin);
1655
1656         /* Now search for the wrap around point. */
1657         pow2 = (128 * 1024);
1658         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1659                 cache_op(Index_Load_Tag_SD, addr);
1660                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1661                 if (!read_c0_taglo())
1662                         break;
1663                 pow2 <<= 1;
1664         }
1665         local_irq_restore(flags);
1666         addr -= begin;
1667
1668         scache_size = addr;
1669         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1670         c->scache.ways = 1;
1671         c->scache.waybit = 0;           /* does not matter */
1672
1673         return 1;
1674 }
1675
1676 static void loongson2_sc_init(void)
1677 {
1678         struct cpuinfo_mips *c = &current_cpu_data;
1679
1680         scache_size = 512*1024;
1681         c->scache.linesz = 32;
1682         c->scache.ways = 4;
1683         c->scache.waybit = 0;
1684         c->scache.waysize = scache_size / (c->scache.ways);
1685         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1686         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1687                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1688
1689         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1690 }
1691
1692 static void __init loongson3_sc_init(void)
1693 {
1694         struct cpuinfo_mips *c = &current_cpu_data;
1695         unsigned int config2, lsize;
1696
1697         config2 = read_c0_config2();
1698         lsize = (config2 >> 4) & 15;
1699         if (lsize)
1700                 c->scache.linesz = 2 << lsize;
1701         else
1702                 c->scache.linesz = 0;
1703         c->scache.sets = 64 << ((config2 >> 8) & 15);
1704         c->scache.ways = 1 + (config2 & 15);
1705
1706         scache_size = c->scache.sets *
1707                                   c->scache.ways *
1708                                   c->scache.linesz;
1709         /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1710         scache_size *= 4;
1711         c->scache.waybit = 0;
1712         c->scache.waysize = scache_size / c->scache.ways;
1713         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1714                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1715         if (scache_size)
1716                 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1717         return;
1718 }
1719
1720 extern int r5k_sc_init(void);
1721 extern int rm7k_sc_init(void);
1722 extern int mips_sc_init(void);
1723
1724 static void setup_scache(void)
1725 {
1726         struct cpuinfo_mips *c = &current_cpu_data;
1727         unsigned int config = read_c0_config();
1728         int sc_present = 0;
1729
1730         /*
1731          * Do the probing thing on R4000SC and R4400SC processors.  Other
1732          * processors don't have a S-cache that would be relevant to the
1733          * Linux memory management.
1734          */
1735         switch (current_cpu_type()) {
1736         case CPU_R4000SC:
1737         case CPU_R4000MC:
1738         case CPU_R4400SC:
1739         case CPU_R4400MC:
1740                 sc_present = run_uncached(probe_scache);
1741                 if (sc_present)
1742                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1743                 break;
1744
1745         case CPU_R10000:
1746         case CPU_R12000:
1747         case CPU_R14000:
1748         case CPU_R16000:
1749                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1750                 c->scache.linesz = 64 << ((config >> 13) & 1);
1751                 c->scache.ways = 2;
1752                 c->scache.waybit= 0;
1753                 sc_present = 1;
1754                 break;
1755
1756         case CPU_R5000:
1757         case CPU_NEVADA:
1758 #ifdef CONFIG_R5000_CPU_SCACHE
1759                 r5k_sc_init();
1760 #endif
1761                 return;
1762
1763         case CPU_RM7000:
1764 #ifdef CONFIG_RM7000_CPU_SCACHE
1765                 rm7k_sc_init();
1766 #endif
1767                 return;
1768
1769         case CPU_LOONGSON2:
1770                 loongson2_sc_init();
1771                 return;
1772
1773         case CPU_LOONGSON3:
1774                 loongson3_sc_init();
1775                 return;
1776
1777         case CPU_CAVIUM_OCTEON3:
1778         case CPU_XLP:
1779                 /* don't need to worry about L2, fully coherent */
1780                 return;
1781
1782         default:
1783                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1784                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1785                                     MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1786 #ifdef CONFIG_MIPS_CPU_SCACHE
1787                         if (mips_sc_init ()) {
1788                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1789                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1790                                        scache_size >> 10,
1791                                        way_string[c->scache.ways], c->scache.linesz);
1792
1793                                 if (current_cpu_type() == CPU_BMIPS5000)
1794                                         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1795                         }
1796
1797 #else
1798                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1799                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1800 #endif
1801                         return;
1802                 }
1803                 sc_present = 0;
1804         }
1805
1806         if (!sc_present)
1807                 return;
1808
1809         /* compute a couple of other cache variables */
1810         c->scache.waysize = scache_size / c->scache.ways;
1811
1812         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1813
1814         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1815                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1816
1817         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1818 }
1819
1820 void au1x00_fixup_config_od(void)
1821 {
1822         /*
1823          * c0_config.od (bit 19) was write only (and read as 0)
1824          * on the early revisions of Alchemy SOCs.  It disables the bus
1825          * transaction overlapping and needs to be set to fix various errata.
1826          */
1827         switch (read_c0_prid()) {
1828         case 0x00030100: /* Au1000 DA */
1829         case 0x00030201: /* Au1000 HA */
1830         case 0x00030202: /* Au1000 HB */
1831         case 0x01030200: /* Au1500 AB */
1832         /*
1833          * Au1100 errata actually keeps silence about this bit, so we set it
1834          * just in case for those revisions that require it to be set according
1835          * to the (now gone) cpu table.
1836          */
1837         case 0x02030200: /* Au1100 AB */
1838         case 0x02030201: /* Au1100 BA */
1839         case 0x02030202: /* Au1100 BC */
1840                 set_c0_config(1 << 19);
1841                 break;
1842         }
1843 }
1844
1845 /* CP0 hazard avoidance. */
1846 #define NXP_BARRIER()                                                   \
1847          __asm__ __volatile__(                                          \
1848         ".set noreorder\n\t"                                            \
1849         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1850         ".set reorder\n\t")
1851
1852 static void nxp_pr4450_fixup_config(void)
1853 {
1854         unsigned long config0;
1855
1856         config0 = read_c0_config();
1857
1858         /* clear all three cache coherency fields */
1859         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1860         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1861                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1862                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1863         write_c0_config(config0);
1864         NXP_BARRIER();
1865 }
1866
1867 static int cca = -1;
1868
1869 static int __init cca_setup(char *str)
1870 {
1871         get_option(&str, &cca);
1872
1873         return 0;
1874 }
1875
1876 early_param("cca", cca_setup);
1877
1878 static void coherency_setup(void)
1879 {
1880         if (cca < 0 || cca > 7)
1881                 cca = read_c0_config() & CONF_CM_CMASK;
1882         _page_cachable_default = cca << _CACHE_SHIFT;
1883
1884         pr_debug("Using cache attribute %d\n", cca);
1885         change_c0_config(CONF_CM_CMASK, cca);
1886
1887         /*
1888          * c0_status.cu=0 specifies that updates by the sc instruction use
1889          * the coherency mode specified by the TLB; 1 means cachable
1890          * coherent update on write will be used.  Not all processors have
1891          * this bit and; some wire it to zero, others like Toshiba had the
1892          * silly idea of putting something else there ...
1893          */
1894         switch (current_cpu_type()) {
1895         case CPU_R4000PC:
1896         case CPU_R4000SC:
1897         case CPU_R4000MC:
1898         case CPU_R4400PC:
1899         case CPU_R4400SC:
1900         case CPU_R4400MC:
1901                 clear_c0_config(CONF_CU);
1902                 break;
1903         /*
1904          * We need to catch the early Alchemy SOCs with
1905          * the write-only co_config.od bit and set it back to one on:
1906          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1907          */
1908         case CPU_ALCHEMY:
1909                 au1x00_fixup_config_od();
1910                 break;
1911
1912         case PRID_IMP_PR4450:
1913                 nxp_pr4450_fixup_config();
1914                 break;
1915         }
1916 }
1917
1918 static void r4k_cache_error_setup(void)
1919 {
1920         extern char __weak except_vec2_generic;
1921         extern char __weak except_vec2_sb1;
1922
1923         switch (current_cpu_type()) {
1924         case CPU_SB1:
1925         case CPU_SB1A:
1926                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1927                 break;
1928
1929         default:
1930                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1931                 break;
1932         }
1933 }
1934
1935 void r4k_cache_init(void)
1936 {
1937         extern void build_clear_page(void);
1938         extern void build_copy_page(void);
1939         struct cpuinfo_mips *c = &current_cpu_data;
1940
1941         probe_pcache();
1942         probe_vcache();
1943         setup_scache();
1944
1945         r4k_blast_dcache_page_setup();
1946         r4k_blast_dcache_page_indexed_setup();
1947         r4k_blast_dcache_setup();
1948         r4k_blast_icache_page_setup();
1949         r4k_blast_icache_page_indexed_setup();
1950         r4k_blast_icache_setup();
1951         r4k_blast_scache_page_setup();
1952         r4k_blast_scache_page_indexed_setup();
1953         r4k_blast_scache_setup();
1954         r4k_blast_scache_node_setup();
1955 #ifdef CONFIG_EVA
1956         r4k_blast_dcache_user_page_setup();
1957         r4k_blast_icache_user_page_setup();
1958 #endif
1959
1960         /*
1961          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1962          * This code supports virtually indexed processors and will be
1963          * unnecessarily inefficient on physically indexed processors.
1964          */
1965         if (c->dcache.linesz && cpu_has_dc_aliases)
1966                 shm_align_mask = max_t( unsigned long,
1967                                         c->dcache.sets * c->dcache.linesz - 1,
1968                                         PAGE_SIZE - 1);
1969         else
1970                 shm_align_mask = PAGE_SIZE-1;
1971
1972         __flush_cache_vmap      = r4k__flush_cache_vmap;
1973         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1974
1975         flush_cache_all         = cache_noop;
1976         __flush_cache_all       = r4k___flush_cache_all;
1977         flush_cache_mm          = r4k_flush_cache_mm;
1978         flush_cache_page        = r4k_flush_cache_page;
1979         flush_cache_range       = r4k_flush_cache_range;
1980
1981         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1982
1983         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1984         flush_icache_all        = r4k_flush_icache_all;
1985         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1986         flush_data_cache_page   = r4k_flush_data_cache_page;
1987         flush_icache_range      = r4k_flush_icache_range;
1988         local_flush_icache_range        = local_r4k_flush_icache_range;
1989         __flush_icache_user_range       = r4k_flush_icache_user_range;
1990         __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1991
1992 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1993 # if defined(CONFIG_DMA_PERDEV_COHERENT)
1994         if (0) {
1995 # else
1996         if ((coherentio == IO_COHERENCE_ENABLED) ||
1997             ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) {
1998 # endif
1999                 _dma_cache_wback_inv    = (void *)cache_noop;
2000                 _dma_cache_wback        = (void *)cache_noop;
2001                 _dma_cache_inv          = (void *)cache_noop;
2002         } else {
2003                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
2004                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
2005                 _dma_cache_inv          = r4k_dma_cache_inv;
2006         }
2007 #endif
2008
2009         build_clear_page();
2010         build_copy_page();
2011
2012         /*
2013          * We want to run CMP kernels on core with and without coherent
2014          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
2015          * or not to flush caches.
2016          */
2017         local_r4k___flush_cache_all(NULL);
2018
2019         coherency_setup();
2020         board_cache_error_setup = r4k_cache_error_setup;
2021
2022         /*
2023          * Per-CPU overrides
2024          */
2025         switch (current_cpu_type()) {
2026         case CPU_BMIPS4350:
2027         case CPU_BMIPS4380:
2028                 /* No IPI is needed because all CPUs share the same D$ */
2029                 flush_data_cache_page = r4k_blast_dcache_page;
2030                 break;
2031         case CPU_BMIPS5000:
2032                 /* We lose our superpowers if L2 is disabled */
2033                 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
2034                         break;
2035
2036                 /* I$ fills from D$ just by emptying the write buffers */
2037                 flush_cache_page = (void *)b5k_instruction_hazard;
2038                 flush_cache_range = (void *)b5k_instruction_hazard;
2039                 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
2040                 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
2041                 flush_data_cache_page = (void *)b5k_instruction_hazard;
2042                 flush_icache_range = (void *)b5k_instruction_hazard;
2043                 local_flush_icache_range = (void *)b5k_instruction_hazard;
2044
2045
2046                 /* Optimization: an L2 flush implicitly flushes the L1 */
2047                 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
2048                 break;
2049         case CPU_LOONGSON3:
2050                 /* Loongson-3 maintains cache coherency by hardware */
2051                 __flush_cache_all       = cache_noop;
2052                 __flush_cache_vmap      = cache_noop;
2053                 __flush_cache_vunmap    = cache_noop;
2054                 __flush_kernel_vmap_range = (void *)cache_noop;
2055                 flush_cache_mm          = (void *)cache_noop;
2056                 flush_cache_page        = (void *)cache_noop;
2057                 flush_cache_range       = (void *)cache_noop;
2058                 flush_cache_sigtramp    = (void *)cache_noop;
2059                 flush_icache_all        = (void *)cache_noop;
2060                 flush_data_cache_page   = (void *)cache_noop;
2061                 local_flush_data_cache_page     = (void *)cache_noop;
2062                 break;
2063         }
2064 }
2065
2066 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
2067                                void *v)
2068 {
2069         switch (cmd) {
2070         case CPU_PM_ENTER_FAILED:
2071         case CPU_PM_EXIT:
2072                 coherency_setup();
2073                 break;
2074         }
2075
2076         return NOTIFY_OK;
2077 }
2078
2079 static struct notifier_block r4k_cache_pm_notifier_block = {
2080         .notifier_call = r4k_cache_pm_notifier,
2081 };
2082
2083 int __init r4k_cache_init_pm(void)
2084 {
2085         return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
2086 }
2087 arch_initcall(r4k_cache_init_pm);