2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2005-2007 Cavium Networks
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/smp.h>
13 #include <linux/bitops.h>
14 #include <linux/cpu.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cacheops.h>
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
23 #include <asm/r4kcache.h>
24 #include <asm/traps.h>
25 #include <asm/mmu_context.h>
27 #include <asm/octeon/octeon.h>
29 unsigned long long cache_err_dcache[NR_CPUS];
30 EXPORT_SYMBOL_GPL(cache_err_dcache);
33 * Octeon automatically flushes the dcache on tlb changes, so
34 * from Linux's viewpoint it acts much like a physically
35 * tagged cache. No flushing is needed
38 static void octeon_flush_data_cache_page(unsigned long addr)
43 static inline void octeon_local_flush_icache(void)
45 asm volatile ("synci 0($0)");
49 * Flush local I-cache for the specified range.
51 static void local_octeon_flush_icache_range(unsigned long start,
54 octeon_local_flush_icache();
58 * octeon_flush_icache_all_cores - Flush caches as necessary for all cores
59 * affected by a vma. If no vma is supplied, all cores are flushed.
61 * @vma: VMA to flush or NULL to flush all icaches.
63 static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
65 extern void octeon_send_ipi_single(int cpu, unsigned int action);
72 octeon_local_flush_icache();
75 cpu = smp_processor_id();
78 * If we have a vma structure, we only need to worry about
79 * cores it has been used on
82 mask = *mm_cpumask(vma->vm_mm);
84 mask = *cpu_online_mask;
85 cpumask_clear_cpu(cpu, &mask);
86 for_each_cpu(cpu, &mask)
87 octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
95 * Called to flush the icache on all cores
97 static void octeon_flush_icache_all(void)
99 octeon_flush_icache_all_cores(NULL);
104 * octeon_flush_cache_mm - flush all memory associated with a memory context.
106 * @mm: Memory context to flush
108 static void octeon_flush_cache_mm(struct mm_struct *mm)
111 * According to the R4K version of this file, CPUs without
112 * dcache aliases don't need to do anything here
118 * Flush a range of kernel addresses out of the icache
121 static void octeon_flush_icache_range(unsigned long start, unsigned long end)
123 octeon_flush_icache_all_cores(NULL);
128 * octeon_flush_cache_range - Flush a range out of a vma
131 * @start: beginning address for flush
132 * @end: ending address for flush
134 static void octeon_flush_cache_range(struct vm_area_struct *vma,
135 unsigned long start, unsigned long end)
137 if (vma->vm_flags & VM_EXEC)
138 octeon_flush_icache_all_cores(vma);
143 * octeon_flush_cache_page - Flush a specific page of a vma
145 * @vma: VMA to flush page for
146 * @page: Page to flush
147 * @pfn: Page frame number
149 static void octeon_flush_cache_page(struct vm_area_struct *vma,
150 unsigned long page, unsigned long pfn)
152 if (vma->vm_flags & VM_EXEC)
153 octeon_flush_icache_all_cores(vma);
156 static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
162 * Probe Octeon's caches
165 static void probe_octeon(void)
167 unsigned long icache_size;
168 unsigned long dcache_size;
169 unsigned int config1;
170 struct cpuinfo_mips *c = ¤t_cpu_data;
171 int cputype = current_cpu_type();
173 config1 = read_c0_config1();
175 case CPU_CAVIUM_OCTEON:
176 case CPU_CAVIUM_OCTEON_PLUS:
177 c->icache.linesz = 2 << ((config1 >> 19) & 7);
178 c->icache.sets = 64 << ((config1 >> 22) & 7);
179 c->icache.ways = 1 + ((config1 >> 16) & 7);
180 c->icache.flags |= MIPS_CACHE_VTAG;
182 c->icache.sets * c->icache.ways * c->icache.linesz;
183 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
184 c->dcache.linesz = 128;
185 if (cputype == CPU_CAVIUM_OCTEON_PLUS)
186 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
188 c->dcache.sets = 1; /* CN3XXX has one Dcache set */
191 c->dcache.sets * c->dcache.ways * c->dcache.linesz;
192 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
193 c->options |= MIPS_CPU_PREFETCH;
196 case CPU_CAVIUM_OCTEON2:
197 c->icache.linesz = 2 << ((config1 >> 19) & 7);
200 c->icache.flags |= MIPS_CACHE_VTAG;
201 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
203 c->dcache.linesz = 128;
206 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
207 c->options |= MIPS_CPU_PREFETCH;
210 case CPU_CAVIUM_OCTEON3:
211 c->icache.linesz = 128;
214 c->icache.flags |= MIPS_CACHE_VTAG;
215 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
217 c->dcache.linesz = 128;
220 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
221 c->options |= MIPS_CPU_PREFETCH;
225 panic("Unsupported Cavium Networks CPU type");
229 /* compute a couple of other cache variables */
230 c->icache.waysize = icache_size / c->icache.ways;
231 c->dcache.waysize = dcache_size / c->dcache.ways;
233 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
234 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
236 if (smp_processor_id() == 0) {
237 pr_info("Primary instruction cache %ldkB, %s, %d way, "
238 "%d sets, linesize %d bytes.\n",
240 cpu_has_vtag_icache ?
241 "virtually tagged" : "physically tagged",
242 c->icache.ways, c->icache.sets, c->icache.linesz);
244 pr_info("Primary data cache %ldkB, %d-way, %d sets, "
245 "linesize %d bytes.\n",
246 dcache_size >> 10, c->dcache.ways,
247 c->dcache.sets, c->dcache.linesz);
251 static void octeon_cache_error_setup(void)
253 extern char except_vec2_octeon;
254 set_handler(0x100, &except_vec2_octeon, 0x80);
258 * Setup the Octeon cache flush routines
261 void octeon_cache_init(void)
265 shm_align_mask = PAGE_SIZE - 1;
267 flush_cache_all = octeon_flush_icache_all;
268 __flush_cache_all = octeon_flush_icache_all;
269 flush_cache_mm = octeon_flush_cache_mm;
270 flush_cache_page = octeon_flush_cache_page;
271 flush_cache_range = octeon_flush_cache_range;
272 flush_icache_all = octeon_flush_icache_all;
273 flush_data_cache_page = octeon_flush_data_cache_page;
274 flush_icache_range = octeon_flush_icache_range;
275 local_flush_icache_range = local_octeon_flush_icache_range;
276 __flush_icache_user_range = octeon_flush_icache_range;
277 __local_flush_icache_user_range = local_octeon_flush_icache_range;
279 __flush_kernel_vmap_range = octeon_flush_kernel_vmap_range;
284 board_cache_error_setup = octeon_cache_error_setup;
288 * Handle a cache error exception
290 static RAW_NOTIFIER_HEAD(co_cache_error_chain);
292 int register_co_cache_error_notifier(struct notifier_block *nb)
294 return raw_notifier_chain_register(&co_cache_error_chain, nb);
296 EXPORT_SYMBOL_GPL(register_co_cache_error_notifier);
298 int unregister_co_cache_error_notifier(struct notifier_block *nb)
300 return raw_notifier_chain_unregister(&co_cache_error_chain, nb);
302 EXPORT_SYMBOL_GPL(unregister_co_cache_error_notifier);
304 static void co_cache_error_call_notifiers(unsigned long val)
306 int rv = raw_notifier_call_chain(&co_cache_error_chain, val, NULL);
307 if ((rv & ~NOTIFY_STOP_MASK) != NOTIFY_OK) {
309 unsigned long coreid = cvmx_get_core_num();
310 u64 icache_err = read_octeon_c0_icacheerr();
313 dcache_err = cache_err_dcache[coreid];
314 cache_err_dcache[coreid] = 0;
316 dcache_err = read_octeon_c0_dcacheerr();
319 pr_err("Core%lu: Cache error exception:\n", coreid);
320 pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
321 if (icache_err & 1) {
322 pr_err("CacheErr (Icache) == %llx\n",
323 (unsigned long long)icache_err);
324 write_octeon_c0_icacheerr(0);
326 if (dcache_err & 1) {
327 pr_err("CacheErr (Dcache) == %llx\n",
328 (unsigned long long)dcache_err);
334 * Called when the exception is recoverable
337 asmlinkage void cache_parity_error_octeon_recoverable(void)
339 co_cache_error_call_notifiers(0);
343 * Called when the exception is not recoverable
346 asmlinkage void cache_parity_error_octeon_non_recoverable(void)
348 co_cache_error_call_notifiers(1);
349 panic("Can't handle cache error: nested exception");