2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
52 #include <asm/mips-r2-to-r6-emul.h>
56 /* Function which emulates a floating point instruction. */
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
64 /* Control registers */
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
101 switch (insn.mm_i_format.opcode) {
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
134 switch (insn.mm_fp0_format.func) {
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
146 else if (op == mm_32f_11_op)
148 else if (op == mm_32f_02_op)
150 else if (op == mm_32f_12_op)
152 else if (op == mm_32f_41_op)
154 else if (op == mm_32f_51_op)
156 else if (op == mm_32f_42_op)
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
172 else if (op == mm_sdxc1_op)
174 else if (op == mm_lwxc1_op)
176 else if (op == mm_swxc1_op)
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
261 if ((insn.mm_fp1_format.op & 0x7f) ==
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
278 if ((insn.mm_fp1_format.op & 0x7f) ==
281 fmt = swl_format[insn.mm_fp3_format.fmt];
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
301 if ((insn.mm_fp1_format.op & 0x7f) ==
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
427 *insn_ptr = mips32_insn;
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
442 unsigned int bit = 0;
444 switch (insn.i_format.opcode) {
446 switch (insn.r_format.func) {
448 if (insn.r_format.rd != 0) {
449 regs->regs[insn.r_format.rd] =
450 regs->cp0_epc + dec_insn.pc_inc +
451 dec_insn.next_pc_inc;
455 /* For R6, JR already emulated in jalr_op */
456 if (NO_R6EMU && insn.r_format.func == jr_op)
458 *contpc = regs->regs[insn.r_format.rs];
463 switch (insn.i_format.rt) {
466 if (NO_R6EMU && (insn.i_format.rs ||
467 insn.i_format.rt == bltzall_op))
470 regs->regs[31] = regs->cp0_epc +
472 dec_insn.next_pc_inc;
478 if ((long)regs->regs[insn.i_format.rs] < 0)
479 *contpc = regs->cp0_epc +
481 (insn.i_format.simmediate << 2);
483 *contpc = regs->cp0_epc +
485 dec_insn.next_pc_inc;
489 if (NO_R6EMU && (insn.i_format.rs ||
490 insn.i_format.rt == bgezall_op))
493 regs->regs[31] = regs->cp0_epc +
495 dec_insn.next_pc_inc;
501 if ((long)regs->regs[insn.i_format.rs] >= 0)
502 *contpc = regs->cp0_epc +
504 (insn.i_format.simmediate << 2);
506 *contpc = regs->cp0_epc +
508 dec_insn.next_pc_inc;
515 regs->regs[31] = regs->cp0_epc +
517 dec_insn.next_pc_inc;
520 *contpc = regs->cp0_epc + dec_insn.pc_inc;
523 *contpc |= (insn.j_format.target << 2);
524 /* Set microMIPS mode bit: XOR for jalx. */
531 if (regs->regs[insn.i_format.rs] ==
532 regs->regs[insn.i_format.rt])
533 *contpc = regs->cp0_epc +
535 (insn.i_format.simmediate << 2);
537 *contpc = regs->cp0_epc +
539 dec_insn.next_pc_inc;
545 if (regs->regs[insn.i_format.rs] !=
546 regs->regs[insn.i_format.rt])
547 *contpc = regs->cp0_epc +
549 (insn.i_format.simmediate << 2);
551 *contpc = regs->cp0_epc +
553 dec_insn.next_pc_inc;
556 if (!insn.i_format.rt && NO_R6EMU)
561 * Compact branches for R6 for the
562 * blez and blezl opcodes.
563 * BLEZ | rs = 0 | rt != 0 == BLEZALC
564 * BLEZ | rs = rt != 0 == BGEZALC
565 * BLEZ | rs != 0 | rt != 0 == BGEUC
566 * BLEZL | rs = 0 | rt != 0 == BLEZC
567 * BLEZL | rs = rt != 0 == BGEZC
568 * BLEZL | rs != 0 | rt != 0 == BGEC
570 * For real BLEZ{,L}, rt is always 0.
572 if (cpu_has_mips_r6 && insn.i_format.rt) {
573 if ((insn.i_format.opcode == blez_op) &&
574 ((!insn.i_format.rs && insn.i_format.rt) ||
575 (insn.i_format.rs == insn.i_format.rt)))
576 regs->regs[31] = regs->cp0_epc +
578 *contpc = regs->cp0_epc + dec_insn.pc_inc +
579 dec_insn.next_pc_inc;
583 if ((long)regs->regs[insn.i_format.rs] <= 0)
584 *contpc = regs->cp0_epc +
586 (insn.i_format.simmediate << 2);
588 *contpc = regs->cp0_epc +
590 dec_insn.next_pc_inc;
593 if (!insn.i_format.rt && NO_R6EMU)
597 * Compact branches for R6 for the
598 * bgtz and bgtzl opcodes.
599 * BGTZ | rs = 0 | rt != 0 == BGTZALC
600 * BGTZ | rs = rt != 0 == BLTZALC
601 * BGTZ | rs != 0 | rt != 0 == BLTUC
602 * BGTZL | rs = 0 | rt != 0 == BGTZC
603 * BGTZL | rs = rt != 0 == BLTZC
604 * BGTZL | rs != 0 | rt != 0 == BLTC
606 * *ZALC varint for BGTZ &&& rt != 0
607 * For real GTZ{,L}, rt is always 0.
609 if (cpu_has_mips_r6 && insn.i_format.rt) {
610 if ((insn.i_format.opcode == blez_op) &&
611 ((!insn.i_format.rs && insn.i_format.rt) ||
612 (insn.i_format.rs == insn.i_format.rt)))
613 regs->regs[31] = regs->cp0_epc +
615 *contpc = regs->cp0_epc + dec_insn.pc_inc +
616 dec_insn.next_pc_inc;
621 if ((long)regs->regs[insn.i_format.rs] > 0)
622 *contpc = regs->cp0_epc +
624 (insn.i_format.simmediate << 2);
626 *contpc = regs->cp0_epc +
628 dec_insn.next_pc_inc;
632 if (!cpu_has_mips_r6)
634 if (insn.i_format.rt && !insn.i_format.rs)
635 regs->regs[31] = regs->cp0_epc + 4;
636 *contpc = regs->cp0_epc + dec_insn.pc_inc +
637 dec_insn.next_pc_inc;
640 #ifdef CONFIG_CPU_CAVIUM_OCTEON
641 case lwc2_op: /* This is bbit0 on Octeon */
642 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
643 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
645 *contpc = regs->cp0_epc + 8;
647 case ldc2_op: /* This is bbit032 on Octeon */
648 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
649 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
651 *contpc = regs->cp0_epc + 8;
653 case swc2_op: /* This is bbit1 on Octeon */
654 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
655 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
657 *contpc = regs->cp0_epc + 8;
659 case sdc2_op: /* This is bbit132 on Octeon */
660 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
661 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
663 *contpc = regs->cp0_epc + 8;
668 * Only valid for MIPS R6 but we can still end up
669 * here from a broken userland so just tell emulator
670 * this is not a branch and let it break later on.
672 if (!cpu_has_mips_r6)
674 *contpc = regs->cp0_epc + dec_insn.pc_inc +
675 dec_insn.next_pc_inc;
679 if (!cpu_has_mips_r6)
681 regs->regs[31] = regs->cp0_epc + 4;
682 *contpc = regs->cp0_epc + dec_insn.pc_inc +
683 dec_insn.next_pc_inc;
687 if (!cpu_has_mips_r6)
689 *contpc = regs->cp0_epc + dec_insn.pc_inc +
690 dec_insn.next_pc_inc;
694 if (!cpu_has_mips_r6)
696 if (!insn.i_format.rs)
697 regs->regs[31] = regs->cp0_epc + 4;
698 *contpc = regs->cp0_epc + dec_insn.pc_inc +
699 dec_insn.next_pc_inc;
705 /* Need to check for R6 bc1nez and bc1eqz branches */
706 if (cpu_has_mips_r6 &&
707 ((insn.i_format.rs == bc1eqz_op) ||
708 (insn.i_format.rs == bc1nez_op))) {
710 switch (insn.i_format.rs) {
712 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
716 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
721 *contpc = regs->cp0_epc +
723 (insn.i_format.simmediate << 2);
725 *contpc = regs->cp0_epc +
727 dec_insn.next_pc_inc;
731 /* R2/R6 compatible cop1 instruction. Fall through */
734 if (insn.i_format.rs == bc_op) {
737 fcr31 = read_32bit_cp1_register(CP1_STATUS);
739 fcr31 = current->thread.fpu.fcr31;
742 bit = (insn.i_format.rt >> 2);
745 switch (insn.i_format.rt & 3) {
748 if (~fcr31 & (1 << bit))
749 *contpc = regs->cp0_epc +
751 (insn.i_format.simmediate << 2);
753 *contpc = regs->cp0_epc +
755 dec_insn.next_pc_inc;
759 if (fcr31 & (1 << bit))
760 *contpc = regs->cp0_epc +
762 (insn.i_format.simmediate << 2);
764 *contpc = regs->cp0_epc +
766 dec_insn.next_pc_inc;
776 * In the Linux kernel, we support selection of FPR format on the
777 * basis of the Status.FR bit. If an FPU is not present, the FR bit
778 * is hardwired to zero, which would imply a 32-bit FPU even for
779 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
780 * FPU emu is slow and bulky and optimizing this function offers fairly
781 * sizeable benefits so we try to be clever and make this function return
782 * a constant whenever possible, that is on 64-bit kernels without O32
783 * compatibility enabled and on 32-bit without 64-bit FPU support.
785 static inline int cop1_64bit(struct pt_regs *xcp)
787 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
789 else if (config_enabled(CONFIG_32BIT) &&
790 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
793 return !test_thread_flag(TIF_32BIT_FPREGS);
796 static inline bool hybrid_fprs(void)
798 return test_thread_flag(TIF_HYBRID_FPREGS);
801 #define SIFROMREG(si, x) \
803 if (cop1_64bit(xcp) && !hybrid_fprs()) \
804 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
806 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
809 #define SITOREG(si, x) \
811 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
813 set_fpr32(&ctx->fpr[x], 0, si); \
814 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
815 set_fpr32(&ctx->fpr[x], i, 0); \
817 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
821 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
823 #define SITOHREG(si, x) \
826 set_fpr32(&ctx->fpr[x], 1, si); \
827 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
828 set_fpr32(&ctx->fpr[x], i, 0); \
831 #define DIFROMREG(di, x) \
832 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0))
834 #define DITOREG(di, x) \
837 fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
838 set_fpr64(&ctx->fpr[fpr], 0, di); \
839 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
840 set_fpr64(&ctx->fpr[fpr], i, 0); \
843 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
844 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
845 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
846 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
849 * Emulate a CFC1 instruction.
851 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
854 u32 fcr31 = ctx->fcr31;
857 switch (MIPSInst_RD(ir)) {
860 pr_debug("%p gpr[%d]<-csr=%08x\n",
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
867 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
869 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
870 pr_debug("%p gpr[%d]<-enr=%08x\n",
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
877 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
878 pr_debug("%p gpr[%d]<-exr=%08x\n",
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
885 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
887 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
888 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
889 pr_debug("%p gpr[%d]<-ccr=%08x\n",
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
894 value = boot_cpu_data.fpu_id;
902 xcp->regs[MIPSInst_RT(ir)] = value;
906 * Emulate a CTC1 instruction.
908 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
911 u32 fcr31 = ctx->fcr31;
915 if (MIPSInst_RT(ir) == 0)
918 value = xcp->regs[MIPSInst_RT(ir)];
920 switch (MIPSInst_RD(ir)) {
922 pr_debug("%p gpr[%d]->csr=%08x\n",
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
925 /* Preserve read-only bits. */
926 mask = boot_cpu_data.fpu_msk31;
927 fcr31 = (value & ~mask) | (fcr31 & mask);
933 pr_debug("%p gpr[%d]->enr=%08x\n",
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
935 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
936 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
938 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
944 pr_debug("%p gpr[%d]->exr=%08x\n",
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
946 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
947 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
953 pr_debug("%p gpr[%d]->ccr=%08x\n",
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
955 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
956 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
958 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
970 * Emulate the single floating point instruction pointed at by EPC.
971 * Two instructions if the instruction is in a branch delay slot.
974 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
975 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
977 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
978 unsigned int cond, cbit, bit0;
989 * These are giving gcc a gentle hint about what to expect in
990 * dec_inst in order to do better optimization.
992 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
995 /* XXX NEC Vr54xx bug workaround */
996 if (delay_slot(xcp)) {
997 if (dec_insn.micro_mips_mode) {
998 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
999 clear_delay_slot(xcp);
1001 if (!isBranchInstr(xcp, dec_insn, &contpc))
1002 clear_delay_slot(xcp);
1006 if (delay_slot(xcp)) {
1008 * The instruction to be emulated is in a branch delay slot
1009 * which means that we have to emulate the branch instruction
1010 * BEFORE we do the cop1 instruction.
1012 * This branch could be a COP1 branch, but in that case we
1013 * would have had a trap for that instruction, and would not
1014 * come through this route.
1016 * Linux MIPS branch emulator operates on context, updating the
1019 ir = dec_insn.next_insn; /* process delay slot instr */
1020 pc_inc = dec_insn.next_pc_inc;
1022 ir = dec_insn.insn; /* process current instr */
1023 pc_inc = dec_insn.pc_inc;
1027 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1028 * instructions, we want to convert microMIPS FPU instructions
1029 * into MIPS32 instructions so that we could reuse all of the
1030 * FPU emulation code.
1032 * NOTE: We cannot do this for branch instructions since they
1033 * are not a subset. Example: Cannot emulate a 16-bit
1034 * aligned target address with a MIPS32 instruction.
1036 if (dec_insn.micro_mips_mode) {
1038 * If next instruction is a 16-bit instruction, then it
1039 * it cannot be a FPU instruction. This could happen
1040 * since we can be called for non-FPU instructions.
1042 if ((pc_inc == 2) ||
1043 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1049 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1050 MIPS_FPU_EMU_INC_STATS(emulated);
1051 switch (MIPSInst_OPCODE(ir)) {
1053 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1055 MIPS_FPU_EMU_INC_STATS(loads);
1057 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1058 MIPS_FPU_EMU_INC_STATS(errors);
1062 if (__get_user(dval, dva)) {
1063 MIPS_FPU_EMU_INC_STATS(errors);
1067 DITOREG(dval, MIPSInst_RT(ir));
1071 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1073 MIPS_FPU_EMU_INC_STATS(stores);
1074 DIFROMREG(dval, MIPSInst_RT(ir));
1075 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1076 MIPS_FPU_EMU_INC_STATS(errors);
1080 if (__put_user(dval, dva)) {
1081 MIPS_FPU_EMU_INC_STATS(errors);
1088 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1090 MIPS_FPU_EMU_INC_STATS(loads);
1091 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1092 MIPS_FPU_EMU_INC_STATS(errors);
1096 if (__get_user(wval, wva)) {
1097 MIPS_FPU_EMU_INC_STATS(errors);
1101 SITOREG(wval, MIPSInst_RT(ir));
1105 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1107 MIPS_FPU_EMU_INC_STATS(stores);
1108 SIFROMREG(wval, MIPSInst_RT(ir));
1109 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1110 MIPS_FPU_EMU_INC_STATS(errors);
1114 if (__put_user(wval, wva)) {
1115 MIPS_FPU_EMU_INC_STATS(errors);
1122 switch (MIPSInst_RS(ir)) {
1124 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1127 /* copregister fs -> gpr[rt] */
1128 if (MIPSInst_RT(ir) != 0) {
1129 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1135 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1138 /* copregister fs <- rt */
1139 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1143 if (!cpu_has_mips_r2_r6)
1146 /* copregister rd -> gpr[rt] */
1147 if (MIPSInst_RT(ir) != 0) {
1148 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1154 if (!cpu_has_mips_r2_r6)
1157 /* copregister rd <- gpr[rt] */
1158 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1162 /* copregister rd -> gpr[rt] */
1163 if (MIPSInst_RT(ir) != 0) {
1164 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1170 /* copregister rd <- rt */
1171 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1175 /* cop control register rd -> gpr[rt] */
1176 cop1_cfc(xcp, ctx, ir);
1180 /* copregister rd <- rt */
1181 cop1_ctc(xcp, ctx, ir);
1182 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1189 if (!cpu_has_mips_r6 || delay_slot(xcp))
1193 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1194 bit0 = get_fpr32(fpr, 0) & 0x1;
1195 switch (MIPSInst_RS(ir)) {
1206 if (delay_slot(xcp))
1209 if (cpu_has_mips_4_5_r)
1210 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1212 cbit = FPU_CSR_COND;
1213 cond = ctx->fcr31 & cbit;
1216 switch (MIPSInst_RT(ir) & 3) {
1218 if (cpu_has_mips_2_3_4_5_r)
1225 if (cpu_has_mips_2_3_4_5_r)
1232 set_delay_slot(xcp);
1235 * Branch taken: emulate dslot instruction
1240 * Remember EPC at the branch to point back
1241 * at so that any delay-slot instruction
1242 * signal is not silently ignored.
1244 bcpc = xcp->cp0_epc;
1245 xcp->cp0_epc += dec_insn.pc_inc;
1247 contpc = MIPSInst_SIMM(ir);
1248 ir = dec_insn.next_insn;
1249 if (dec_insn.micro_mips_mode) {
1250 contpc = (xcp->cp0_epc + (contpc << 1));
1252 /* If 16-bit instruction, not FPU. */
1253 if ((dec_insn.next_pc_inc == 2) ||
1254 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1257 * Since this instruction will
1258 * be put on the stack with
1259 * 32-bit words, get around
1260 * this problem by putting a
1261 * NOP16 as the second one.
1263 if (dec_insn.next_pc_inc == 2)
1264 ir = (ir & (~0xffff)) | MM_NOP16;
1267 * Single step the non-CP1
1268 * instruction in the dslot.
1270 sig = mips_dsemul(xcp, ir,
1273 xcp->cp0_epc = bcpc;
1275 * SIGILL forces out of
1276 * the emulation loop.
1278 return sig ? sig : SIGILL;
1281 contpc = (xcp->cp0_epc + (contpc << 2));
1283 switch (MIPSInst_OPCODE(ir)) {
1290 if (cpu_has_mips_2_3_4_5_r)
1299 if (cpu_has_mips_4_5_64_r2_r6)
1300 /* its one of ours */
1306 switch (MIPSInst_FUNC(ir)) {
1308 if (cpu_has_mips_4_5_r)
1316 xcp->cp0_epc = bcpc;
1321 * Single step the non-cp1
1322 * instruction in the dslot
1324 sig = mips_dsemul(xcp, ir, contpc);
1326 xcp->cp0_epc = bcpc;
1327 /* SIGILL forces out of the emulation loop. */
1328 return sig ? sig : SIGILL;
1329 } else if (likely) { /* branch not taken */
1331 * branch likely nullifies
1332 * dslot if not taken
1334 xcp->cp0_epc += dec_insn.pc_inc;
1335 contpc += dec_insn.pc_inc;
1337 * else continue & execute
1338 * dslot as normal insn
1344 if (!(MIPSInst_RS(ir) & 0x10))
1347 /* a real fpu computation instruction */
1348 if ((sig = fpu_emu(xcp, ctx, ir)))
1354 if (!cpu_has_mips_4_5_64_r2_r6)
1357 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1363 if (!cpu_has_mips_4_5_r)
1366 if (MIPSInst_FUNC(ir) != movc_op)
1368 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1369 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1370 xcp->regs[MIPSInst_RD(ir)] =
1371 xcp->regs[MIPSInst_RS(ir)];
1379 xcp->cp0_epc = contpc;
1380 clear_delay_slot(xcp);
1386 * Conversion table from MIPS compare ops 48-63
1387 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1389 static const unsigned char cmptab[8] = {
1390 0, /* cmp_0 (sig) cmp_sf */
1391 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1392 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1393 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1394 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1395 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1396 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1397 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1400 static const unsigned char negative_cmptab[8] = {
1402 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1403 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1404 IEEE754_CLT | IEEE754_CGT,
1410 * Additional MIPS4 instructions
1413 #define DEF3OP(name, p, f1, f2, f3) \
1414 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1415 union ieee754##p s, union ieee754##p t) \
1417 struct _ieee754_csr ieee754_csr_save; \
1419 ieee754_csr_save = ieee754_csr; \
1421 ieee754_csr_save.cx |= ieee754_csr.cx; \
1422 ieee754_csr_save.sx |= ieee754_csr.sx; \
1424 ieee754_csr.cx |= ieee754_csr_save.cx; \
1425 ieee754_csr.sx |= ieee754_csr_save.sx; \
1429 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1431 return ieee754dp_div(ieee754dp_one(0), d);
1434 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1436 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1439 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1441 return ieee754sp_div(ieee754sp_one(0), s);
1444 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1446 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1449 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1450 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1451 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1452 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1453 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1454 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1455 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1456 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1458 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1459 mips_instruction ir, void *__user *fault_addr)
1461 unsigned rcsr = 0; /* resulting csr */
1463 MIPS_FPU_EMU_INC_STATS(cp1xops);
1465 switch (MIPSInst_FMA_FFMT(ir)) {
1466 case s_fmt:{ /* 0 */
1468 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1469 union ieee754sp fd, fr, fs, ft;
1473 switch (MIPSInst_FUNC(ir)) {
1475 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1476 xcp->regs[MIPSInst_FT(ir)]);
1478 MIPS_FPU_EMU_INC_STATS(loads);
1479 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1480 MIPS_FPU_EMU_INC_STATS(errors);
1484 if (__get_user(val, va)) {
1485 MIPS_FPU_EMU_INC_STATS(errors);
1489 SITOREG(val, MIPSInst_FD(ir));
1493 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1494 xcp->regs[MIPSInst_FT(ir)]);
1496 MIPS_FPU_EMU_INC_STATS(stores);
1498 SIFROMREG(val, MIPSInst_FS(ir));
1499 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1500 MIPS_FPU_EMU_INC_STATS(errors);
1504 if (put_user(val, va)) {
1505 MIPS_FPU_EMU_INC_STATS(errors);
1512 handler = fpemu_sp_madd;
1515 handler = fpemu_sp_msub;
1518 handler = fpemu_sp_nmadd;
1521 handler = fpemu_sp_nmsub;
1525 SPFROMREG(fr, MIPSInst_FR(ir));
1526 SPFROMREG(fs, MIPSInst_FS(ir));
1527 SPFROMREG(ft, MIPSInst_FT(ir));
1528 fd = (*handler) (fr, fs, ft);
1529 SPTOREG(fd, MIPSInst_FD(ir));
1532 if (ieee754_cxtest(IEEE754_INEXACT)) {
1533 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1534 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1536 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1537 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1538 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1540 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1541 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1542 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1544 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1545 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1546 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1549 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1550 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1551 /*printk ("SIGFPE: FPU csr = %08x\n",
1564 case d_fmt:{ /* 1 */
1565 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1566 union ieee754dp fd, fr, fs, ft;
1570 switch (MIPSInst_FUNC(ir)) {
1572 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1573 xcp->regs[MIPSInst_FT(ir)]);
1575 MIPS_FPU_EMU_INC_STATS(loads);
1576 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1577 MIPS_FPU_EMU_INC_STATS(errors);
1581 if (__get_user(val, va)) {
1582 MIPS_FPU_EMU_INC_STATS(errors);
1586 DITOREG(val, MIPSInst_FD(ir));
1590 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1591 xcp->regs[MIPSInst_FT(ir)]);
1593 MIPS_FPU_EMU_INC_STATS(stores);
1594 DIFROMREG(val, MIPSInst_FS(ir));
1595 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1596 MIPS_FPU_EMU_INC_STATS(errors);
1600 if (__put_user(val, va)) {
1601 MIPS_FPU_EMU_INC_STATS(errors);
1608 handler = fpemu_dp_madd;
1611 handler = fpemu_dp_msub;
1614 handler = fpemu_dp_nmadd;
1617 handler = fpemu_dp_nmsub;
1621 DPFROMREG(fr, MIPSInst_FR(ir));
1622 DPFROMREG(fs, MIPSInst_FS(ir));
1623 DPFROMREG(ft, MIPSInst_FT(ir));
1624 fd = (*handler) (fr, fs, ft);
1625 DPTOREG(fd, MIPSInst_FD(ir));
1635 if (MIPSInst_FUNC(ir) != pfetch_op)
1638 /* ignore prefx operation */
1651 * Emulate a single COP1 arithmetic instruction.
1653 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1654 mips_instruction ir)
1656 int rfmt; /* resulting format */
1657 unsigned rcsr = 0; /* resulting csr */
1666 } rv; /* resulting value */
1669 MIPS_FPU_EMU_INC_STATS(cp1ops);
1670 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1671 case s_fmt: { /* 0 */
1673 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1674 union ieee754sp(*u) (union ieee754sp);
1676 union ieee754sp fs, ft;
1678 switch (MIPSInst_FUNC(ir)) {
1681 handler.b = ieee754sp_add;
1684 handler.b = ieee754sp_sub;
1687 handler.b = ieee754sp_mul;
1690 handler.b = ieee754sp_div;
1695 if (!cpu_has_mips_2_3_4_5_r)
1698 handler.u = ieee754sp_sqrt;
1702 * Note that on some MIPS IV implementations such as the
1703 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1704 * achieve full IEEE-754 accuracy - however this emulator does.
1707 if (!cpu_has_mips_4_5_64_r2_r6)
1710 handler.u = fpemu_sp_rsqrt;
1714 if (!cpu_has_mips_4_5_64_r2_r6)
1717 handler.u = fpemu_sp_recip;
1721 if (!cpu_has_mips_4_5_r)
1724 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1725 if (((ctx->fcr31 & cond) != 0) !=
1726 ((MIPSInst_FT(ir) & 1) != 0))
1728 SPFROMREG(rv.s, MIPSInst_FS(ir));
1732 if (!cpu_has_mips_4_5_r)
1735 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1737 SPFROMREG(rv.s, MIPSInst_FS(ir));
1741 if (!cpu_has_mips_4_5_r)
1744 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1746 SPFROMREG(rv.s, MIPSInst_FS(ir));
1750 if (!cpu_has_mips_r6)
1753 SPFROMREG(rv.s, MIPSInst_FT(ir));
1757 SPFROMREG(rv.s, MIPSInst_FS(ir));
1761 if (!cpu_has_mips_r6)
1764 SPFROMREG(rv.s, MIPSInst_FT(ir));
1766 SPFROMREG(rv.s, MIPSInst_FS(ir));
1772 union ieee754sp ft, fs, fd;
1774 if (!cpu_has_mips_r6)
1777 SPFROMREG(ft, MIPSInst_FT(ir));
1778 SPFROMREG(fs, MIPSInst_FS(ir));
1779 SPFROMREG(fd, MIPSInst_FD(ir));
1780 rv.s = ieee754sp_maddf(fd, fs, ft);
1785 union ieee754sp ft, fs, fd;
1787 if (!cpu_has_mips_r6)
1790 SPFROMREG(ft, MIPSInst_FT(ir));
1791 SPFROMREG(fs, MIPSInst_FS(ir));
1792 SPFROMREG(fd, MIPSInst_FD(ir));
1793 rv.s = ieee754sp_msubf(fd, fs, ft);
1800 if (!cpu_has_mips_r6)
1803 SPFROMREG(fs, MIPSInst_FS(ir));
1804 rv.l = ieee754sp_tlong(fs);
1805 rv.s = ieee754sp_flong(rv.l);
1812 if (!cpu_has_mips_r6)
1815 SPFROMREG(fs, MIPSInst_FS(ir));
1816 rv.w = ieee754sp_2008class(fs);
1822 union ieee754sp fs, ft;
1824 if (!cpu_has_mips_r6)
1827 SPFROMREG(ft, MIPSInst_FT(ir));
1828 SPFROMREG(fs, MIPSInst_FS(ir));
1829 rv.s = ieee754sp_fmin(fs, ft);
1834 union ieee754sp fs, ft;
1836 if (!cpu_has_mips_r6)
1839 SPFROMREG(ft, MIPSInst_FT(ir));
1840 SPFROMREG(fs, MIPSInst_FS(ir));
1841 rv.s = ieee754sp_fmina(fs, ft);
1846 union ieee754sp fs, ft;
1848 if (!cpu_has_mips_r6)
1851 SPFROMREG(ft, MIPSInst_FT(ir));
1852 SPFROMREG(fs, MIPSInst_FS(ir));
1853 rv.s = ieee754sp_fmax(fs, ft);
1858 union ieee754sp fs, ft;
1860 if (!cpu_has_mips_r6)
1863 SPFROMREG(ft, MIPSInst_FT(ir));
1864 SPFROMREG(fs, MIPSInst_FS(ir));
1865 rv.s = ieee754sp_fmaxa(fs, ft);
1870 handler.u = ieee754sp_abs;
1874 handler.u = ieee754sp_neg;
1879 SPFROMREG(rv.s, MIPSInst_FS(ir));
1882 /* binary op on handler */
1884 SPFROMREG(fs, MIPSInst_FS(ir));
1885 SPFROMREG(ft, MIPSInst_FT(ir));
1887 rv.s = (*handler.b) (fs, ft);
1890 SPFROMREG(fs, MIPSInst_FS(ir));
1891 rv.s = (*handler.u) (fs);
1894 if (ieee754_cxtest(IEEE754_INEXACT)) {
1895 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1896 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1898 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1899 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1900 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1902 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1903 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1904 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1906 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1907 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1908 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1910 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1911 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1912 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1916 /* unary conv ops */
1918 return SIGILL; /* not defined */
1921 SPFROMREG(fs, MIPSInst_FS(ir));
1922 rv.d = ieee754dp_fsp(fs);
1927 SPFROMREG(fs, MIPSInst_FS(ir));
1928 rv.w = ieee754sp_tint(fs);
1936 if (!cpu_has_mips_2_3_4_5_r)
1939 oldrm = ieee754_csr.rm;
1940 SPFROMREG(fs, MIPSInst_FS(ir));
1941 ieee754_csr.rm = MIPSInst_FUNC(ir);
1942 rv.w = ieee754sp_tint(fs);
1943 ieee754_csr.rm = oldrm;
1948 if (!cpu_has_mips_3_4_5_64_r2_r6)
1951 SPFROMREG(fs, MIPSInst_FS(ir));
1952 rv.l = ieee754sp_tlong(fs);
1960 if (!cpu_has_mips_3_4_5_64_r2_r6)
1963 oldrm = ieee754_csr.rm;
1964 SPFROMREG(fs, MIPSInst_FS(ir));
1965 ieee754_csr.rm = MIPSInst_FUNC(ir);
1966 rv.l = ieee754sp_tlong(fs);
1967 ieee754_csr.rm = oldrm;
1972 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1973 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1974 union ieee754sp fs, ft;
1976 SPFROMREG(fs, MIPSInst_FS(ir));
1977 SPFROMREG(ft, MIPSInst_FT(ir));
1978 rv.w = ieee754sp_cmp(fs, ft,
1979 cmptab[cmpop & 0x7], cmpop & 0x8);
1981 if ((cmpop & 0x8) && ieee754_cxtest
1982 (IEEE754_INVALID_OPERATION))
1983 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1995 union ieee754dp fs, ft;
1997 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1998 union ieee754dp(*u) (union ieee754dp);
2001 switch (MIPSInst_FUNC(ir)) {
2004 handler.b = ieee754dp_add;
2007 handler.b = ieee754dp_sub;
2010 handler.b = ieee754dp_mul;
2013 handler.b = ieee754dp_div;
2018 if (!cpu_has_mips_2_3_4_5_r)
2021 handler.u = ieee754dp_sqrt;
2024 * Note that on some MIPS IV implementations such as the
2025 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2026 * achieve full IEEE-754 accuracy - however this emulator does.
2029 if (!cpu_has_mips_4_5_64_r2_r6)
2032 handler.u = fpemu_dp_rsqrt;
2035 if (!cpu_has_mips_4_5_64_r2_r6)
2038 handler.u = fpemu_dp_recip;
2041 if (!cpu_has_mips_4_5_r)
2044 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2045 if (((ctx->fcr31 & cond) != 0) !=
2046 ((MIPSInst_FT(ir) & 1) != 0))
2048 DPFROMREG(rv.d, MIPSInst_FS(ir));
2051 if (!cpu_has_mips_4_5_r)
2054 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2056 DPFROMREG(rv.d, MIPSInst_FS(ir));
2059 if (!cpu_has_mips_4_5_r)
2062 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2064 DPFROMREG(rv.d, MIPSInst_FS(ir));
2068 if (!cpu_has_mips_r6)
2071 DPFROMREG(rv.d, MIPSInst_FT(ir));
2075 DPFROMREG(rv.d, MIPSInst_FS(ir));
2079 if (!cpu_has_mips_r6)
2082 DPFROMREG(rv.d, MIPSInst_FT(ir));
2084 DPFROMREG(rv.d, MIPSInst_FS(ir));
2090 union ieee754dp ft, fs, fd;
2092 if (!cpu_has_mips_r6)
2095 DPFROMREG(ft, MIPSInst_FT(ir));
2096 DPFROMREG(fs, MIPSInst_FS(ir));
2097 DPFROMREG(fd, MIPSInst_FD(ir));
2098 rv.d = ieee754dp_maddf(fd, fs, ft);
2103 union ieee754dp ft, fs, fd;
2105 if (!cpu_has_mips_r6)
2108 DPFROMREG(ft, MIPSInst_FT(ir));
2109 DPFROMREG(fs, MIPSInst_FS(ir));
2110 DPFROMREG(fd, MIPSInst_FD(ir));
2111 rv.d = ieee754dp_msubf(fd, fs, ft);
2118 if (!cpu_has_mips_r6)
2121 DPFROMREG(fs, MIPSInst_FS(ir));
2122 rv.l = ieee754dp_tlong(fs);
2123 rv.d = ieee754dp_flong(rv.l);
2130 if (!cpu_has_mips_r6)
2133 DPFROMREG(fs, MIPSInst_FS(ir));
2134 rv.w = ieee754dp_2008class(fs);
2140 union ieee754dp fs, ft;
2142 if (!cpu_has_mips_r6)
2145 DPFROMREG(ft, MIPSInst_FT(ir));
2146 DPFROMREG(fs, MIPSInst_FS(ir));
2147 rv.d = ieee754dp_fmin(fs, ft);
2152 union ieee754dp fs, ft;
2154 if (!cpu_has_mips_r6)
2157 DPFROMREG(ft, MIPSInst_FT(ir));
2158 DPFROMREG(fs, MIPSInst_FS(ir));
2159 rv.d = ieee754dp_fmina(fs, ft);
2164 union ieee754dp fs, ft;
2166 if (!cpu_has_mips_r6)
2169 DPFROMREG(ft, MIPSInst_FT(ir));
2170 DPFROMREG(fs, MIPSInst_FS(ir));
2171 rv.d = ieee754dp_fmax(fs, ft);
2176 union ieee754dp fs, ft;
2178 if (!cpu_has_mips_r6)
2181 DPFROMREG(ft, MIPSInst_FT(ir));
2182 DPFROMREG(fs, MIPSInst_FS(ir));
2183 rv.d = ieee754dp_fmaxa(fs, ft);
2188 handler.u = ieee754dp_abs;
2192 handler.u = ieee754dp_neg;
2197 DPFROMREG(rv.d, MIPSInst_FS(ir));
2200 /* binary op on handler */
2202 DPFROMREG(fs, MIPSInst_FS(ir));
2203 DPFROMREG(ft, MIPSInst_FT(ir));
2205 rv.d = (*handler.b) (fs, ft);
2208 DPFROMREG(fs, MIPSInst_FS(ir));
2209 rv.d = (*handler.u) (fs);
2216 DPFROMREG(fs, MIPSInst_FS(ir));
2217 rv.s = ieee754sp_fdp(fs);
2222 return SIGILL; /* not defined */
2225 DPFROMREG(fs, MIPSInst_FS(ir));
2226 rv.w = ieee754dp_tint(fs); /* wrong */
2234 if (!cpu_has_mips_2_3_4_5_r)
2237 oldrm = ieee754_csr.rm;
2238 DPFROMREG(fs, MIPSInst_FS(ir));
2239 ieee754_csr.rm = MIPSInst_FUNC(ir);
2240 rv.w = ieee754dp_tint(fs);
2241 ieee754_csr.rm = oldrm;
2246 if (!cpu_has_mips_3_4_5_64_r2_r6)
2249 DPFROMREG(fs, MIPSInst_FS(ir));
2250 rv.l = ieee754dp_tlong(fs);
2258 if (!cpu_has_mips_3_4_5_64_r2_r6)
2261 oldrm = ieee754_csr.rm;
2262 DPFROMREG(fs, MIPSInst_FS(ir));
2263 ieee754_csr.rm = MIPSInst_FUNC(ir);
2264 rv.l = ieee754dp_tlong(fs);
2265 ieee754_csr.rm = oldrm;
2270 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2271 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2272 union ieee754dp fs, ft;
2274 DPFROMREG(fs, MIPSInst_FS(ir));
2275 DPFROMREG(ft, MIPSInst_FT(ir));
2276 rv.w = ieee754dp_cmp(fs, ft,
2277 cmptab[cmpop & 0x7], cmpop & 0x8);
2282 (IEEE754_INVALID_OPERATION))
2283 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2299 switch (MIPSInst_FUNC(ir)) {
2301 /* convert word to single precision real */
2302 SPFROMREG(fs, MIPSInst_FS(ir));
2303 rv.s = ieee754sp_fint(fs.bits);
2307 /* convert word to double precision real */
2308 SPFROMREG(fs, MIPSInst_FS(ir));
2309 rv.d = ieee754dp_fint(fs.bits);
2313 /* Emulating the new CMP.condn.fmt R6 instruction */
2314 #define CMPOP_MASK 0x7
2315 #define SIGN_BIT (0x1 << 3)
2316 #define PREDICATE_BIT (0x1 << 4)
2318 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2319 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2320 union ieee754sp fs, ft;
2322 /* This is an R6 only instruction */
2323 if (!cpu_has_mips_r6 ||
2324 (MIPSInst_FUNC(ir) & 0x20))
2327 /* fmt is w_fmt for single precision so fix it */
2329 /* default to false */
2333 SPFROMREG(fs, MIPSInst_FS(ir));
2334 SPFROMREG(ft, MIPSInst_FT(ir));
2336 /* positive predicates */
2337 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2338 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2340 rv.w = -1; /* true, all 1s */
2342 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2343 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2347 /* negative predicates */
2352 if (ieee754sp_cmp(fs, ft,
2353 negative_cmptab[cmpop],
2355 rv.w = -1; /* true, all 1s */
2357 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2358 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2363 /* Reserved R6 ops */
2374 if (!cpu_has_mips_3_4_5_64_r2_r6)
2377 DIFROMREG(bits, MIPSInst_FS(ir));
2379 switch (MIPSInst_FUNC(ir)) {
2381 /* convert long to single precision real */
2382 rv.s = ieee754sp_flong(bits);
2386 /* convert long to double precision real */
2387 rv.d = ieee754dp_flong(bits);
2391 /* Emulating the new CMP.condn.fmt R6 instruction */
2392 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2393 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2394 union ieee754dp fs, ft;
2396 if (!cpu_has_mips_r6 ||
2397 (MIPSInst_FUNC(ir) & 0x20))
2400 /* fmt is l_fmt for double precision so fix it */
2402 /* default to false */
2406 DPFROMREG(fs, MIPSInst_FS(ir));
2407 DPFROMREG(ft, MIPSInst_FT(ir));
2409 /* positive predicates */
2410 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2411 if (ieee754dp_cmp(fs, ft,
2412 cmptab[cmpop], sig))
2413 rv.l = -1LL; /* true, all 1s */
2415 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2416 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2420 /* negative predicates */
2425 if (ieee754dp_cmp(fs, ft,
2426 negative_cmptab[cmpop],
2428 rv.l = -1LL; /* true, all 1s */
2430 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2431 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2436 /* Reserved R6 ops */
2448 * Update the fpu CSR register for this operation.
2449 * If an exception is required, generate a tidy SIGFPE exception,
2450 * without updating the result register.
2451 * Note: cause exception bits do not accumulate, they are rewritten
2452 * for each op; only the flag/sticky bits accumulate.
2454 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2455 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2456 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2461 * Now we can safely write the result back to the register file.
2466 if (cpu_has_mips_4_5_r)
2467 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2469 cbit = FPU_CSR_COND;
2473 ctx->fcr31 &= ~cbit;
2477 DPTOREG(rv.d, MIPSInst_FD(ir));
2480 SPTOREG(rv.s, MIPSInst_FD(ir));
2483 SITOREG(rv.w, MIPSInst_FD(ir));
2486 if (!cpu_has_mips_3_4_5_64_r2_r6)
2489 DITOREG(rv.l, MIPSInst_FD(ir));
2499 * Emulate FPU instructions.
2501 * If we use FPU hardware, then we have been typically called to handle
2502 * an unimplemented operation, such as where an operand is a NaN or
2503 * denormalized. In that case exit the emulation loop after a single
2504 * iteration so as to let hardware execute any subsequent instructions.
2506 * If we have no FPU hardware or it has been disabled, then continue
2507 * emulating floating-point instructions until one of these conditions
2510 * - a non-FPU instruction has been encountered,
2512 * - an attempt to emulate has ended with a signal,
2514 * - the ISA mode has been switched.
2516 * We need to terminate the emulation loop if we got switched to the
2517 * MIPS16 mode, whether supported or not, so that we do not attempt
2518 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2519 * Similarly if we got switched to the microMIPS mode and only the
2520 * regular MIPS mode is supported, so that we do not attempt to emulate
2521 * a microMIPS instruction as a regular MIPS FPU instruction. Or if
2522 * we got switched to the regular MIPS mode and only the microMIPS mode
2523 * is supported, so that we do not attempt to emulate a regular MIPS
2524 * instruction that should cause an Address Error exception instead.
2525 * For simplicity we always terminate upon an ISA mode switch.
2527 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2528 int has_fpu, void *__user *fault_addr)
2530 unsigned long oldepc, prevepc;
2531 struct mm_decoded_insn dec_insn;
2536 oldepc = xcp->cp0_epc;
2538 prevepc = xcp->cp0_epc;
2540 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2542 * Get next 2 microMIPS instructions and convert them
2543 * into 32-bit instructions.
2545 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2546 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2547 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2548 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2549 MIPS_FPU_EMU_INC_STATS(errors);
2554 /* Get first instruction. */
2555 if (mm_insn_16bit(*instr_ptr)) {
2556 /* Duplicate the half-word. */
2557 dec_insn.insn = (*instr_ptr << 16) |
2559 /* 16-bit instruction. */
2560 dec_insn.pc_inc = 2;
2563 dec_insn.insn = (*instr_ptr << 16) |
2565 /* 32-bit instruction. */
2566 dec_insn.pc_inc = 4;
2569 /* Get second instruction. */
2570 if (mm_insn_16bit(*instr_ptr)) {
2571 /* Duplicate the half-word. */
2572 dec_insn.next_insn = (*instr_ptr << 16) |
2574 /* 16-bit instruction. */
2575 dec_insn.next_pc_inc = 2;
2577 dec_insn.next_insn = (*instr_ptr << 16) |
2579 /* 32-bit instruction. */
2580 dec_insn.next_pc_inc = 4;
2582 dec_insn.micro_mips_mode = 1;
2584 if ((get_user(dec_insn.insn,
2585 (mips_instruction __user *) xcp->cp0_epc)) ||
2586 (get_user(dec_insn.next_insn,
2587 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2588 MIPS_FPU_EMU_INC_STATS(errors);
2591 dec_insn.pc_inc = 4;
2592 dec_insn.next_pc_inc = 4;
2593 dec_insn.micro_mips_mode = 0;
2596 if ((dec_insn.insn == 0) ||
2597 ((dec_insn.pc_inc == 2) &&
2598 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2599 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2602 * The 'ieee754_csr' is an alias of ctx->fcr31.
2603 * No need to copy ctx->fcr31 to ieee754_csr.
2605 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2613 * We have to check for the ISA bit explicitly here,
2614 * because `get_isa16_mode' may return 0 if support
2615 * for code compression has been globally disabled,
2616 * or otherwise we may produce the wrong signal or
2617 * even proceed successfully where we must not.
2619 if ((xcp->cp0_epc ^ prevepc) & 0x1)
2623 } while (xcp->cp0_epc > prevepc);
2625 /* SIGILL indicates a non-fpu instruction */
2626 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2627 /* but if EPC has advanced, then ignore it */