2 * the OHCI Virtual Support Module of AMD CS5536
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <cs5536/cs5536.h>
17 #include <cs5536/cs5536_pci.h>
19 void pci_ohci_write_reg(int reg, u32 value)
21 u32 hi = 0, lo = value;
25 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
29 hi &= ~PCI_COMMAND_MASTER;
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_OHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
54 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
57 hi = 0x40000000 | ((value & 0xff000000) >> 24);
58 lo = 0x000fffff | ((value & 0x00fff000) << 8);
59 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
62 case PCI_OHCI_INT_REG:
63 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
64 lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
65 if (value) /* enable all the usb interrupt in PIC */
66 lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
67 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
74 u32 pci_ohci_read_reg(int reg)
82 CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
85 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
86 if (hi & PCI_COMMAND_MASTER)
87 conf_data |= PCI_COMMAND_MASTER;
88 if (hi & PCI_COMMAND_MEMORY)
89 conf_data |= PCI_COMMAND_MEMORY;
92 conf_data |= PCI_STATUS_66MHZ;
93 conf_data |= PCI_STATUS_FAST_BACK;
94 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
95 if (lo & SB_PARE_ERR_FLAG)
96 conf_data |= PCI_STATUS_PARITY;
97 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
99 case PCI_CLASS_REVISION:
100 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
101 conf_data = lo & 0x000000ff;
102 conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
104 case PCI_CACHE_LINE_SIZE:
106 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
107 PCI_NORMAL_LATENCY_TIMER);
110 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
111 if (lo & SOFT_BAR_OHCI_FLAG) {
112 conf_data = CS5536_OHCI_RANGE |
113 PCI_BASE_ADDRESS_SPACE_MEMORY;
114 lo &= ~SOFT_BAR_OHCI_FLAG;
115 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
117 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
118 conf_data = lo & 0xffffff00;
119 conf_data &= ~0x0000000f; /* 32bit mem */
122 case PCI_CARDBUS_CIS:
123 conf_data = PCI_CARDBUS_CIS_POINTER;
125 case PCI_SUBSYSTEM_VENDOR_ID:
127 CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
129 case PCI_ROM_ADDRESS:
130 conf_data = PCI_EXPANSION_ROM_BAR;
132 case PCI_CAPABILITY_LIST:
133 conf_data = PCI_CAPLIST_USB_POINTER;
135 case PCI_INTERRUPT_LINE:
137 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
139 case PCI_OHCI_INT_REG:
140 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
141 if (((lo >> PIC_YSEL_LOW_USB_SHIFT) & 0xf) == CS5536_USB_INTR)