2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2011 John Crispin <john@phrozen.org>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/export.h>
23 #include <linux/spinlock.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <lantiq_soc.h>
31 #define LTQ_DMA_ID 0x08
32 #define LTQ_DMA_CTRL 0x10
33 #define LTQ_DMA_CPOLL 0x14
34 #define LTQ_DMA_CS 0x18
35 #define LTQ_DMA_CCTRL 0x1C
36 #define LTQ_DMA_CDBA 0x20
37 #define LTQ_DMA_CDLEN 0x24
38 #define LTQ_DMA_CIS 0x28
39 #define LTQ_DMA_CIE 0x2C
40 #define LTQ_DMA_PS 0x40
41 #define LTQ_DMA_PCTRL 0x44
42 #define LTQ_DMA_IRNEN 0xf4
44 #define DMA_ID_CHNR GENMASK(26, 20) /* channel number */
45 #define DMA_DESCPT BIT(3) /* descriptor complete irq */
46 #define DMA_TX BIT(8) /* TX channel direction */
47 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */
48 #define DMA_PDEN BIT(6) /* enable packet drop */
49 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */
50 #define DMA_RESET BIT(0) /* channel on / off bit */
51 #define DMA_IRQ_ACK 0x7e /* IRQ status register */
52 #define DMA_POLL BIT(31) /* turn on channel polling */
53 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
54 #define DMA_2W_BURST BIT(1) /* 2 word burst length */
55 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
56 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
58 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
59 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
60 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
61 ltq_dma_membase + (z))
63 static void __iomem *ltq_dma_membase;
64 static DEFINE_SPINLOCK(ltq_dma_lock);
67 ltq_dma_enable_irq(struct ltq_dma_channel *ch)
71 spin_lock_irqsave(<q_dma_lock, flags);
72 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
73 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
74 spin_unlock_irqrestore(<q_dma_lock, flags);
76 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
79 ltq_dma_disable_irq(struct ltq_dma_channel *ch)
83 spin_lock_irqsave(<q_dma_lock, flags);
84 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
85 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
86 spin_unlock_irqrestore(<q_dma_lock, flags);
88 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
91 ltq_dma_ack_irq(struct ltq_dma_channel *ch)
95 spin_lock_irqsave(<q_dma_lock, flags);
96 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
97 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
98 spin_unlock_irqrestore(<q_dma_lock, flags);
100 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
103 ltq_dma_open(struct ltq_dma_channel *ch)
107 spin_lock_irqsave(<q_dma_lock, flag);
108 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
109 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
110 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
111 spin_unlock_irqrestore(<q_dma_lock, flag);
113 EXPORT_SYMBOL_GPL(ltq_dma_open);
116 ltq_dma_close(struct ltq_dma_channel *ch)
120 spin_lock_irqsave(<q_dma_lock, flag);
121 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
122 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
123 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
124 spin_unlock_irqrestore(<q_dma_lock, flag);
126 EXPORT_SYMBOL_GPL(ltq_dma_close);
129 ltq_dma_alloc(struct ltq_dma_channel *ch)
134 ch->desc_base = dma_alloc_coherent(NULL,
135 LTQ_DESC_NUM * LTQ_DESC_SIZE,
136 &ch->phys, GFP_ATOMIC);
137 memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
139 spin_lock_irqsave(<q_dma_lock, flags);
140 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
141 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
142 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
143 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
145 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
146 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
148 spin_unlock_irqrestore(<q_dma_lock, flags);
152 ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
158 spin_lock_irqsave(<q_dma_lock, flags);
159 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
160 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
161 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
162 spin_unlock_irqrestore(<q_dma_lock, flags);
164 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
167 ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
173 spin_lock_irqsave(<q_dma_lock, flags);
174 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
175 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
176 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
177 spin_unlock_irqrestore(<q_dma_lock, flags);
179 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
182 ltq_dma_free(struct ltq_dma_channel *ch)
187 dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE,
188 ch->desc_base, ch->phys);
190 EXPORT_SYMBOL_GPL(ltq_dma_free);
193 ltq_dma_init_port(int p)
195 ltq_dma_w32(p, LTQ_DMA_PS);
199 * Tell the DMA engine to swap the endianness of data frames and
200 * drop packets if the channel arbitration fails.
202 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
207 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
215 EXPORT_SYMBOL_GPL(ltq_dma_init_port);
218 ltq_dma_init(struct platform_device *pdev)
221 struct resource *res;
222 unsigned int id, nchannels;
225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
227 if (IS_ERR(ltq_dma_membase))
228 panic("Failed to remap dma resource");
230 /* power up and reset the dma engine */
231 clk = clk_get(&pdev->dev, NULL);
233 panic("Failed to get dma clock");
236 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
240 /* disable all interrupts */
241 ltq_dma_w32(0, LTQ_DMA_IRNEN);
243 /* reset/configure each channel */
244 id = ltq_dma_r32(LTQ_DMA_ID);
245 nchannels = ((id & DMA_ID_CHNR) >> 20);
246 for (i = 0; i < nchannels; i++) {
247 ltq_dma_w32(i, LTQ_DMA_CS);
248 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
249 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
250 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
254 "Init done - hw rev: %X, ports: %d, channels: %d\n",
255 id & 0x1f, (id >> 16) & 0xf, nchannels);
260 static const struct of_device_id dma_match[] = {
261 { .compatible = "lantiq,dma-xway" },
265 static struct platform_driver dma_driver = {
266 .probe = ltq_dma_init,
269 .of_match_table = dma_match,
276 return platform_driver_register(&dma_driver);
279 postcore_initcall(dma_init);