arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/memblock.h>
  22
  23 #include <asm/fpu.h>
  24 #include <asm/page.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/pgtable.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33 #include "commpage.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "trace.h"
  37
  38 #ifndef VECTORSPACING
  39 #define VECTORSPACING 0x100     /* for EI/VI mode */
  40 #endif
  41
  42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  43 struct kvm_stats_debugfs_item debugfs_entries[] = {
  44         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  45         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  46         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  47         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  48         { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  49         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  50         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  51         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  52         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  53         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  54         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  55         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  56         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  57         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  58         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  59         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  60         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  61         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  62 #ifdef CONFIG_KVM_MIPS_VZ
  63         { "vz_gpsi",      VCPU_STAT(vz_gpsi_exits),      KVM_STAT_VCPU },
  64         { "vz_gsfc",      VCPU_STAT(vz_gsfc_exits),      KVM_STAT_VCPU },
  65         { "vz_hc",        VCPU_STAT(vz_hc_exits),        KVM_STAT_VCPU },
  66         { "vz_grr",       VCPU_STAT(vz_grr_exits),       KVM_STAT_VCPU },
  67         { "vz_gva",       VCPU_STAT(vz_gva_exits),       KVM_STAT_VCPU },
  68         { "vz_ghfc",      VCPU_STAT(vz_ghfc_exits),      KVM_STAT_VCPU },
  69         { "vz_gpa",       VCPU_STAT(vz_gpa_exits),       KVM_STAT_VCPU },
  70         { "vz_resvd",     VCPU_STAT(vz_resvd_exits),     KVM_STAT_VCPU },
  71 #endif
  72         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  73         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  74         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  75         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  76         {NULL}
  77 };
  78
  79 bool kvm_trace_guest_mode_change;
  80
  81 int kvm_guest_mode_change_trace_reg(void)
  82 {
  83         kvm_trace_guest_mode_change = 1;
  84         return 0;
  85 }
  86
  87 void kvm_guest_mode_change_trace_unreg(void)
  88 {
  89         kvm_trace_guest_mode_change = 0;
  90 }
  91
  92 /*
  93  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  94  * Config7, so we are "runnable" if interrupts are pending
  95  */
  96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  97 {
  98         return !!(vcpu->arch.pending_exceptions);
  99 }
 100
 101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 102 {
 103         return false;
 104 }
 105
 106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 107 {
 108         return 1;
 109 }
 110
 111 int kvm_arch_hardware_enable(void)
 112 {
 113         return kvm_mips_callbacks->hardware_enable();
 114 }
 115
 116 void kvm_arch_hardware_disable(void)
 117 {
 118         kvm_mips_callbacks->hardware_disable();
 119 }
 120
 121 int kvm_arch_hardware_setup(void)
 122 {
 123         return 0;
 124 }
 125
 126 int kvm_arch_check_processor_compat(void)
 127 {
 128         return 0;
 129 }
 130
 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 132 {
 133         switch (type) {
 134         case KVM_VM_MIPS_AUTO:
 135                 break;
 136 #ifdef CONFIG_KVM_MIPS_VZ
 137         case KVM_VM_MIPS_VZ:
 138 #else
 139         case KVM_VM_MIPS_TE:
 140 #endif
 141                 break;
 142         default:
 143                 /* Unsupported KVM type */
 144                 return -EINVAL;
 145         };
 146
 147         /* Allocate page table to map GPA -> RPA */
 148         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 149         if (!kvm->arch.gpa_mm.pgd)
 150                 return -ENOMEM;
 151
 152         return 0;
 153 }
 154
 155 void kvm_mips_free_vcpus(struct kvm *kvm)
 156 {
 157         unsigned int i;
 158         struct kvm_vcpu *vcpu;
 159
 160         kvm_for_each_vcpu(i, vcpu, kvm) {
 161                 kvm_arch_vcpu_free(vcpu);
 162         }
 163
 164         mutex_lock(&kvm->lock);
 165
 166         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 167                 kvm->vcpus[i] = NULL;
 168
 169         atomic_set(&kvm->online_vcpus, 0);
 170
 171         mutex_unlock(&kvm->lock);
 172 }
 173
 174 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 175 {
 176         /* It should always be safe to remove after flushing the whole range */
 177         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 178         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 179 }
 180
 181 void kvm_arch_destroy_vm(struct kvm *kvm)
 182 {
 183         kvm_mips_free_vcpus(kvm);
 184         kvm_mips_free_gpa_pt(kvm);
 185 }
 186
 187 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 188                         unsigned long arg)
 189 {
 190         return -ENOIOCTLCMD;
 191 }
 192
 193 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 194                             unsigned long npages)
 195 {
 196         return 0;
 197 }
 198
 199 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 200 {
 201         /* Flush whole GPA */
 202         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 203
 204         /* Let implementation do the rest */
 205         kvm_mips_callbacks->flush_shadow_all(kvm);
 206 }
 207
 208 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 209                                    struct kvm_memory_slot *slot)
 210 {
 211         /*
 212          * The slot has been made invalid (ready for moving or deletion), so we
 213          * need to ensure that it can no longer be accessed by any guest VCPUs.
 214          */
 215
 216         spin_lock(&kvm->mmu_lock);
 217         /* Flush slot from GPA */
 218         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 219                               slot->base_gfn + slot->npages - 1);
 220         /* Let implementation do the rest */
 221         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 222         spin_unlock(&kvm->mmu_lock);
 223 }
 224
 225 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 226                                    struct kvm_memory_slot *memslot,
 227                                    const struct kvm_userspace_memory_region *mem,
 228                                    enum kvm_mr_change change)
 229 {
 230         return 0;
 231 }
 232
 233 void kvm_arch_commit_memory_region(struct kvm *kvm,
 234                                    const struct kvm_userspace_memory_region *mem,
 235                                    const struct kvm_memory_slot *old,
 236                                    const struct kvm_memory_slot *new,
 237                                    enum kvm_mr_change change)
 238 {
 239         int needs_flush;
 240
 241         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 242                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 243                   mem->memory_size, mem->userspace_addr);
 244
 245         /*
 246          * If dirty page logging is enabled, write protect all pages in the slot
 247          * ready for dirty logging.
 248          *
 249          * There is no need to do this in any of the following cases:
 250          * CREATE:      No dirty mappings will already exist.
 251          * MOVE/DELETE: The old mappings will already have been cleaned up by
 252          *              kvm_arch_flush_shadow_memslot()
 253          */
 254         if (change == KVM_MR_FLAGS_ONLY &&
 255             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 256              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 257                 spin_lock(&kvm->mmu_lock);
 258                 /* Write protect GPA page table entries */
 259                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 260                                         new->base_gfn + new->npages - 1);
 261                 /* Let implementation do the rest */
 262                 if (needs_flush)
 263                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 264                 spin_unlock(&kvm->mmu_lock);
 265         }
 266 }
 267
 268 static inline void dump_handler(const char *symbol, void *start, void *end)
 269 {
 270         u32 *p;
 271
 272         pr_debug("LEAF(%s)\n", symbol);
 273
 274         pr_debug("\t.set push\n");
 275         pr_debug("\t.set noreorder\n");
 276
 277         for (p = start; p < (u32 *)end; ++p)
 278                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 279
 280         pr_debug("\t.set\tpop\n");
 281
 282         pr_debug("\tEND(%s)\n", symbol);
 283 }
 284
 285 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 286 {
 287         int err, size;
 288         void *gebase, *p, *handler, *refill_start, *refill_end;
 289         int i;
 290
 291         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 292
 293         if (!vcpu) {
 294                 err = -ENOMEM;
 295                 goto out;
 296         }
 297
 298         err = kvm_vcpu_init(vcpu, kvm, id);
 299
 300         if (err)
 301                 goto out_free_cpu;
 302
 303         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 304
 305         /*
 306          * Allocate space for host mode exception handlers that handle
 307          * guest mode exits
 308          */
 309         if (cpu_has_veic || cpu_has_vint)
 310                 size = 0x200 + VECTORSPACING * 64;
 311         else
 312                 size = 0x4000;
 313
 314         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 315
 316         if (!gebase) {
 317                 err = -ENOMEM;
 318                 goto out_uninit_cpu;
 319         }
 320         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 321                   ALIGN(size, PAGE_SIZE), gebase);
 322
 323         /*
 324          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 325          * limits us to the low 512MB of physical address space. If the memory
 326          * we allocate is out of range, just give up now.
 327          */
 328         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 329                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 330                         gebase);
 331                 err = -ENOMEM;
 332                 goto out_free_gebase;
 333         }
 334
 335         /* Save new ebase */
 336         vcpu->arch.guest_ebase = gebase;
 337
 338         /* Build guest exception vectors dynamically in unmapped memory */
 339         handler = gebase + 0x2000;
 340
 341         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 342         refill_start = gebase;
 343         if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
 344                 refill_start += 0x080;
 345         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 346
 347         /* General Exception Entry point */
 348         kvm_mips_build_exception(gebase + 0x180, handler);
 349
 350         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 351         for (i = 0; i < 8; i++) {
 352                 kvm_debug("L1 Vectored handler @ %p\n",
 353                           gebase + 0x200 + (i * VECTORSPACING));
 354                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 355                                          handler);
 356         }
 357
 358         /* General exit handler */
 359         p = handler;
 360         p = kvm_mips_build_exit(p);
 361
 362         /* Guest entry routine */
 363         vcpu->arch.vcpu_run = p;
 364         p = kvm_mips_build_vcpu_run(p);
 365
 366         /* Dump the generated code */
 367         pr_debug("#include <asm/asm.h>\n");
 368         pr_debug("#include <asm/regdef.h>\n");
 369         pr_debug("\n");
 370         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 371         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 372         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 373         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 374
 375         /* Invalidate the icache for these ranges */
 376         flush_icache_range((unsigned long)gebase,
 377                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 378
 379         /*
 380          * Allocate comm page for guest kernel, a TLB will be reserved for
 381          * mapping GVA @ 0xFFFF8000 to this page
 382          */
 383         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 384
 385         if (!vcpu->arch.kseg0_commpage) {
 386                 err = -ENOMEM;
 387                 goto out_free_gebase;
 388         }
 389
 390         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 391         kvm_mips_commpage_init(vcpu);
 392
 393         /* Init */
 394         vcpu->arch.last_sched_cpu = -1;
 395         vcpu->arch.last_exec_cpu = -1;
 396
 397         return vcpu;
 398
 399 out_free_gebase:
 400         kfree(gebase);
 401
 402 out_uninit_cpu:
 403         kvm_vcpu_uninit(vcpu);
 404
 405 out_free_cpu:
 406         kfree(vcpu);
 407
 408 out:
 409         return ERR_PTR(err);
 410 }
 411
 412 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 413 {
 414         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 415
 416         kvm_vcpu_uninit(vcpu);
 417
 418         kvm_mips_dump_stats(vcpu);
 419
 420         kvm_mmu_free_memory_caches(vcpu);
 421         kfree(vcpu->arch.guest_ebase);
 422         kfree(vcpu->arch.kseg0_commpage);
 423         kfree(vcpu);
 424 }
 425
 426 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 427 {
 428         kvm_arch_vcpu_free(vcpu);
 429 }
 430
 431 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 432                                         struct kvm_guest_debug *dbg)
 433 {
 434         return -ENOIOCTLCMD;
 435 }
 436
 437 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 438 {
 439         int r = -EINTR;
 440
 441         vcpu_load(vcpu);
 442
 443         kvm_sigset_activate(vcpu);
 444
 445         if (vcpu->mmio_needed) {
 446                 if (!vcpu->mmio_is_write)
 447                         kvm_mips_complete_mmio_load(vcpu, run);
 448                 vcpu->mmio_needed = 0;
 449         }
 450
 451         if (run->immediate_exit)
 452                 goto out;
 453
 454         lose_fpu(1);
 455
 456         local_irq_disable();
 457         guest_enter_irqoff();
 458         trace_kvm_enter(vcpu);
 459
 460         /*
 461          * Make sure the read of VCPU requests in vcpu_run() callback is not
 462          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 463          * flush request while the requester sees the VCPU as outside of guest
 464          * mode and not needing an IPI.
 465          */
 466         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 467
 468         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 469
 470         trace_kvm_out(vcpu);
 471         guest_exit_irqoff();
 472         local_irq_enable();
 473
 474 out:
 475         kvm_sigset_deactivate(vcpu);
 476
 477         vcpu_put(vcpu);
 478         return r;
 479 }
 480
 481 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 482                              struct kvm_mips_interrupt *irq)
 483 {
 484         int intr = (int)irq->irq;
 485         struct kvm_vcpu *dvcpu = NULL;
 486
 487         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 488                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 489                           (int)intr);
 490
 491         if (irq->cpu == -1)
 492                 dvcpu = vcpu;
 493         else
 494                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 495
 496         if (intr == 2 || intr == 3 || intr == 4) {
 497                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 498
 499         } else if (intr == -2 || intr == -3 || intr == -4) {
 500                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 501         } else {
 502                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 503                         irq->cpu, irq->irq);
 504                 return -EINVAL;
 505         }
 506
 507         dvcpu->arch.wait = 0;
 508
 509         if (swq_has_sleeper(&dvcpu->wq))
 510                 swake_up_one(&dvcpu->wq);
 511
 512         return 0;
 513 }
 514
 515 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 516                                     struct kvm_mp_state *mp_state)
 517 {
 518         return -ENOIOCTLCMD;
 519 }
 520
 521 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 522                                     struct kvm_mp_state *mp_state)
 523 {
 524         return -ENOIOCTLCMD;
 525 }
 526
 527 static u64 kvm_mips_get_one_regs[] = {
 528         KVM_REG_MIPS_R0,
 529         KVM_REG_MIPS_R1,
 530         KVM_REG_MIPS_R2,
 531         KVM_REG_MIPS_R3,
 532         KVM_REG_MIPS_R4,
 533         KVM_REG_MIPS_R5,
 534         KVM_REG_MIPS_R6,
 535         KVM_REG_MIPS_R7,
 536         KVM_REG_MIPS_R8,
 537         KVM_REG_MIPS_R9,
 538         KVM_REG_MIPS_R10,
 539         KVM_REG_MIPS_R11,
 540         KVM_REG_MIPS_R12,
 541         KVM_REG_MIPS_R13,
 542         KVM_REG_MIPS_R14,
 543         KVM_REG_MIPS_R15,
 544         KVM_REG_MIPS_R16,
 545         KVM_REG_MIPS_R17,
 546         KVM_REG_MIPS_R18,
 547         KVM_REG_MIPS_R19,
 548         KVM_REG_MIPS_R20,
 549         KVM_REG_MIPS_R21,
 550         KVM_REG_MIPS_R22,
 551         KVM_REG_MIPS_R23,
 552         KVM_REG_MIPS_R24,
 553         KVM_REG_MIPS_R25,
 554         KVM_REG_MIPS_R26,
 555         KVM_REG_MIPS_R27,
 556         KVM_REG_MIPS_R28,
 557         KVM_REG_MIPS_R29,
 558         KVM_REG_MIPS_R30,
 559         KVM_REG_MIPS_R31,
 560
 561 #ifndef CONFIG_CPU_MIPSR6
 562         KVM_REG_MIPS_HI,
 563         KVM_REG_MIPS_LO,
 564 #endif
 565         KVM_REG_MIPS_PC,
 566 };
 567
 568 static u64 kvm_mips_get_one_regs_fpu[] = {
 569         KVM_REG_MIPS_FCR_IR,
 570         KVM_REG_MIPS_FCR_CSR,
 571 };
 572
 573 static u64 kvm_mips_get_one_regs_msa[] = {
 574         KVM_REG_MIPS_MSA_IR,
 575         KVM_REG_MIPS_MSA_CSR,
 576 };
 577
 578 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 579 {
 580         unsigned long ret;
 581
 582         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 583         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 584                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 585                 /* odd doubles */
 586                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 587                         ret += 16;
 588         }
 589         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 590                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 591         ret += kvm_mips_callbacks->num_regs(vcpu);
 592
 593         return ret;
 594 }
 595
 596 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 597 {
 598         u64 index;
 599         unsigned int i;
 600
 601         if (copy_to_user(indices, kvm_mips_get_one_regs,
 602                          sizeof(kvm_mips_get_one_regs)))
 603                 return -EFAULT;
 604         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 605
 606         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 607                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 608                                  sizeof(kvm_mips_get_one_regs_fpu)))
 609                         return -EFAULT;
 610                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 611
 612                 for (i = 0; i < 32; ++i) {
 613                         index = KVM_REG_MIPS_FPR_32(i);
 614                         if (copy_to_user(indices, &index, sizeof(index)))
 615                                 return -EFAULT;
 616                         ++indices;
 617
 618                         /* skip odd doubles if no F64 */
 619                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 620                                 continue;
 621
 622                         index = KVM_REG_MIPS_FPR_64(i);
 623                         if (copy_to_user(indices, &index, sizeof(index)))
 624                                 return -EFAULT;
 625                         ++indices;
 626                 }
 627         }
 628
 629         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 630                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 631                                  sizeof(kvm_mips_get_one_regs_msa)))
 632                         return -EFAULT;
 633                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 634
 635                 for (i = 0; i < 32; ++i) {
 636                         index = KVM_REG_MIPS_VEC_128(i);
 637                         if (copy_to_user(indices, &index, sizeof(index)))
 638                                 return -EFAULT;
 639                         ++indices;
 640                 }
 641         }
 642
 643         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 644 }
 645
 646 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 647                             const struct kvm_one_reg *reg)
 648 {
 649         struct mips_coproc *cop0 = vcpu->arch.cop0;
 650         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 651         int ret;
 652         s64 v;
 653         s64 vs[2];
 654         unsigned int idx;
 655
 656         switch (reg->id) {
 657         /* General purpose registers */
 658         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 659                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 660                 break;
 661 #ifndef CONFIG_CPU_MIPSR6
 662         case KVM_REG_MIPS_HI:
 663                 v = (long)vcpu->arch.hi;
 664                 break;
 665         case KVM_REG_MIPS_LO:
 666                 v = (long)vcpu->arch.lo;
 667                 break;
 668 #endif
 669         case KVM_REG_MIPS_PC:
 670                 v = (long)vcpu->arch.pc;
 671                 break;
 672
 673         /* Floating point registers */
 674         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 675                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 676                         return -EINVAL;
 677                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 678                 /* Odd singles in top of even double when FR=0 */
 679                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 680                         v = get_fpr32(&fpu->fpr[idx], 0);
 681                 else
 682                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 683                 break;
 684         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 685                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 686                         return -EINVAL;
 687                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 688                 /* Can't access odd doubles in FR=0 mode */
 689                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 690                         return -EINVAL;
 691                 v = get_fpr64(&fpu->fpr[idx], 0);
 692                 break;
 693         case KVM_REG_MIPS_FCR_IR:
 694                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 695                         return -EINVAL;
 696                 v = boot_cpu_data.fpu_id;
 697                 break;
 698         case KVM_REG_MIPS_FCR_CSR:
 699                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 700                         return -EINVAL;
 701                 v = fpu->fcr31;
 702                 break;
 703
 704         /* MIPS SIMD Architecture (MSA) registers */
 705         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 706                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 707                         return -EINVAL;
 708                 /* Can't access MSA registers in FR=0 mode */
 709                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 710                         return -EINVAL;
 711                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 712 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 713                 /* least significant byte first */
 714                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 715                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 716 #else
 717                 /* most significant byte first */
 718                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 719                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 720 #endif
 721                 break;
 722         case KVM_REG_MIPS_MSA_IR:
 723                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 724                         return -EINVAL;
 725                 v = boot_cpu_data.msa_id;
 726                 break;
 727         case KVM_REG_MIPS_MSA_CSR:
 728                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 729                         return -EINVAL;
 730                 v = fpu->msacsr;
 731                 break;
 732
 733         /* registers to be handled specially */
 734         default:
 735                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 736                 if (ret)
 737                         return ret;
 738                 break;
 739         }
 740         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 741                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 742
 743                 return put_user(v, uaddr64);
 744         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 745                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 746                 u32 v32 = (u32)v;
 747
 748                 return put_user(v32, uaddr32);
 749         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 750                 void __user *uaddr = (void __user *)(long)reg->addr;
 751
 752                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 753         } else {
 754                 return -EINVAL;
 755         }
 756 }
 757
 758 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 759                             const struct kvm_one_reg *reg)
 760 {
 761         struct mips_coproc *cop0 = vcpu->arch.cop0;
 762         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 763         s64 v;
 764         s64 vs[2];
 765         unsigned int idx;
 766
 767         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 768                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 769
 770                 if (get_user(v, uaddr64) != 0)
 771                         return -EFAULT;
 772         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 773                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 774                 s32 v32;
 775
 776                 if (get_user(v32, uaddr32) != 0)
 777                         return -EFAULT;
 778                 v = (s64)v32;
 779         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 780                 void __user *uaddr = (void __user *)(long)reg->addr;
 781
 782                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 783         } else {
 784                 return -EINVAL;
 785         }
 786
 787         switch (reg->id) {
 788         /* General purpose registers */
 789         case KVM_REG_MIPS_R0:
 790                 /* Silently ignore requests to set $0 */
 791                 break;
 792         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 793                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 794                 break;
 795 #ifndef CONFIG_CPU_MIPSR6
 796         case KVM_REG_MIPS_HI:
 797                 vcpu->arch.hi = v;
 798                 break;
 799         case KVM_REG_MIPS_LO:
 800                 vcpu->arch.lo = v;
 801                 break;
 802 #endif
 803         case KVM_REG_MIPS_PC:
 804                 vcpu->arch.pc = v;
 805                 break;
 806
 807         /* Floating point registers */
 808         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 809                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 810                         return -EINVAL;
 811                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 812                 /* Odd singles in top of even double when FR=0 */
 813                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 814                         set_fpr32(&fpu->fpr[idx], 0, v);
 815                 else
 816                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 817                 break;
 818         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 819                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 820                         return -EINVAL;
 821                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 822                 /* Can't access odd doubles in FR=0 mode */
 823                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 824                         return -EINVAL;
 825                 set_fpr64(&fpu->fpr[idx], 0, v);
 826                 break;
 827         case KVM_REG_MIPS_FCR_IR:
 828                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 829                         return -EINVAL;
 830                 /* Read-only */
 831                 break;
 832         case KVM_REG_MIPS_FCR_CSR:
 833                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 834                         return -EINVAL;
 835                 fpu->fcr31 = v;
 836                 break;
 837
 838         /* MIPS SIMD Architecture (MSA) registers */
 839         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 840                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 841                         return -EINVAL;
 842                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 843 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 844                 /* least significant byte first */
 845                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 846                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 847 #else
 848                 /* most significant byte first */
 849                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 850                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 851 #endif
 852                 break;
 853         case KVM_REG_MIPS_MSA_IR:
 854                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 855                         return -EINVAL;
 856                 /* Read-only */
 857                 break;
 858         case KVM_REG_MIPS_MSA_CSR:
 859                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 860                         return -EINVAL;
 861                 fpu->msacsr = v;
 862                 break;
 863
 864         /* registers to be handled specially */
 865         default:
 866                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 867         }
 868         return 0;
 869 }
 870
 871 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 872                                      struct kvm_enable_cap *cap)
 873 {
 874         int r = 0;
 875
 876         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 877                 return -EINVAL;
 878         if (cap->flags)
 879                 return -EINVAL;
 880         if (cap->args[0])
 881                 return -EINVAL;
 882
 883         switch (cap->cap) {
 884         case KVM_CAP_MIPS_FPU:
 885                 vcpu->arch.fpu_enabled = true;
 886                 break;
 887         case KVM_CAP_MIPS_MSA:
 888                 vcpu->arch.msa_enabled = true;
 889                 break;
 890         default:
 891                 r = -EINVAL;
 892                 break;
 893         }
 894
 895         return r;
 896 }
 897
 898 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
 899                                unsigned long arg)
 900 {
 901         struct kvm_vcpu *vcpu = filp->private_data;
 902         void __user *argp = (void __user *)arg;
 903
 904         if (ioctl == KVM_INTERRUPT) {
 905                 struct kvm_mips_interrupt irq;
 906
 907                 if (copy_from_user(&irq, argp, sizeof(irq)))
 908                         return -EFAULT;
 909                 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 910                           irq.irq);
 911
 912                 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 913         }
 914
 915         return -ENOIOCTLCMD;
 916 }
 917
 918 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 919                          unsigned long arg)
 920 {
 921         struct kvm_vcpu *vcpu = filp->private_data;
 922         void __user *argp = (void __user *)arg;
 923         long r;
 924
 925         vcpu_load(vcpu);
 926
 927         switch (ioctl) {
 928         case KVM_SET_ONE_REG:
 929         case KVM_GET_ONE_REG: {
 930                 struct kvm_one_reg reg;
 931
 932                 r = -EFAULT;
 933                 if (copy_from_user(&reg, argp, sizeof(reg)))
 934                         break;
 935                 if (ioctl == KVM_SET_ONE_REG)
 936                         r = kvm_mips_set_reg(vcpu, &reg);
 937                 else
 938                         r = kvm_mips_get_reg(vcpu, &reg);
 939                 break;
 940         }
 941         case KVM_GET_REG_LIST: {
 942                 struct kvm_reg_list __user *user_list = argp;
 943                 struct kvm_reg_list reg_list;
 944                 unsigned n;
 945
 946                 r = -EFAULT;
 947                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 948                         break;
 949                 n = reg_list.n;
 950                 reg_list.n = kvm_mips_num_regs(vcpu);
 951                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 952                         break;
 953                 r = -E2BIG;
 954                 if (n < reg_list.n)
 955                         break;
 956                 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 957                 break;
 958         }
 959         case KVM_ENABLE_CAP: {
 960                 struct kvm_enable_cap cap;
 961
 962                 r = -EFAULT;
 963                 if (copy_from_user(&cap, argp, sizeof(cap)))
 964                         break;
 965                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 966                 break;
 967         }
 968         default:
 969                 r = -ENOIOCTLCMD;
 970         }
 971
 972         vcpu_put(vcpu);
 973         return r;
 974 }
 975
 976 /**
 977  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
 978  * @kvm: kvm instance
 979  * @log: slot id and address to which we copy the log
 980  *
 981  * Steps 1-4 below provide general overview of dirty page logging. See
 982  * kvm_get_dirty_log_protect() function description for additional details.
 983  *
 984  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
 985  * always flush the TLB (step 4) even if previous step failed  and the dirty
 986  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
 987  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
 988  * writes will be marked dirty for next log read.
 989  *
 990  *   1. Take a snapshot of the bit and clear it if needed.
 991  *   2. Write protect the corresponding page.
 992  *   3. Copy the snapshot to the userspace.
 993  *   4. Flush TLB's if needed.
 994  */
 995 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 996 {
 997         struct kvm_memslots *slots;
 998         struct kvm_memory_slot *memslot;
 999         bool flush = false;
1000         int r;
1001
1002         mutex_lock(&kvm->slots_lock);
1003
1004         r = kvm_get_dirty_log_protect(kvm, log, &flush);
1005
1006         if (flush) {
1007                 slots = kvm_memslots(kvm);
1008                 memslot = id_to_memslot(slots, log->slot);
1009
1010                 /* Let implementation handle TLB/GVA invalidation */
1011                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1012         }
1013
1014         mutex_unlock(&kvm->slots_lock);
1015         return r;
1016 }
1017
1018 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
1019 {
1020         struct kvm_memslots *slots;
1021         struct kvm_memory_slot *memslot;
1022         bool flush = false;
1023         int r;
1024
1025         mutex_lock(&kvm->slots_lock);
1026
1027         r = kvm_clear_dirty_log_protect(kvm, log, &flush);
1028
1029         if (flush) {
1030                 slots = kvm_memslots(kvm);
1031                 memslot = id_to_memslot(slots, log->slot);
1032
1033                 /* Let implementation handle TLB/GVA invalidation */
1034                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1035         }
1036
1037         mutex_unlock(&kvm->slots_lock);
1038         return r;
1039 }
1040
1041 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1042 {
1043         long r;
1044
1045         switch (ioctl) {
1046         default:
1047                 r = -ENOIOCTLCMD;
1048         }
1049
1050         return r;
1051 }
1052
1053 int kvm_arch_init(void *opaque)
1054 {
1055         if (kvm_mips_callbacks) {
1056                 kvm_err("kvm: module already exists\n");
1057                 return -EEXIST;
1058         }
1059
1060         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1061 }
1062
1063 void kvm_arch_exit(void)
1064 {
1065         kvm_mips_callbacks = NULL;
1066 }
1067
1068 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1069                                   struct kvm_sregs *sregs)
1070 {
1071         return -ENOIOCTLCMD;
1072 }
1073
1074 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1075                                   struct kvm_sregs *sregs)
1076 {
1077         return -ENOIOCTLCMD;
1078 }
1079
1080 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1081 {
1082 }
1083
1084 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1085 {
1086         return -ENOIOCTLCMD;
1087 }
1088
1089 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1090 {
1091         return -ENOIOCTLCMD;
1092 }
1093
1094 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1095 {
1096         return VM_FAULT_SIGBUS;
1097 }
1098
1099 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1100 {
1101         int r;
1102
1103         switch (ext) {
1104         case KVM_CAP_ONE_REG:
1105         case KVM_CAP_ENABLE_CAP:
1106         case KVM_CAP_READONLY_MEM:
1107         case KVM_CAP_SYNC_MMU:
1108         case KVM_CAP_IMMEDIATE_EXIT:
1109                 r = 1;
1110                 break;
1111         case KVM_CAP_NR_VCPUS:
1112                 r = num_online_cpus();
1113                 break;
1114         case KVM_CAP_MAX_VCPUS:
1115                 r = KVM_MAX_VCPUS;
1116                 break;
1117         case KVM_CAP_MAX_VCPU_ID:
1118                 r = KVM_MAX_VCPU_ID;
1119                 break;
1120         case KVM_CAP_MIPS_FPU:
1121                 /* We don't handle systems with inconsistent cpu_has_fpu */
1122                 r = !!raw_cpu_has_fpu;
1123                 break;
1124         case KVM_CAP_MIPS_MSA:
1125                 /*
1126                  * We don't support MSA vector partitioning yet:
1127                  * 1) It would require explicit support which can't be tested
1128                  *    yet due to lack of support in current hardware.
1129                  * 2) It extends the state that would need to be saved/restored
1130                  *    by e.g. QEMU for migration.
1131                  *
1132                  * When vector partitioning hardware becomes available, support
1133                  * could be added by requiring a flag when enabling
1134                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1135                  * to save/restore the appropriate extra state.
1136                  */
1137                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1138                 break;
1139         default:
1140                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1141                 break;
1142         }
1143         return r;
1144 }
1145
1146 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1147 {
1148         return kvm_mips_pending_timer(vcpu) ||
1149                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1150 }
1151
1152 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1153 {
1154         int i;
1155         struct mips_coproc *cop0;
1156
1157         if (!vcpu)
1158                 return -1;
1159
1160         kvm_debug("VCPU Register Dump:\n");
1161         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1162         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1163
1164         for (i = 0; i < 32; i += 4) {
1165                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1166                        vcpu->arch.gprs[i],
1167                        vcpu->arch.gprs[i + 1],
1168                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1169         }
1170         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1171         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1172
1173         cop0 = vcpu->arch.cop0;
1174         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1175                   kvm_read_c0_guest_status(cop0),
1176                   kvm_read_c0_guest_cause(cop0));
1177
1178         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1179
1180         return 0;
1181 }
1182
1183 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1184 {
1185         int i;
1186
1187         vcpu_load(vcpu);
1188
1189         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1190                 vcpu->arch.gprs[i] = regs->gpr[i];
1191         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1192         vcpu->arch.hi = regs->hi;
1193         vcpu->arch.lo = regs->lo;
1194         vcpu->arch.pc = regs->pc;
1195
1196         vcpu_put(vcpu);
1197         return 0;
1198 }
1199
1200 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1201 {
1202         int i;
1203
1204         vcpu_load(vcpu);
1205
1206         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1207                 regs->gpr[i] = vcpu->arch.gprs[i];
1208
1209         regs->hi = vcpu->arch.hi;
1210         regs->lo = vcpu->arch.lo;
1211         regs->pc = vcpu->arch.pc;
1212
1213         vcpu_put(vcpu);
1214         return 0;
1215 }
1216
1217 static void kvm_mips_comparecount_func(unsigned long data)
1218 {
1219         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1220
1221         kvm_mips_callbacks->queue_timer_int(vcpu);
1222
1223         vcpu->arch.wait = 0;
1224         if (swq_has_sleeper(&vcpu->wq))
1225                 swake_up_one(&vcpu->wq);
1226 }
1227
1228 /* low level hrtimer wake routine */
1229 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1230 {
1231         struct kvm_vcpu *vcpu;
1232
1233         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1234         kvm_mips_comparecount_func((unsigned long) vcpu);
1235         return kvm_mips_count_timeout(vcpu);
1236 }
1237
1238 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1239 {
1240         int err;
1241
1242         err = kvm_mips_callbacks->vcpu_init(vcpu);
1243         if (err)
1244                 return err;
1245
1246         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1247                      HRTIMER_MODE_REL);
1248         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1249         return 0;
1250 }
1251
1252 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1253 {
1254         kvm_mips_callbacks->vcpu_uninit(vcpu);
1255 }
1256
1257 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1258                                   struct kvm_translation *tr)
1259 {
1260         return 0;
1261 }
1262
1263 /* Initial guest state */
1264 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1265 {
1266         return kvm_mips_callbacks->vcpu_setup(vcpu);
1267 }
1268
1269 static void kvm_mips_set_c0_status(void)
1270 {
1271         u32 status = read_c0_status();
1272
1273         if (cpu_has_dsp)
1274                 status |= (ST0_MX);
1275
1276         write_c0_status(status);
1277         ehb();
1278 }
1279
1280 /*
1281  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1282  */
1283 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1284 {
1285         u32 cause = vcpu->arch.host_cp0_cause;
1286         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1287         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1288         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1289         enum emulation_result er = EMULATE_DONE;
1290         u32 inst;
1291         int ret = RESUME_GUEST;
1292
1293         vcpu->mode = OUTSIDE_GUEST_MODE;
1294
1295         /* re-enable HTW before enabling interrupts */
1296         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1297                 htw_start();
1298
1299         /* Set a default exit reason */
1300         run->exit_reason = KVM_EXIT_UNKNOWN;
1301         run->ready_for_interrupt_injection = 1;
1302
1303         /*
1304          * Set the appropriate status bits based on host CPU features,
1305          * before we hit the scheduler
1306          */
1307         kvm_mips_set_c0_status();
1308
1309         local_irq_enable();
1310
1311         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1312                         cause, opc, run, vcpu);
1313         trace_kvm_exit(vcpu, exccode);
1314
1315         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1316                 /*
1317                  * Do a privilege check, if in UM most of these exit conditions
1318                  * end up causing an exception to be delivered to the Guest
1319                  * Kernel
1320                  */
1321                 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1322                 if (er == EMULATE_PRIV_FAIL) {
1323                         goto skip_emul;
1324                 } else if (er == EMULATE_FAIL) {
1325                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1326                         ret = RESUME_HOST;
1327                         goto skip_emul;
1328                 }
1329         }
1330
1331         switch (exccode) {
1332         case EXCCODE_INT:
1333                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1334
1335                 ++vcpu->stat.int_exits;
1336
1337                 if (need_resched())
1338                         cond_resched();
1339
1340                 ret = RESUME_GUEST;
1341                 break;
1342
1343         case EXCCODE_CPU:
1344                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1345
1346                 ++vcpu->stat.cop_unusable_exits;
1347                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1348                 /* XXXKYMA: Might need to return to user space */
1349                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1350                         ret = RESUME_HOST;
1351                 break;
1352
1353         case EXCCODE_MOD:
1354                 ++vcpu->stat.tlbmod_exits;
1355                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1356                 break;
1357
1358         case EXCCODE_TLBS:
1359                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1360                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1361                           badvaddr);
1362
1363                 ++vcpu->stat.tlbmiss_st_exits;
1364                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1365                 break;
1366
1367         case EXCCODE_TLBL:
1368                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1369                           cause, opc, badvaddr);
1370
1371                 ++vcpu->stat.tlbmiss_ld_exits;
1372                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1373                 break;
1374
1375         case EXCCODE_ADES:
1376                 ++vcpu->stat.addrerr_st_exits;
1377                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1378                 break;
1379
1380         case EXCCODE_ADEL:
1381                 ++vcpu->stat.addrerr_ld_exits;
1382                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1383                 break;
1384
1385         case EXCCODE_SYS:
1386                 ++vcpu->stat.syscall_exits;
1387                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1388                 break;
1389
1390         case EXCCODE_RI:
1391                 ++vcpu->stat.resvd_inst_exits;
1392                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1393                 break;
1394
1395         case EXCCODE_BP:
1396                 ++vcpu->stat.break_inst_exits;
1397                 ret = kvm_mips_callbacks->handle_break(vcpu);
1398                 break;
1399
1400         case EXCCODE_TR:
1401                 ++vcpu->stat.trap_inst_exits;
1402                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1403                 break;
1404
1405         case EXCCODE_MSAFPE:
1406                 ++vcpu->stat.msa_fpe_exits;
1407                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1408                 break;
1409
1410         case EXCCODE_FPE:
1411                 ++vcpu->stat.fpe_exits;
1412                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1413                 break;
1414
1415         case EXCCODE_MSADIS:
1416                 ++vcpu->stat.msa_disabled_exits;
1417                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1418                 break;
1419
1420         case EXCCODE_GE:
1421                 /* defer exit accounting to handler */
1422                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1423                 break;
1424
1425         default:
1426                 if (cause & CAUSEF_BD)
1427                         opc += 1;
1428                 inst = 0;
1429                 kvm_get_badinstr(opc, vcpu, &inst);
1430                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1431                         exccode, opc, inst, badvaddr,
1432                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1433                 kvm_arch_vcpu_dump_regs(vcpu);
1434                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1435                 ret = RESUME_HOST;
1436                 break;
1437
1438         }
1439
1440 skip_emul:
1441         local_irq_disable();
1442
1443         if (ret == RESUME_GUEST)
1444                 kvm_vz_acquire_htimer(vcpu);
1445
1446         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1447                 kvm_mips_deliver_interrupts(vcpu, cause);
1448
1449         if (!(ret & RESUME_HOST)) {
1450                 /* Only check for signals if not already exiting to userspace */
1451                 if (signal_pending(current)) {
1452                         run->exit_reason = KVM_EXIT_INTR;
1453                         ret = (-EINTR << 2) | RESUME_HOST;
1454                         ++vcpu->stat.signal_exits;
1455                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1456                 }
1457         }
1458
1459         if (ret == RESUME_GUEST) {
1460                 trace_kvm_reenter(vcpu);
1461
1462                 /*
1463                  * Make sure the read of VCPU requests in vcpu_reenter()
1464                  * callback is not reordered ahead of the write to vcpu->mode,
1465                  * or we could miss a TLB flush request while the requester sees
1466                  * the VCPU as outside of guest mode and not needing an IPI.
1467                  */
1468                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1469
1470                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1471
1472                 /*
1473                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1474                  * is live), restore FCR31 / MSACSR.
1475                  *
1476                  * This should be before returning to the guest exception
1477                  * vector, as it may well cause an [MSA] FP exception if there
1478                  * are pending exception bits unmasked. (see
1479                  * kvm_mips_csr_die_notifier() for how that is handled).
1480                  */
1481                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1482                     read_c0_status() & ST0_CU1)
1483                         __kvm_restore_fcsr(&vcpu->arch);
1484
1485                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1486                     read_c0_config5() & MIPS_CONF5_MSAEN)
1487                         __kvm_restore_msacsr(&vcpu->arch);
1488         }
1489
1490         /* Disable HTW before returning to guest or host */
1491         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1492                 htw_stop();
1493
1494         return ret;
1495 }
1496
1497 /* Enable FPU for guest and restore context */
1498 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1499 {
1500         struct mips_coproc *cop0 = vcpu->arch.cop0;
1501         unsigned int sr, cfg5;
1502
1503         preempt_disable();
1504
1505         sr = kvm_read_c0_guest_status(cop0);
1506
1507         /*
1508          * If MSA state is already live, it is undefined how it interacts with
1509          * FR=0 FPU state, and we don't want to hit reserved instruction
1510          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1511          * play it safe and save it first.
1512          *
1513          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1514          * get called when guest CU1 is set, however we can't trust the guest
1515          * not to clobber the status register directly via the commpage.
1516          */
1517         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1518             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1519                 kvm_lose_fpu(vcpu);
1520
1521         /*
1522          * Enable FPU for guest
1523          * We set FR and FRE according to guest context
1524          */
1525         change_c0_status(ST0_CU1 | ST0_FR, sr);
1526         if (cpu_has_fre) {
1527                 cfg5 = kvm_read_c0_guest_config5(cop0);
1528                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1529         }
1530         enable_fpu_hazard();
1531
1532         /* If guest FPU state not active, restore it now */
1533         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1534                 __kvm_restore_fpu(&vcpu->arch);
1535                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1536                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1537         } else {
1538                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1539         }
1540
1541         preempt_enable();
1542 }
1543
1544 #ifdef CONFIG_CPU_HAS_MSA
1545 /* Enable MSA for guest and restore context */
1546 void kvm_own_msa(struct kvm_vcpu *vcpu)
1547 {
1548         struct mips_coproc *cop0 = vcpu->arch.cop0;
1549         unsigned int sr, cfg5;
1550
1551         preempt_disable();
1552
1553         /*
1554          * Enable FPU if enabled in guest, since we're restoring FPU context
1555          * anyway. We set FR and FRE according to guest context.
1556          */
1557         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1558                 sr = kvm_read_c0_guest_status(cop0);
1559
1560                 /*
1561                  * If FR=0 FPU state is already live, it is undefined how it
1562                  * interacts with MSA state, so play it safe and save it first.
1563                  */
1564                 if (!(sr & ST0_FR) &&
1565                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1566                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1567                         kvm_lose_fpu(vcpu);
1568
1569                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1570                 if (sr & ST0_CU1 && cpu_has_fre) {
1571                         cfg5 = kvm_read_c0_guest_config5(cop0);
1572                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1573                 }
1574         }
1575
1576         /* Enable MSA for guest */
1577         set_c0_config5(MIPS_CONF5_MSAEN);
1578         enable_fpu_hazard();
1579
1580         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1581         case KVM_MIPS_AUX_FPU:
1582                 /*
1583                  * Guest FPU state already loaded, only restore upper MSA state
1584                  */
1585                 __kvm_restore_msa_upper(&vcpu->arch);
1586                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1587                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1588                 break;
1589         case 0:
1590                 /* Neither FPU or MSA already active, restore full MSA state */
1591                 __kvm_restore_msa(&vcpu->arch);
1592                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1593                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1594                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1595                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1596                               KVM_TRACE_AUX_FPU_MSA);
1597                 break;
1598         default:
1599                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1600                 break;
1601         }
1602
1603         preempt_enable();
1604 }
1605 #endif
1606
1607 /* Drop FPU & MSA without saving it */
1608 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1609 {
1610         preempt_disable();
1611         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1612                 disable_msa();
1613                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1614                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1615         }
1616         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1617                 clear_c0_status(ST0_CU1 | ST0_FR);
1618                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1619                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1620         }
1621         preempt_enable();
1622 }
1623
1624 /* Save and disable FPU & MSA */
1625 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1626 {
1627         /*
1628          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1629          * is disabled in guest context (software), but the register state in
1630          * the hardware may still be in use.
1631          * This is why we explicitly re-enable the hardware before saving.
1632          */
1633
1634         preempt_disable();
1635         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1636                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1637                         set_c0_config5(MIPS_CONF5_MSAEN);
1638                         enable_fpu_hazard();
1639                 }
1640
1641                 __kvm_save_msa(&vcpu->arch);
1642                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1643
1644                 /* Disable MSA & FPU */
1645                 disable_msa();
1646                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1647                         clear_c0_status(ST0_CU1 | ST0_FR);
1648                         disable_fpu_hazard();
1649                 }
1650                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1651         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1652                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1653                         set_c0_status(ST0_CU1);
1654                         enable_fpu_hazard();
1655                 }
1656
1657                 __kvm_save_fpu(&vcpu->arch);
1658                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1659                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1660
1661                 /* Disable FPU */
1662                 clear_c0_status(ST0_CU1 | ST0_FR);
1663                 disable_fpu_hazard();
1664         }
1665         preempt_enable();
1666 }
1667
1668 /*
1669  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1670  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1671  * exception if cause bits are set in the value being written.
1672  */
1673 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1674                                    unsigned long cmd, void *ptr)
1675 {
1676         struct die_args *args = (struct die_args *)ptr;
1677         struct pt_regs *regs = args->regs;
1678         unsigned long pc;
1679
1680         /* Only interested in FPE and MSAFPE */
1681         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1682                 return NOTIFY_DONE;
1683
1684         /* Return immediately if guest context isn't active */
1685         if (!(current->flags & PF_VCPU))
1686                 return NOTIFY_DONE;
1687
1688         /* Should never get here from user mode */
1689         BUG_ON(user_mode(regs));
1690
1691         pc = instruction_pointer(regs);
1692         switch (cmd) {
1693         case DIE_FP:
1694                 /* match 2nd instruction in __kvm_restore_fcsr */
1695                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1696                         return NOTIFY_DONE;
1697                 break;
1698         case DIE_MSAFP:
1699                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1700                 if (!cpu_has_msa ||
1701                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1702                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1703                         return NOTIFY_DONE;
1704                 break;
1705         }
1706
1707         /* Move PC forward a little and continue executing */
1708         instruction_pointer(regs) += 4;
1709
1710         return NOTIFY_STOP;
1711 }
1712
1713 static struct notifier_block kvm_mips_csr_die_notifier = {
1714         .notifier_call = kvm_mips_csr_die_notify,
1715 };
1716
1717 static int __init kvm_mips_init(void)
1718 {
1719         int ret;
1720
1721         if (cpu_has_mmid) {
1722                 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1723                 return -EOPNOTSUPP;
1724         }
1725
1726         ret = kvm_mips_entry_setup();
1727         if (ret)
1728                 return ret;
1729
1730         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1731
1732         if (ret)
1733                 return ret;
1734
1735         register_die_notifier(&kvm_mips_csr_die_notifier);
1736
1737         return 0;
1738 }
1739
1740 static void __exit kvm_mips_exit(void)
1741 {
1742         kvm_exit();
1743
1744         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1745 }
1746
1747 module_init(kvm_mips_init);
1748 module_exit(kvm_mips_exit);
1749
1750 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);