2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
21 #include <linux/bootmem.h>
25 #include <asm/cacheflush.h>
26 #include <asm/mmu_context.h>
27 #include <asm/pgalloc.h>
28 #include <asm/pgtable.h>
30 #include <linux/kvm_host.h>
32 #include "interrupt.h"
35 #define CREATE_TRACE_POINTS
39 #define VECTORSPACING 0x100 /* for EI/VI mode */
42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
43 struct kvm_stats_debugfs_item debugfs_entries[] = {
44 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
45 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
46 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
47 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
48 { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
49 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
52 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
54 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
55 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
56 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
57 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
58 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
59 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
60 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
61 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
62 #ifdef CONFIG_KVM_MIPS_VZ
63 { "vz_gpsi", VCPU_STAT(vz_gpsi_exits), KVM_STAT_VCPU },
64 { "vz_gsfc", VCPU_STAT(vz_gsfc_exits), KVM_STAT_VCPU },
65 { "vz_hc", VCPU_STAT(vz_hc_exits), KVM_STAT_VCPU },
66 { "vz_grr", VCPU_STAT(vz_grr_exits), KVM_STAT_VCPU },
67 { "vz_gva", VCPU_STAT(vz_gva_exits), KVM_STAT_VCPU },
68 { "vz_ghfc", VCPU_STAT(vz_ghfc_exits), KVM_STAT_VCPU },
69 { "vz_gpa", VCPU_STAT(vz_gpa_exits), KVM_STAT_VCPU },
70 { "vz_resvd", VCPU_STAT(vz_resvd_exits), KVM_STAT_VCPU },
72 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
73 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
74 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
75 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
79 bool kvm_trace_guest_mode_change;
81 int kvm_guest_mode_change_trace_reg(void)
83 kvm_trace_guest_mode_change = 1;
87 void kvm_guest_mode_change_trace_unreg(void)
89 kvm_trace_guest_mode_change = 0;
93 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
94 * Config7, so we are "runnable" if interrupts are pending
96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
98 return !!(vcpu->arch.pending_exceptions);
101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
111 int kvm_arch_hardware_enable(void)
113 return kvm_mips_callbacks->hardware_enable();
116 void kvm_arch_hardware_disable(void)
118 kvm_mips_callbacks->hardware_disable();
121 int kvm_arch_hardware_setup(void)
126 void kvm_arch_check_processor_compat(void *rtn)
131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
134 case KVM_VM_MIPS_AUTO:
136 #ifdef CONFIG_KVM_MIPS_VZ
143 /* Unsupported KVM type */
147 /* Allocate page table to map GPA -> RPA */
148 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
149 if (!kvm->arch.gpa_mm.pgd)
155 bool kvm_arch_has_vcpu_debugfs(void)
160 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
165 void kvm_mips_free_vcpus(struct kvm *kvm)
168 struct kvm_vcpu *vcpu;
170 kvm_for_each_vcpu(i, vcpu, kvm) {
171 kvm_arch_vcpu_free(vcpu);
174 mutex_lock(&kvm->lock);
176 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
177 kvm->vcpus[i] = NULL;
179 atomic_set(&kvm->online_vcpus, 0);
181 mutex_unlock(&kvm->lock);
184 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
186 /* It should always be safe to remove after flushing the whole range */
187 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
188 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
191 void kvm_arch_destroy_vm(struct kvm *kvm)
193 kvm_mips_free_vcpus(kvm);
194 kvm_mips_free_gpa_pt(kvm);
197 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
203 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
204 unsigned long npages)
209 void kvm_arch_flush_shadow_all(struct kvm *kvm)
211 /* Flush whole GPA */
212 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
214 /* Let implementation do the rest */
215 kvm_mips_callbacks->flush_shadow_all(kvm);
218 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
219 struct kvm_memory_slot *slot)
222 * The slot has been made invalid (ready for moving or deletion), so we
223 * need to ensure that it can no longer be accessed by any guest VCPUs.
226 spin_lock(&kvm->mmu_lock);
227 /* Flush slot from GPA */
228 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
229 slot->base_gfn + slot->npages - 1);
230 /* Let implementation do the rest */
231 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
232 spin_unlock(&kvm->mmu_lock);
235 int kvm_arch_prepare_memory_region(struct kvm *kvm,
236 struct kvm_memory_slot *memslot,
237 const struct kvm_userspace_memory_region *mem,
238 enum kvm_mr_change change)
243 void kvm_arch_commit_memory_region(struct kvm *kvm,
244 const struct kvm_userspace_memory_region *mem,
245 const struct kvm_memory_slot *old,
246 const struct kvm_memory_slot *new,
247 enum kvm_mr_change change)
251 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
252 __func__, kvm, mem->slot, mem->guest_phys_addr,
253 mem->memory_size, mem->userspace_addr);
256 * If dirty page logging is enabled, write protect all pages in the slot
257 * ready for dirty logging.
259 * There is no need to do this in any of the following cases:
260 * CREATE: No dirty mappings will already exist.
261 * MOVE/DELETE: The old mappings will already have been cleaned up by
262 * kvm_arch_flush_shadow_memslot()
264 if (change == KVM_MR_FLAGS_ONLY &&
265 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
266 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
267 spin_lock(&kvm->mmu_lock);
268 /* Write protect GPA page table entries */
269 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
270 new->base_gfn + new->npages - 1);
271 /* Let implementation do the rest */
273 kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
274 spin_unlock(&kvm->mmu_lock);
278 static inline void dump_handler(const char *symbol, void *start, void *end)
282 pr_debug("LEAF(%s)\n", symbol);
284 pr_debug("\t.set push\n");
285 pr_debug("\t.set noreorder\n");
287 for (p = start; p < (u32 *)end; ++p)
288 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
290 pr_debug("\t.set\tpop\n");
292 pr_debug("\tEND(%s)\n", symbol);
295 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
298 void *gebase, *p, *handler, *refill_start, *refill_end;
301 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
308 err = kvm_vcpu_init(vcpu, kvm, id);
313 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
316 * Allocate space for host mode exception handlers that handle
319 if (cpu_has_veic || cpu_has_vint)
320 size = 0x200 + VECTORSPACING * 64;
324 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
330 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
331 ALIGN(size, PAGE_SIZE), gebase);
334 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
335 * limits us to the low 512MB of physical address space. If the memory
336 * we allocate is out of range, just give up now.
338 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
339 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
342 goto out_free_gebase;
346 vcpu->arch.guest_ebase = gebase;
348 /* Build guest exception vectors dynamically in unmapped memory */
349 handler = gebase + 0x2000;
351 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
352 refill_start = gebase;
353 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
354 refill_start += 0x080;
355 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
357 /* General Exception Entry point */
358 kvm_mips_build_exception(gebase + 0x180, handler);
360 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
361 for (i = 0; i < 8; i++) {
362 kvm_debug("L1 Vectored handler @ %p\n",
363 gebase + 0x200 + (i * VECTORSPACING));
364 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
368 /* General exit handler */
370 p = kvm_mips_build_exit(p);
372 /* Guest entry routine */
373 vcpu->arch.vcpu_run = p;
374 p = kvm_mips_build_vcpu_run(p);
376 /* Dump the generated code */
377 pr_debug("#include <asm/asm.h>\n");
378 pr_debug("#include <asm/regdef.h>\n");
380 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
381 dump_handler("kvm_tlb_refill", refill_start, refill_end);
382 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
383 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
385 /* Invalidate the icache for these ranges */
386 flush_icache_range((unsigned long)gebase,
387 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
390 * Allocate comm page for guest kernel, a TLB will be reserved for
391 * mapping GVA @ 0xFFFF8000 to this page
393 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
395 if (!vcpu->arch.kseg0_commpage) {
397 goto out_free_gebase;
400 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
401 kvm_mips_commpage_init(vcpu);
404 vcpu->arch.last_sched_cpu = -1;
405 vcpu->arch.last_exec_cpu = -1;
413 kvm_vcpu_uninit(vcpu);
422 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
424 hrtimer_cancel(&vcpu->arch.comparecount_timer);
426 kvm_vcpu_uninit(vcpu);
428 kvm_mips_dump_stats(vcpu);
430 kvm_mmu_free_memory_caches(vcpu);
431 kfree(vcpu->arch.guest_ebase);
432 kfree(vcpu->arch.kseg0_commpage);
436 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
438 kvm_arch_vcpu_free(vcpu);
441 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
442 struct kvm_guest_debug *dbg)
447 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
451 kvm_sigset_activate(vcpu);
453 if (vcpu->mmio_needed) {
454 if (!vcpu->mmio_is_write)
455 kvm_mips_complete_mmio_load(vcpu, run);
456 vcpu->mmio_needed = 0;
459 if (run->immediate_exit)
465 guest_enter_irqoff();
466 trace_kvm_enter(vcpu);
469 * Make sure the read of VCPU requests in vcpu_run() callback is not
470 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
471 * flush request while the requester sees the VCPU as outside of guest
472 * mode and not needing an IPI.
474 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
476 r = kvm_mips_callbacks->vcpu_run(run, vcpu);
483 kvm_sigset_deactivate(vcpu);
488 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
489 struct kvm_mips_interrupt *irq)
491 int intr = (int)irq->irq;
492 struct kvm_vcpu *dvcpu = NULL;
494 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
495 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
501 dvcpu = vcpu->kvm->vcpus[irq->cpu];
503 if (intr == 2 || intr == 3 || intr == 4) {
504 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
506 } else if (intr == -2 || intr == -3 || intr == -4) {
507 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
509 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
514 dvcpu->arch.wait = 0;
516 if (swq_has_sleeper(&dvcpu->wq))
517 swake_up(&dvcpu->wq);
522 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
523 struct kvm_mp_state *mp_state)
528 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
529 struct kvm_mp_state *mp_state)
534 static u64 kvm_mips_get_one_regs[] = {
568 #ifndef CONFIG_CPU_MIPSR6
575 static u64 kvm_mips_get_one_regs_fpu[] = {
577 KVM_REG_MIPS_FCR_CSR,
580 static u64 kvm_mips_get_one_regs_msa[] = {
582 KVM_REG_MIPS_MSA_CSR,
585 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
589 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
590 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
591 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
593 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
596 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
597 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
598 ret += kvm_mips_callbacks->num_regs(vcpu);
603 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
608 if (copy_to_user(indices, kvm_mips_get_one_regs,
609 sizeof(kvm_mips_get_one_regs)))
611 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
613 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
614 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
615 sizeof(kvm_mips_get_one_regs_fpu)))
617 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
619 for (i = 0; i < 32; ++i) {
620 index = KVM_REG_MIPS_FPR_32(i);
621 if (copy_to_user(indices, &index, sizeof(index)))
625 /* skip odd doubles if no F64 */
626 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
629 index = KVM_REG_MIPS_FPR_64(i);
630 if (copy_to_user(indices, &index, sizeof(index)))
636 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
637 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
638 sizeof(kvm_mips_get_one_regs_msa)))
640 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
642 for (i = 0; i < 32; ++i) {
643 index = KVM_REG_MIPS_VEC_128(i);
644 if (copy_to_user(indices, &index, sizeof(index)))
650 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
653 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
654 const struct kvm_one_reg *reg)
656 struct mips_coproc *cop0 = vcpu->arch.cop0;
657 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
664 /* General purpose registers */
665 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
666 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
668 #ifndef CONFIG_CPU_MIPSR6
669 case KVM_REG_MIPS_HI:
670 v = (long)vcpu->arch.hi;
672 case KVM_REG_MIPS_LO:
673 v = (long)vcpu->arch.lo;
676 case KVM_REG_MIPS_PC:
677 v = (long)vcpu->arch.pc;
680 /* Floating point registers */
681 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
682 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
684 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
685 /* Odd singles in top of even double when FR=0 */
686 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
687 v = get_fpr32(&fpu->fpr[idx], 0);
689 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
691 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
692 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
694 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
695 /* Can't access odd doubles in FR=0 mode */
696 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
698 v = get_fpr64(&fpu->fpr[idx], 0);
700 case KVM_REG_MIPS_FCR_IR:
701 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
703 v = boot_cpu_data.fpu_id;
705 case KVM_REG_MIPS_FCR_CSR:
706 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
711 /* MIPS SIMD Architecture (MSA) registers */
712 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
713 if (!kvm_mips_guest_has_msa(&vcpu->arch))
715 /* Can't access MSA registers in FR=0 mode */
716 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
718 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
719 #ifdef CONFIG_CPU_LITTLE_ENDIAN
720 /* least significant byte first */
721 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
722 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
724 /* most significant byte first */
725 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
726 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
729 case KVM_REG_MIPS_MSA_IR:
730 if (!kvm_mips_guest_has_msa(&vcpu->arch))
732 v = boot_cpu_data.msa_id;
734 case KVM_REG_MIPS_MSA_CSR:
735 if (!kvm_mips_guest_has_msa(&vcpu->arch))
740 /* registers to be handled specially */
742 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
747 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
748 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
750 return put_user(v, uaddr64);
751 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
752 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
755 return put_user(v32, uaddr32);
756 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
757 void __user *uaddr = (void __user *)(long)reg->addr;
759 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
765 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
766 const struct kvm_one_reg *reg)
768 struct mips_coproc *cop0 = vcpu->arch.cop0;
769 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
774 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
775 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
777 if (get_user(v, uaddr64) != 0)
779 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
780 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
783 if (get_user(v32, uaddr32) != 0)
786 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
787 void __user *uaddr = (void __user *)(long)reg->addr;
789 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
795 /* General purpose registers */
796 case KVM_REG_MIPS_R0:
797 /* Silently ignore requests to set $0 */
799 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
800 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
802 #ifndef CONFIG_CPU_MIPSR6
803 case KVM_REG_MIPS_HI:
806 case KVM_REG_MIPS_LO:
810 case KVM_REG_MIPS_PC:
814 /* Floating point registers */
815 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
816 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
818 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
819 /* Odd singles in top of even double when FR=0 */
820 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
821 set_fpr32(&fpu->fpr[idx], 0, v);
823 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
825 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
826 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
828 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
829 /* Can't access odd doubles in FR=0 mode */
830 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
832 set_fpr64(&fpu->fpr[idx], 0, v);
834 case KVM_REG_MIPS_FCR_IR:
835 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
839 case KVM_REG_MIPS_FCR_CSR:
840 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
845 /* MIPS SIMD Architecture (MSA) registers */
846 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
847 if (!kvm_mips_guest_has_msa(&vcpu->arch))
849 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
850 #ifdef CONFIG_CPU_LITTLE_ENDIAN
851 /* least significant byte first */
852 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
853 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
855 /* most significant byte first */
856 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
857 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
860 case KVM_REG_MIPS_MSA_IR:
861 if (!kvm_mips_guest_has_msa(&vcpu->arch))
865 case KVM_REG_MIPS_MSA_CSR:
866 if (!kvm_mips_guest_has_msa(&vcpu->arch))
871 /* registers to be handled specially */
873 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
878 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
879 struct kvm_enable_cap *cap)
883 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
891 case KVM_CAP_MIPS_FPU:
892 vcpu->arch.fpu_enabled = true;
894 case KVM_CAP_MIPS_MSA:
895 vcpu->arch.msa_enabled = true;
905 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
908 struct kvm_vcpu *vcpu = filp->private_data;
909 void __user *argp = (void __user *)arg;
913 case KVM_SET_ONE_REG:
914 case KVM_GET_ONE_REG: {
915 struct kvm_one_reg reg;
917 if (copy_from_user(®, argp, sizeof(reg)))
919 if (ioctl == KVM_SET_ONE_REG)
920 return kvm_mips_set_reg(vcpu, ®);
922 return kvm_mips_get_reg(vcpu, ®);
924 case KVM_GET_REG_LIST: {
925 struct kvm_reg_list __user *user_list = argp;
926 struct kvm_reg_list reg_list;
929 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
932 reg_list.n = kvm_mips_num_regs(vcpu);
933 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
937 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
941 struct kvm_mips_interrupt irq;
943 if (copy_from_user(&irq, argp, sizeof(irq)))
945 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
948 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
951 case KVM_ENABLE_CAP: {
952 struct kvm_enable_cap cap;
954 if (copy_from_user(&cap, argp, sizeof(cap)))
956 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
966 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
968 * @log: slot id and address to which we copy the log
970 * Steps 1-4 below provide general overview of dirty page logging. See
971 * kvm_get_dirty_log_protect() function description for additional details.
973 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
974 * always flush the TLB (step 4) even if previous step failed and the dirty
975 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
976 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
977 * writes will be marked dirty for next log read.
979 * 1. Take a snapshot of the bit and clear it if needed.
980 * 2. Write protect the corresponding page.
981 * 3. Copy the snapshot to the userspace.
982 * 4. Flush TLB's if needed.
984 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
986 struct kvm_memslots *slots;
987 struct kvm_memory_slot *memslot;
988 bool is_dirty = false;
991 mutex_lock(&kvm->slots_lock);
993 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
996 slots = kvm_memslots(kvm);
997 memslot = id_to_memslot(slots, log->slot);
999 /* Let implementation handle TLB/GVA invalidation */
1000 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1003 mutex_unlock(&kvm->slots_lock);
1007 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1019 int kvm_arch_init(void *opaque)
1021 if (kvm_mips_callbacks) {
1022 kvm_err("kvm: module already exists\n");
1026 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1029 void kvm_arch_exit(void)
1031 kvm_mips_callbacks = NULL;
1034 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1035 struct kvm_sregs *sregs)
1037 return -ENOIOCTLCMD;
1040 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1041 struct kvm_sregs *sregs)
1043 return -ENOIOCTLCMD;
1046 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1050 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1052 return -ENOIOCTLCMD;
1055 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1057 return -ENOIOCTLCMD;
1060 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1062 return VM_FAULT_SIGBUS;
1065 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1070 case KVM_CAP_ONE_REG:
1071 case KVM_CAP_ENABLE_CAP:
1072 case KVM_CAP_READONLY_MEM:
1073 case KVM_CAP_SYNC_MMU:
1074 case KVM_CAP_IMMEDIATE_EXIT:
1077 case KVM_CAP_NR_VCPUS:
1078 r = num_online_cpus();
1080 case KVM_CAP_MAX_VCPUS:
1083 case KVM_CAP_MAX_VCPU_ID:
1084 r = KVM_MAX_VCPU_ID;
1086 case KVM_CAP_MIPS_FPU:
1087 /* We don't handle systems with inconsistent cpu_has_fpu */
1088 r = !!raw_cpu_has_fpu;
1090 case KVM_CAP_MIPS_MSA:
1092 * We don't support MSA vector partitioning yet:
1093 * 1) It would require explicit support which can't be tested
1094 * yet due to lack of support in current hardware.
1095 * 2) It extends the state that would need to be saved/restored
1096 * by e.g. QEMU for migration.
1098 * When vector partitioning hardware becomes available, support
1099 * could be added by requiring a flag when enabling
1100 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1101 * to save/restore the appropriate extra state.
1103 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1106 r = kvm_mips_callbacks->check_extension(kvm, ext);
1112 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1114 return kvm_mips_pending_timer(vcpu) ||
1115 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1118 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1121 struct mips_coproc *cop0;
1126 kvm_debug("VCPU Register Dump:\n");
1127 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1128 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1130 for (i = 0; i < 32; i += 4) {
1131 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1133 vcpu->arch.gprs[i + 1],
1134 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1136 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1137 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1139 cop0 = vcpu->arch.cop0;
1140 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1141 kvm_read_c0_guest_status(cop0),
1142 kvm_read_c0_guest_cause(cop0));
1144 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1149 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1153 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1154 vcpu->arch.gprs[i] = regs->gpr[i];
1155 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1156 vcpu->arch.hi = regs->hi;
1157 vcpu->arch.lo = regs->lo;
1158 vcpu->arch.pc = regs->pc;
1163 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1167 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1168 regs->gpr[i] = vcpu->arch.gprs[i];
1170 regs->hi = vcpu->arch.hi;
1171 regs->lo = vcpu->arch.lo;
1172 regs->pc = vcpu->arch.pc;
1177 static void kvm_mips_comparecount_func(unsigned long data)
1179 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1181 kvm_mips_callbacks->queue_timer_int(vcpu);
1183 vcpu->arch.wait = 0;
1184 if (swq_has_sleeper(&vcpu->wq))
1185 swake_up(&vcpu->wq);
1188 /* low level hrtimer wake routine */
1189 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1191 struct kvm_vcpu *vcpu;
1193 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1194 kvm_mips_comparecount_func((unsigned long) vcpu);
1195 return kvm_mips_count_timeout(vcpu);
1198 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1202 err = kvm_mips_callbacks->vcpu_init(vcpu);
1206 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1208 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1212 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1214 kvm_mips_callbacks->vcpu_uninit(vcpu);
1217 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1218 struct kvm_translation *tr)
1223 /* Initial guest state */
1224 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1226 return kvm_mips_callbacks->vcpu_setup(vcpu);
1229 static void kvm_mips_set_c0_status(void)
1231 u32 status = read_c0_status();
1236 write_c0_status(status);
1241 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1243 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1245 u32 cause = vcpu->arch.host_cp0_cause;
1246 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1247 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1248 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1249 enum emulation_result er = EMULATE_DONE;
1251 int ret = RESUME_GUEST;
1253 vcpu->mode = OUTSIDE_GUEST_MODE;
1255 /* re-enable HTW before enabling interrupts */
1256 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1259 /* Set a default exit reason */
1260 run->exit_reason = KVM_EXIT_UNKNOWN;
1261 run->ready_for_interrupt_injection = 1;
1264 * Set the appropriate status bits based on host CPU features,
1265 * before we hit the scheduler
1267 kvm_mips_set_c0_status();
1271 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1272 cause, opc, run, vcpu);
1273 trace_kvm_exit(vcpu, exccode);
1275 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1277 * Do a privilege check, if in UM most of these exit conditions
1278 * end up causing an exception to be delivered to the Guest
1281 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1282 if (er == EMULATE_PRIV_FAIL) {
1284 } else if (er == EMULATE_FAIL) {
1285 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1293 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1295 ++vcpu->stat.int_exits;
1304 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1306 ++vcpu->stat.cop_unusable_exits;
1307 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1308 /* XXXKYMA: Might need to return to user space */
1309 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1314 ++vcpu->stat.tlbmod_exits;
1315 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1319 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1320 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1323 ++vcpu->stat.tlbmiss_st_exits;
1324 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1328 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1329 cause, opc, badvaddr);
1331 ++vcpu->stat.tlbmiss_ld_exits;
1332 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1336 ++vcpu->stat.addrerr_st_exits;
1337 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1341 ++vcpu->stat.addrerr_ld_exits;
1342 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1346 ++vcpu->stat.syscall_exits;
1347 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1351 ++vcpu->stat.resvd_inst_exits;
1352 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1356 ++vcpu->stat.break_inst_exits;
1357 ret = kvm_mips_callbacks->handle_break(vcpu);
1361 ++vcpu->stat.trap_inst_exits;
1362 ret = kvm_mips_callbacks->handle_trap(vcpu);
1365 case EXCCODE_MSAFPE:
1366 ++vcpu->stat.msa_fpe_exits;
1367 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1371 ++vcpu->stat.fpe_exits;
1372 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1375 case EXCCODE_MSADIS:
1376 ++vcpu->stat.msa_disabled_exits;
1377 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1381 /* defer exit accounting to handler */
1382 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1386 if (cause & CAUSEF_BD)
1389 kvm_get_badinstr(opc, vcpu, &inst);
1390 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1391 exccode, opc, inst, badvaddr,
1392 kvm_read_c0_guest_status(vcpu->arch.cop0));
1393 kvm_arch_vcpu_dump_regs(vcpu);
1394 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1401 local_irq_disable();
1403 if (ret == RESUME_GUEST)
1404 kvm_vz_acquire_htimer(vcpu);
1406 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1407 kvm_mips_deliver_interrupts(vcpu, cause);
1409 if (!(ret & RESUME_HOST)) {
1410 /* Only check for signals if not already exiting to userspace */
1411 if (signal_pending(current)) {
1412 run->exit_reason = KVM_EXIT_INTR;
1413 ret = (-EINTR << 2) | RESUME_HOST;
1414 ++vcpu->stat.signal_exits;
1415 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1419 if (ret == RESUME_GUEST) {
1420 trace_kvm_reenter(vcpu);
1423 * Make sure the read of VCPU requests in vcpu_reenter()
1424 * callback is not reordered ahead of the write to vcpu->mode,
1425 * or we could miss a TLB flush request while the requester sees
1426 * the VCPU as outside of guest mode and not needing an IPI.
1428 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1430 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1433 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1434 * is live), restore FCR31 / MSACSR.
1436 * This should be before returning to the guest exception
1437 * vector, as it may well cause an [MSA] FP exception if there
1438 * are pending exception bits unmasked. (see
1439 * kvm_mips_csr_die_notifier() for how that is handled).
1441 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1442 read_c0_status() & ST0_CU1)
1443 __kvm_restore_fcsr(&vcpu->arch);
1445 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1446 read_c0_config5() & MIPS_CONF5_MSAEN)
1447 __kvm_restore_msacsr(&vcpu->arch);
1450 /* Disable HTW before returning to guest or host */
1451 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1457 /* Enable FPU for guest and restore context */
1458 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1460 struct mips_coproc *cop0 = vcpu->arch.cop0;
1461 unsigned int sr, cfg5;
1465 sr = kvm_read_c0_guest_status(cop0);
1468 * If MSA state is already live, it is undefined how it interacts with
1469 * FR=0 FPU state, and we don't want to hit reserved instruction
1470 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1471 * play it safe and save it first.
1473 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1474 * get called when guest CU1 is set, however we can't trust the guest
1475 * not to clobber the status register directly via the commpage.
1477 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1478 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1482 * Enable FPU for guest
1483 * We set FR and FRE according to guest context
1485 change_c0_status(ST0_CU1 | ST0_FR, sr);
1487 cfg5 = kvm_read_c0_guest_config5(cop0);
1488 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1490 enable_fpu_hazard();
1492 /* If guest FPU state not active, restore it now */
1493 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1494 __kvm_restore_fpu(&vcpu->arch);
1495 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1496 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1498 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1504 #ifdef CONFIG_CPU_HAS_MSA
1505 /* Enable MSA for guest and restore context */
1506 void kvm_own_msa(struct kvm_vcpu *vcpu)
1508 struct mips_coproc *cop0 = vcpu->arch.cop0;
1509 unsigned int sr, cfg5;
1514 * Enable FPU if enabled in guest, since we're restoring FPU context
1515 * anyway. We set FR and FRE according to guest context.
1517 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1518 sr = kvm_read_c0_guest_status(cop0);
1521 * If FR=0 FPU state is already live, it is undefined how it
1522 * interacts with MSA state, so play it safe and save it first.
1524 if (!(sr & ST0_FR) &&
1525 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1526 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1529 change_c0_status(ST0_CU1 | ST0_FR, sr);
1530 if (sr & ST0_CU1 && cpu_has_fre) {
1531 cfg5 = kvm_read_c0_guest_config5(cop0);
1532 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1536 /* Enable MSA for guest */
1537 set_c0_config5(MIPS_CONF5_MSAEN);
1538 enable_fpu_hazard();
1540 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1541 case KVM_MIPS_AUX_FPU:
1543 * Guest FPU state already loaded, only restore upper MSA state
1545 __kvm_restore_msa_upper(&vcpu->arch);
1546 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1547 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1550 /* Neither FPU or MSA already active, restore full MSA state */
1551 __kvm_restore_msa(&vcpu->arch);
1552 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1553 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1554 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1555 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1556 KVM_TRACE_AUX_FPU_MSA);
1559 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1567 /* Drop FPU & MSA without saving it */
1568 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1571 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1573 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1574 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1576 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1577 clear_c0_status(ST0_CU1 | ST0_FR);
1578 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1579 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1584 /* Save and disable FPU & MSA */
1585 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1588 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1589 * is disabled in guest context (software), but the register state in
1590 * the hardware may still be in use.
1591 * This is why we explicitly re-enable the hardware before saving.
1595 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1596 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1597 set_c0_config5(MIPS_CONF5_MSAEN);
1598 enable_fpu_hazard();
1601 __kvm_save_msa(&vcpu->arch);
1602 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1604 /* Disable MSA & FPU */
1606 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1607 clear_c0_status(ST0_CU1 | ST0_FR);
1608 disable_fpu_hazard();
1610 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1611 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1612 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1613 set_c0_status(ST0_CU1);
1614 enable_fpu_hazard();
1617 __kvm_save_fpu(&vcpu->arch);
1618 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1619 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1622 clear_c0_status(ST0_CU1 | ST0_FR);
1623 disable_fpu_hazard();
1629 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1630 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1631 * exception if cause bits are set in the value being written.
1633 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1634 unsigned long cmd, void *ptr)
1636 struct die_args *args = (struct die_args *)ptr;
1637 struct pt_regs *regs = args->regs;
1640 /* Only interested in FPE and MSAFPE */
1641 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1644 /* Return immediately if guest context isn't active */
1645 if (!(current->flags & PF_VCPU))
1648 /* Should never get here from user mode */
1649 BUG_ON(user_mode(regs));
1651 pc = instruction_pointer(regs);
1654 /* match 2nd instruction in __kvm_restore_fcsr */
1655 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1659 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1661 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1662 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1667 /* Move PC forward a little and continue executing */
1668 instruction_pointer(regs) += 4;
1673 static struct notifier_block kvm_mips_csr_die_notifier = {
1674 .notifier_call = kvm_mips_csr_die_notify,
1677 static int __init kvm_mips_init(void)
1681 ret = kvm_mips_entry_setup();
1685 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1690 register_die_notifier(&kvm_mips_csr_die_notifier);
1695 static void __exit kvm_mips_exit(void)
1699 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1702 module_init(kvm_mips_init);
1703 module_exit(kvm_mips_exit);
1705 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);