arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/fpu.h>
  24 #include <asm/page.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/pgtable.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33 #include "commpage.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "trace.h"
  37
  38 #ifndef VECTORSPACING
  39 #define VECTORSPACING 0x100     /* for EI/VI mode */
  40 #endif
  41
  42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  43 struct kvm_stats_debugfs_item debugfs_entries[] = {
  44         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  45         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  46         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  47         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  48         { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  49         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  50         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  51         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  52         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  53         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  54         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  55         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  56         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  57         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  58         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  59         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  60         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  61         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  62 #ifdef CONFIG_KVM_MIPS_VZ
  63         { "vz_gpsi",      VCPU_STAT(vz_gpsi_exits),      KVM_STAT_VCPU },
  64         { "vz_gsfc",      VCPU_STAT(vz_gsfc_exits),      KVM_STAT_VCPU },
  65         { "vz_hc",        VCPU_STAT(vz_hc_exits),        KVM_STAT_VCPU },
  66         { "vz_grr",       VCPU_STAT(vz_grr_exits),       KVM_STAT_VCPU },
  67         { "vz_gva",       VCPU_STAT(vz_gva_exits),       KVM_STAT_VCPU },
  68         { "vz_ghfc",      VCPU_STAT(vz_ghfc_exits),      KVM_STAT_VCPU },
  69         { "vz_gpa",       VCPU_STAT(vz_gpa_exits),       KVM_STAT_VCPU },
  70         { "vz_resvd",     VCPU_STAT(vz_resvd_exits),     KVM_STAT_VCPU },
  71 #endif
  72         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  73         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  74         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  75         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  76         {NULL}
  77 };
  78
  79 bool kvm_trace_guest_mode_change;
  80
  81 int kvm_guest_mode_change_trace_reg(void)
  82 {
  83         kvm_trace_guest_mode_change = 1;
  84         return 0;
  85 }
  86
  87 void kvm_guest_mode_change_trace_unreg(void)
  88 {
  89         kvm_trace_guest_mode_change = 0;
  90 }
  91
  92 /*
  93  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  94  * Config7, so we are "runnable" if interrupts are pending
  95  */
  96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  97 {
  98         return !!(vcpu->arch.pending_exceptions);
  99 }
 100
 101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 102 {
 103         return false;
 104 }
 105
 106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 107 {
 108         return 1;
 109 }
 110
 111 int kvm_arch_hardware_enable(void)
 112 {
 113         return kvm_mips_callbacks->hardware_enable();
 114 }
 115
 116 void kvm_arch_hardware_disable(void)
 117 {
 118         kvm_mips_callbacks->hardware_disable();
 119 }
 120
 121 int kvm_arch_hardware_setup(void)
 122 {
 123         return 0;
 124 }
 125
 126 void kvm_arch_check_processor_compat(void *rtn)
 127 {
 128         *(int *)rtn = 0;
 129 }
 130
 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 132 {
 133         switch (type) {
 134         case KVM_VM_MIPS_AUTO:
 135                 break;
 136 #ifdef CONFIG_KVM_MIPS_VZ
 137         case KVM_VM_MIPS_VZ:
 138 #else
 139         case KVM_VM_MIPS_TE:
 140 #endif
 141                 break;
 142         default:
 143                 /* Unsupported KVM type */
 144                 return -EINVAL;
 145         };
 146
 147         /* Allocate page table to map GPA -> RPA */
 148         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 149         if (!kvm->arch.gpa_mm.pgd)
 150                 return -ENOMEM;
 151
 152         return 0;
 153 }
 154
 155 bool kvm_arch_has_vcpu_debugfs(void)
 156 {
 157         return false;
 158 }
 159
 160 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
 161 {
 162         return 0;
 163 }
 164
 165 void kvm_mips_free_vcpus(struct kvm *kvm)
 166 {
 167         unsigned int i;
 168         struct kvm_vcpu *vcpu;
 169
 170         kvm_for_each_vcpu(i, vcpu, kvm) {
 171                 kvm_arch_vcpu_free(vcpu);
 172         }
 173
 174         mutex_lock(&kvm->lock);
 175
 176         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 177                 kvm->vcpus[i] = NULL;
 178
 179         atomic_set(&kvm->online_vcpus, 0);
 180
 181         mutex_unlock(&kvm->lock);
 182 }
 183
 184 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 185 {
 186         /* It should always be safe to remove after flushing the whole range */
 187         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 188         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 189 }
 190
 191 void kvm_arch_destroy_vm(struct kvm *kvm)
 192 {
 193         kvm_mips_free_vcpus(kvm);
 194         kvm_mips_free_gpa_pt(kvm);
 195 }
 196
 197 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 198                         unsigned long arg)
 199 {
 200         return -ENOIOCTLCMD;
 201 }
 202
 203 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 204                             unsigned long npages)
 205 {
 206         return 0;
 207 }
 208
 209 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 210 {
 211         /* Flush whole GPA */
 212         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 213
 214         /* Let implementation do the rest */
 215         kvm_mips_callbacks->flush_shadow_all(kvm);
 216 }
 217
 218 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 219                                    struct kvm_memory_slot *slot)
 220 {
 221         /*
 222          * The slot has been made invalid (ready for moving or deletion), so we
 223          * need to ensure that it can no longer be accessed by any guest VCPUs.
 224          */
 225
 226         spin_lock(&kvm->mmu_lock);
 227         /* Flush slot from GPA */
 228         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 229                               slot->base_gfn + slot->npages - 1);
 230         /* Let implementation do the rest */
 231         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 232         spin_unlock(&kvm->mmu_lock);
 233 }
 234
 235 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 236                                    struct kvm_memory_slot *memslot,
 237                                    const struct kvm_userspace_memory_region *mem,
 238                                    enum kvm_mr_change change)
 239 {
 240         return 0;
 241 }
 242
 243 void kvm_arch_commit_memory_region(struct kvm *kvm,
 244                                    const struct kvm_userspace_memory_region *mem,
 245                                    const struct kvm_memory_slot *old,
 246                                    const struct kvm_memory_slot *new,
 247                                    enum kvm_mr_change change)
 248 {
 249         int needs_flush;
 250
 251         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 252                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 253                   mem->memory_size, mem->userspace_addr);
 254
 255         /*
 256          * If dirty page logging is enabled, write protect all pages in the slot
 257          * ready for dirty logging.
 258          *
 259          * There is no need to do this in any of the following cases:
 260          * CREATE:      No dirty mappings will already exist.
 261          * MOVE/DELETE: The old mappings will already have been cleaned up by
 262          *              kvm_arch_flush_shadow_memslot()
 263          */
 264         if (change == KVM_MR_FLAGS_ONLY &&
 265             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 266              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 267                 spin_lock(&kvm->mmu_lock);
 268                 /* Write protect GPA page table entries */
 269                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 270                                         new->base_gfn + new->npages - 1);
 271                 /* Let implementation do the rest */
 272                 if (needs_flush)
 273                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 274                 spin_unlock(&kvm->mmu_lock);
 275         }
 276 }
 277
 278 static inline void dump_handler(const char *symbol, void *start, void *end)
 279 {
 280         u32 *p;
 281
 282         pr_debug("LEAF(%s)\n", symbol);
 283
 284         pr_debug("\t.set push\n");
 285         pr_debug("\t.set noreorder\n");
 286
 287         for (p = start; p < (u32 *)end; ++p)
 288                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 289
 290         pr_debug("\t.set\tpop\n");
 291
 292         pr_debug("\tEND(%s)\n", symbol);
 293 }
 294
 295 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 296 {
 297         int err, size;
 298         void *gebase, *p, *handler, *refill_start, *refill_end;
 299         int i;
 300
 301         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 302
 303         if (!vcpu) {
 304                 err = -ENOMEM;
 305                 goto out;
 306         }
 307
 308         err = kvm_vcpu_init(vcpu, kvm, id);
 309
 310         if (err)
 311                 goto out_free_cpu;
 312
 313         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 314
 315         /*
 316          * Allocate space for host mode exception handlers that handle
 317          * guest mode exits
 318          */
 319         if (cpu_has_veic || cpu_has_vint)
 320                 size = 0x200 + VECTORSPACING * 64;
 321         else
 322                 size = 0x4000;
 323
 324         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 325
 326         if (!gebase) {
 327                 err = -ENOMEM;
 328                 goto out_uninit_cpu;
 329         }
 330         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 331                   ALIGN(size, PAGE_SIZE), gebase);
 332
 333         /*
 334          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 335          * limits us to the low 512MB of physical address space. If the memory
 336          * we allocate is out of range, just give up now.
 337          */
 338         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 339                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 340                         gebase);
 341                 err = -ENOMEM;
 342                 goto out_free_gebase;
 343         }
 344
 345         /* Save new ebase */
 346         vcpu->arch.guest_ebase = gebase;
 347
 348         /* Build guest exception vectors dynamically in unmapped memory */
 349         handler = gebase + 0x2000;
 350
 351         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 352         refill_start = gebase;
 353         if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
 354                 refill_start += 0x080;
 355         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 356
 357         /* General Exception Entry point */
 358         kvm_mips_build_exception(gebase + 0x180, handler);
 359
 360         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 361         for (i = 0; i < 8; i++) {
 362                 kvm_debug("L1 Vectored handler @ %p\n",
 363                           gebase + 0x200 + (i * VECTORSPACING));
 364                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 365                                          handler);
 366         }
 367
 368         /* General exit handler */
 369         p = handler;
 370         p = kvm_mips_build_exit(p);
 371
 372         /* Guest entry routine */
 373         vcpu->arch.vcpu_run = p;
 374         p = kvm_mips_build_vcpu_run(p);
 375
 376         /* Dump the generated code */
 377         pr_debug("#include <asm/asm.h>\n");
 378         pr_debug("#include <asm/regdef.h>\n");
 379         pr_debug("\n");
 380         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 381         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 382         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 383         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 384
 385         /* Invalidate the icache for these ranges */
 386         flush_icache_range((unsigned long)gebase,
 387                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 388
 389         /*
 390          * Allocate comm page for guest kernel, a TLB will be reserved for
 391          * mapping GVA @ 0xFFFF8000 to this page
 392          */
 393         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 394
 395         if (!vcpu->arch.kseg0_commpage) {
 396                 err = -ENOMEM;
 397                 goto out_free_gebase;
 398         }
 399
 400         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 401         kvm_mips_commpage_init(vcpu);
 402
 403         /* Init */
 404         vcpu->arch.last_sched_cpu = -1;
 405         vcpu->arch.last_exec_cpu = -1;
 406
 407         return vcpu;
 408
 409 out_free_gebase:
 410         kfree(gebase);
 411
 412 out_uninit_cpu:
 413         kvm_vcpu_uninit(vcpu);
 414
 415 out_free_cpu:
 416         kfree(vcpu);
 417
 418 out:
 419         return ERR_PTR(err);
 420 }
 421
 422 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 423 {
 424         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 425
 426         kvm_vcpu_uninit(vcpu);
 427
 428         kvm_mips_dump_stats(vcpu);
 429
 430         kvm_mmu_free_memory_caches(vcpu);
 431         kfree(vcpu->arch.guest_ebase);
 432         kfree(vcpu->arch.kseg0_commpage);
 433         kfree(vcpu);
 434 }
 435
 436 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 437 {
 438         kvm_arch_vcpu_free(vcpu);
 439 }
 440
 441 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 442                                         struct kvm_guest_debug *dbg)
 443 {
 444         return -ENOIOCTLCMD;
 445 }
 446
 447 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 448 {
 449         int r = -EINTR;
 450
 451         kvm_sigset_activate(vcpu);
 452
 453         if (vcpu->mmio_needed) {
 454                 if (!vcpu->mmio_is_write)
 455                         kvm_mips_complete_mmio_load(vcpu, run);
 456                 vcpu->mmio_needed = 0;
 457         }
 458
 459         if (run->immediate_exit)
 460                 goto out;
 461
 462         lose_fpu(1);
 463
 464         local_irq_disable();
 465         guest_enter_irqoff();
 466         trace_kvm_enter(vcpu);
 467
 468         /*
 469          * Make sure the read of VCPU requests in vcpu_run() callback is not
 470          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 471          * flush request while the requester sees the VCPU as outside of guest
 472          * mode and not needing an IPI.
 473          */
 474         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 475
 476         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 477
 478         trace_kvm_out(vcpu);
 479         guest_exit_irqoff();
 480         local_irq_enable();
 481
 482 out:
 483         kvm_sigset_deactivate(vcpu);
 484
 485         return r;
 486 }
 487
 488 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 489                              struct kvm_mips_interrupt *irq)
 490 {
 491         int intr = (int)irq->irq;
 492         struct kvm_vcpu *dvcpu = NULL;
 493
 494         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 495                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 496                           (int)intr);
 497
 498         if (irq->cpu == -1)
 499                 dvcpu = vcpu;
 500         else
 501                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 502
 503         if (intr == 2 || intr == 3 || intr == 4) {
 504                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 505
 506         } else if (intr == -2 || intr == -3 || intr == -4) {
 507                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 508         } else {
 509                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 510                         irq->cpu, irq->irq);
 511                 return -EINVAL;
 512         }
 513
 514         dvcpu->arch.wait = 0;
 515
 516         if (swq_has_sleeper(&dvcpu->wq))
 517                 swake_up(&dvcpu->wq);
 518
 519         return 0;
 520 }
 521
 522 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 523                                     struct kvm_mp_state *mp_state)
 524 {
 525         return -ENOIOCTLCMD;
 526 }
 527
 528 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 529                                     struct kvm_mp_state *mp_state)
 530 {
 531         return -ENOIOCTLCMD;
 532 }
 533
 534 static u64 kvm_mips_get_one_regs[] = {
 535         KVM_REG_MIPS_R0,
 536         KVM_REG_MIPS_R1,
 537         KVM_REG_MIPS_R2,
 538         KVM_REG_MIPS_R3,
 539         KVM_REG_MIPS_R4,
 540         KVM_REG_MIPS_R5,
 541         KVM_REG_MIPS_R6,
 542         KVM_REG_MIPS_R7,
 543         KVM_REG_MIPS_R8,
 544         KVM_REG_MIPS_R9,
 545         KVM_REG_MIPS_R10,
 546         KVM_REG_MIPS_R11,
 547         KVM_REG_MIPS_R12,
 548         KVM_REG_MIPS_R13,
 549         KVM_REG_MIPS_R14,
 550         KVM_REG_MIPS_R15,
 551         KVM_REG_MIPS_R16,
 552         KVM_REG_MIPS_R17,
 553         KVM_REG_MIPS_R18,
 554         KVM_REG_MIPS_R19,
 555         KVM_REG_MIPS_R20,
 556         KVM_REG_MIPS_R21,
 557         KVM_REG_MIPS_R22,
 558         KVM_REG_MIPS_R23,
 559         KVM_REG_MIPS_R24,
 560         KVM_REG_MIPS_R25,
 561         KVM_REG_MIPS_R26,
 562         KVM_REG_MIPS_R27,
 563         KVM_REG_MIPS_R28,
 564         KVM_REG_MIPS_R29,
 565         KVM_REG_MIPS_R30,
 566         KVM_REG_MIPS_R31,
 567
 568 #ifndef CONFIG_CPU_MIPSR6
 569         KVM_REG_MIPS_HI,
 570         KVM_REG_MIPS_LO,
 571 #endif
 572         KVM_REG_MIPS_PC,
 573 };
 574
 575 static u64 kvm_mips_get_one_regs_fpu[] = {
 576         KVM_REG_MIPS_FCR_IR,
 577         KVM_REG_MIPS_FCR_CSR,
 578 };
 579
 580 static u64 kvm_mips_get_one_regs_msa[] = {
 581         KVM_REG_MIPS_MSA_IR,
 582         KVM_REG_MIPS_MSA_CSR,
 583 };
 584
 585 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 586 {
 587         unsigned long ret;
 588
 589         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 590         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 591                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 592                 /* odd doubles */
 593                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 594                         ret += 16;
 595         }
 596         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 597                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 598         ret += kvm_mips_callbacks->num_regs(vcpu);
 599
 600         return ret;
 601 }
 602
 603 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 604 {
 605         u64 index;
 606         unsigned int i;
 607
 608         if (copy_to_user(indices, kvm_mips_get_one_regs,
 609                          sizeof(kvm_mips_get_one_regs)))
 610                 return -EFAULT;
 611         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 612
 613         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 614                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 615                                  sizeof(kvm_mips_get_one_regs_fpu)))
 616                         return -EFAULT;
 617                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 618
 619                 for (i = 0; i < 32; ++i) {
 620                         index = KVM_REG_MIPS_FPR_32(i);
 621                         if (copy_to_user(indices, &index, sizeof(index)))
 622                                 return -EFAULT;
 623                         ++indices;
 624
 625                         /* skip odd doubles if no F64 */
 626                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 627                                 continue;
 628
 629                         index = KVM_REG_MIPS_FPR_64(i);
 630                         if (copy_to_user(indices, &index, sizeof(index)))
 631                                 return -EFAULT;
 632                         ++indices;
 633                 }
 634         }
 635
 636         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 637                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 638                                  sizeof(kvm_mips_get_one_regs_msa)))
 639                         return -EFAULT;
 640                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 641
 642                 for (i = 0; i < 32; ++i) {
 643                         index = KVM_REG_MIPS_VEC_128(i);
 644                         if (copy_to_user(indices, &index, sizeof(index)))
 645                                 return -EFAULT;
 646                         ++indices;
 647                 }
 648         }
 649
 650         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 651 }
 652
 653 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 654                             const struct kvm_one_reg *reg)
 655 {
 656         struct mips_coproc *cop0 = vcpu->arch.cop0;
 657         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 658         int ret;
 659         s64 v;
 660         s64 vs[2];
 661         unsigned int idx;
 662
 663         switch (reg->id) {
 664         /* General purpose registers */
 665         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 666                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 667                 break;
 668 #ifndef CONFIG_CPU_MIPSR6
 669         case KVM_REG_MIPS_HI:
 670                 v = (long)vcpu->arch.hi;
 671                 break;
 672         case KVM_REG_MIPS_LO:
 673                 v = (long)vcpu->arch.lo;
 674                 break;
 675 #endif
 676         case KVM_REG_MIPS_PC:
 677                 v = (long)vcpu->arch.pc;
 678                 break;
 679
 680         /* Floating point registers */
 681         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 682                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 683                         return -EINVAL;
 684                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 685                 /* Odd singles in top of even double when FR=0 */
 686                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 687                         v = get_fpr32(&fpu->fpr[idx], 0);
 688                 else
 689                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 690                 break;
 691         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 692                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 693                         return -EINVAL;
 694                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 695                 /* Can't access odd doubles in FR=0 mode */
 696                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 697                         return -EINVAL;
 698                 v = get_fpr64(&fpu->fpr[idx], 0);
 699                 break;
 700         case KVM_REG_MIPS_FCR_IR:
 701                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 702                         return -EINVAL;
 703                 v = boot_cpu_data.fpu_id;
 704                 break;
 705         case KVM_REG_MIPS_FCR_CSR:
 706                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 707                         return -EINVAL;
 708                 v = fpu->fcr31;
 709                 break;
 710
 711         /* MIPS SIMD Architecture (MSA) registers */
 712         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 713                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 714                         return -EINVAL;
 715                 /* Can't access MSA registers in FR=0 mode */
 716                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 717                         return -EINVAL;
 718                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 719 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 720                 /* least significant byte first */
 721                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 722                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 723 #else
 724                 /* most significant byte first */
 725                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 726                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 727 #endif
 728                 break;
 729         case KVM_REG_MIPS_MSA_IR:
 730                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 731                         return -EINVAL;
 732                 v = boot_cpu_data.msa_id;
 733                 break;
 734         case KVM_REG_MIPS_MSA_CSR:
 735                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 736                         return -EINVAL;
 737                 v = fpu->msacsr;
 738                 break;
 739
 740         /* registers to be handled specially */
 741         default:
 742                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 743                 if (ret)
 744                         return ret;
 745                 break;
 746         }
 747         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 748                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 749
 750                 return put_user(v, uaddr64);
 751         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 752                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 753                 u32 v32 = (u32)v;
 754
 755                 return put_user(v32, uaddr32);
 756         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 757                 void __user *uaddr = (void __user *)(long)reg->addr;
 758
 759                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 760         } else {
 761                 return -EINVAL;
 762         }
 763 }
 764
 765 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 766                             const struct kvm_one_reg *reg)
 767 {
 768         struct mips_coproc *cop0 = vcpu->arch.cop0;
 769         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 770         s64 v;
 771         s64 vs[2];
 772         unsigned int idx;
 773
 774         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 775                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 776
 777                 if (get_user(v, uaddr64) != 0)
 778                         return -EFAULT;
 779         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 780                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 781                 s32 v32;
 782
 783                 if (get_user(v32, uaddr32) != 0)
 784                         return -EFAULT;
 785                 v = (s64)v32;
 786         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 787                 void __user *uaddr = (void __user *)(long)reg->addr;
 788
 789                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 790         } else {
 791                 return -EINVAL;
 792         }
 793
 794         switch (reg->id) {
 795         /* General purpose registers */
 796         case KVM_REG_MIPS_R0:
 797                 /* Silently ignore requests to set $0 */
 798                 break;
 799         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 800                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 801                 break;
 802 #ifndef CONFIG_CPU_MIPSR6
 803         case KVM_REG_MIPS_HI:
 804                 vcpu->arch.hi = v;
 805                 break;
 806         case KVM_REG_MIPS_LO:
 807                 vcpu->arch.lo = v;
 808                 break;
 809 #endif
 810         case KVM_REG_MIPS_PC:
 811                 vcpu->arch.pc = v;
 812                 break;
 813
 814         /* Floating point registers */
 815         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 816                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 817                         return -EINVAL;
 818                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 819                 /* Odd singles in top of even double when FR=0 */
 820                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 821                         set_fpr32(&fpu->fpr[idx], 0, v);
 822                 else
 823                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 824                 break;
 825         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 826                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 827                         return -EINVAL;
 828                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 829                 /* Can't access odd doubles in FR=0 mode */
 830                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 831                         return -EINVAL;
 832                 set_fpr64(&fpu->fpr[idx], 0, v);
 833                 break;
 834         case KVM_REG_MIPS_FCR_IR:
 835                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 836                         return -EINVAL;
 837                 /* Read-only */
 838                 break;
 839         case KVM_REG_MIPS_FCR_CSR:
 840                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 841                         return -EINVAL;
 842                 fpu->fcr31 = v;
 843                 break;
 844
 845         /* MIPS SIMD Architecture (MSA) registers */
 846         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 847                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 848                         return -EINVAL;
 849                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 850 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 851                 /* least significant byte first */
 852                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 853                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 854 #else
 855                 /* most significant byte first */
 856                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 857                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 858 #endif
 859                 break;
 860         case KVM_REG_MIPS_MSA_IR:
 861                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 862                         return -EINVAL;
 863                 /* Read-only */
 864                 break;
 865         case KVM_REG_MIPS_MSA_CSR:
 866                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 867                         return -EINVAL;
 868                 fpu->msacsr = v;
 869                 break;
 870
 871         /* registers to be handled specially */
 872         default:
 873                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 874         }
 875         return 0;
 876 }
 877
 878 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 879                                      struct kvm_enable_cap *cap)
 880 {
 881         int r = 0;
 882
 883         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 884                 return -EINVAL;
 885         if (cap->flags)
 886                 return -EINVAL;
 887         if (cap->args[0])
 888                 return -EINVAL;
 889
 890         switch (cap->cap) {
 891         case KVM_CAP_MIPS_FPU:
 892                 vcpu->arch.fpu_enabled = true;
 893                 break;
 894         case KVM_CAP_MIPS_MSA:
 895                 vcpu->arch.msa_enabled = true;
 896                 break;
 897         default:
 898                 r = -EINVAL;
 899                 break;
 900         }
 901
 902         return r;
 903 }
 904
 905 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 906                          unsigned long arg)
 907 {
 908         struct kvm_vcpu *vcpu = filp->private_data;
 909         void __user *argp = (void __user *)arg;
 910         long r;
 911
 912         switch (ioctl) {
 913         case KVM_SET_ONE_REG:
 914         case KVM_GET_ONE_REG: {
 915                 struct kvm_one_reg reg;
 916
 917                 if (copy_from_user(&reg, argp, sizeof(reg)))
 918                         return -EFAULT;
 919                 if (ioctl == KVM_SET_ONE_REG)
 920                         return kvm_mips_set_reg(vcpu, &reg);
 921                 else
 922                         return kvm_mips_get_reg(vcpu, &reg);
 923         }
 924         case KVM_GET_REG_LIST: {
 925                 struct kvm_reg_list __user *user_list = argp;
 926                 struct kvm_reg_list reg_list;
 927                 unsigned n;
 928
 929                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 930                         return -EFAULT;
 931                 n = reg_list.n;
 932                 reg_list.n = kvm_mips_num_regs(vcpu);
 933                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 934                         return -EFAULT;
 935                 if (n < reg_list.n)
 936                         return -E2BIG;
 937                 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 938         }
 939         case KVM_INTERRUPT:
 940                 {
 941                         struct kvm_mips_interrupt irq;
 942
 943                         if (copy_from_user(&irq, argp, sizeof(irq)))
 944                                 return -EFAULT;
 945                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 946                                   irq.irq);
 947
 948                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 949                         break;
 950                 }
 951         case KVM_ENABLE_CAP: {
 952                 struct kvm_enable_cap cap;
 953
 954                 if (copy_from_user(&cap, argp, sizeof(cap)))
 955                         return -EFAULT;
 956                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 957                 break;
 958         }
 959         default:
 960                 r = -ENOIOCTLCMD;
 961         }
 962         return r;
 963 }
 964
 965 /**
 966  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
 967  * @kvm: kvm instance
 968  * @log: slot id and address to which we copy the log
 969  *
 970  * Steps 1-4 below provide general overview of dirty page logging. See
 971  * kvm_get_dirty_log_protect() function description for additional details.
 972  *
 973  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
 974  * always flush the TLB (step 4) even if previous step failed  and the dirty
 975  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
 976  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
 977  * writes will be marked dirty for next log read.
 978  *
 979  *   1. Take a snapshot of the bit and clear it if needed.
 980  *   2. Write protect the corresponding page.
 981  *   3. Copy the snapshot to the userspace.
 982  *   4. Flush TLB's if needed.
 983  */
 984 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 985 {
 986         struct kvm_memslots *slots;
 987         struct kvm_memory_slot *memslot;
 988         bool is_dirty = false;
 989         int r;
 990
 991         mutex_lock(&kvm->slots_lock);
 992
 993         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
 994
 995         if (is_dirty) {
 996                 slots = kvm_memslots(kvm);
 997                 memslot = id_to_memslot(slots, log->slot);
 998
 999                 /* Let implementation handle TLB/GVA invalidation */
1000                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1001         }
1002
1003         mutex_unlock(&kvm->slots_lock);
1004         return r;
1005 }
1006
1007 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1008 {
1009         long r;
1010
1011         switch (ioctl) {
1012         default:
1013                 r = -ENOIOCTLCMD;
1014         }
1015
1016         return r;
1017 }
1018
1019 int kvm_arch_init(void *opaque)
1020 {
1021         if (kvm_mips_callbacks) {
1022                 kvm_err("kvm: module already exists\n");
1023                 return -EEXIST;
1024         }
1025
1026         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1027 }
1028
1029 void kvm_arch_exit(void)
1030 {
1031         kvm_mips_callbacks = NULL;
1032 }
1033
1034 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1035                                   struct kvm_sregs *sregs)
1036 {
1037         return -ENOIOCTLCMD;
1038 }
1039
1040 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1041                                   struct kvm_sregs *sregs)
1042 {
1043         return -ENOIOCTLCMD;
1044 }
1045
1046 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1047 {
1048 }
1049
1050 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1051 {
1052         return -ENOIOCTLCMD;
1053 }
1054
1055 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1056 {
1057         return -ENOIOCTLCMD;
1058 }
1059
1060 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1061 {
1062         return VM_FAULT_SIGBUS;
1063 }
1064
1065 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1066 {
1067         int r;
1068
1069         switch (ext) {
1070         case KVM_CAP_ONE_REG:
1071         case KVM_CAP_ENABLE_CAP:
1072         case KVM_CAP_READONLY_MEM:
1073         case KVM_CAP_SYNC_MMU:
1074         case KVM_CAP_IMMEDIATE_EXIT:
1075                 r = 1;
1076                 break;
1077         case KVM_CAP_NR_VCPUS:
1078                 r = num_online_cpus();
1079                 break;
1080         case KVM_CAP_MAX_VCPUS:
1081                 r = KVM_MAX_VCPUS;
1082                 break;
1083         case KVM_CAP_MAX_VCPU_ID:
1084                 r = KVM_MAX_VCPU_ID;
1085                 break;
1086         case KVM_CAP_MIPS_FPU:
1087                 /* We don't handle systems with inconsistent cpu_has_fpu */
1088                 r = !!raw_cpu_has_fpu;
1089                 break;
1090         case KVM_CAP_MIPS_MSA:
1091                 /*
1092                  * We don't support MSA vector partitioning yet:
1093                  * 1) It would require explicit support which can't be tested
1094                  *    yet due to lack of support in current hardware.
1095                  * 2) It extends the state that would need to be saved/restored
1096                  *    by e.g. QEMU for migration.
1097                  *
1098                  * When vector partitioning hardware becomes available, support
1099                  * could be added by requiring a flag when enabling
1100                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1101                  * to save/restore the appropriate extra state.
1102                  */
1103                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1104                 break;
1105         default:
1106                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1107                 break;
1108         }
1109         return r;
1110 }
1111
1112 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1113 {
1114         return kvm_mips_pending_timer(vcpu) ||
1115                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1116 }
1117
1118 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1119 {
1120         int i;
1121         struct mips_coproc *cop0;
1122
1123         if (!vcpu)
1124                 return -1;
1125
1126         kvm_debug("VCPU Register Dump:\n");
1127         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1128         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1129
1130         for (i = 0; i < 32; i += 4) {
1131                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1132                        vcpu->arch.gprs[i],
1133                        vcpu->arch.gprs[i + 1],
1134                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1135         }
1136         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1137         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1138
1139         cop0 = vcpu->arch.cop0;
1140         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1141                   kvm_read_c0_guest_status(cop0),
1142                   kvm_read_c0_guest_cause(cop0));
1143
1144         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1145
1146         return 0;
1147 }
1148
1149 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1150 {
1151         int i;
1152
1153         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1154                 vcpu->arch.gprs[i] = regs->gpr[i];
1155         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1156         vcpu->arch.hi = regs->hi;
1157         vcpu->arch.lo = regs->lo;
1158         vcpu->arch.pc = regs->pc;
1159
1160         return 0;
1161 }
1162
1163 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1164 {
1165         int i;
1166
1167         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1168                 regs->gpr[i] = vcpu->arch.gprs[i];
1169
1170         regs->hi = vcpu->arch.hi;
1171         regs->lo = vcpu->arch.lo;
1172         regs->pc = vcpu->arch.pc;
1173
1174         return 0;
1175 }
1176
1177 static void kvm_mips_comparecount_func(unsigned long data)
1178 {
1179         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1180
1181         kvm_mips_callbacks->queue_timer_int(vcpu);
1182
1183         vcpu->arch.wait = 0;
1184         if (swq_has_sleeper(&vcpu->wq))
1185                 swake_up(&vcpu->wq);
1186 }
1187
1188 /* low level hrtimer wake routine */
1189 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1190 {
1191         struct kvm_vcpu *vcpu;
1192
1193         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1194         kvm_mips_comparecount_func((unsigned long) vcpu);
1195         return kvm_mips_count_timeout(vcpu);
1196 }
1197
1198 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1199 {
1200         int err;
1201
1202         err = kvm_mips_callbacks->vcpu_init(vcpu);
1203         if (err)
1204                 return err;
1205
1206         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1207                      HRTIMER_MODE_REL);
1208         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1209         return 0;
1210 }
1211
1212 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1213 {
1214         kvm_mips_callbacks->vcpu_uninit(vcpu);
1215 }
1216
1217 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1218                                   struct kvm_translation *tr)
1219 {
1220         return 0;
1221 }
1222
1223 /* Initial guest state */
1224 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1225 {
1226         return kvm_mips_callbacks->vcpu_setup(vcpu);
1227 }
1228
1229 static void kvm_mips_set_c0_status(void)
1230 {
1231         u32 status = read_c0_status();
1232
1233         if (cpu_has_dsp)
1234                 status |= (ST0_MX);
1235
1236         write_c0_status(status);
1237         ehb();
1238 }
1239
1240 /*
1241  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1242  */
1243 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1244 {
1245         u32 cause = vcpu->arch.host_cp0_cause;
1246         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1247         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1248         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1249         enum emulation_result er = EMULATE_DONE;
1250         u32 inst;
1251         int ret = RESUME_GUEST;
1252
1253         vcpu->mode = OUTSIDE_GUEST_MODE;
1254
1255         /* re-enable HTW before enabling interrupts */
1256         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1257                 htw_start();
1258
1259         /* Set a default exit reason */
1260         run->exit_reason = KVM_EXIT_UNKNOWN;
1261         run->ready_for_interrupt_injection = 1;
1262
1263         /*
1264          * Set the appropriate status bits based on host CPU features,
1265          * before we hit the scheduler
1266          */
1267         kvm_mips_set_c0_status();
1268
1269         local_irq_enable();
1270
1271         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1272                         cause, opc, run, vcpu);
1273         trace_kvm_exit(vcpu, exccode);
1274
1275         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1276                 /*
1277                  * Do a privilege check, if in UM most of these exit conditions
1278                  * end up causing an exception to be delivered to the Guest
1279                  * Kernel
1280                  */
1281                 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1282                 if (er == EMULATE_PRIV_FAIL) {
1283                         goto skip_emul;
1284                 } else if (er == EMULATE_FAIL) {
1285                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1286                         ret = RESUME_HOST;
1287                         goto skip_emul;
1288                 }
1289         }
1290
1291         switch (exccode) {
1292         case EXCCODE_INT:
1293                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1294
1295                 ++vcpu->stat.int_exits;
1296
1297                 if (need_resched())
1298                         cond_resched();
1299
1300                 ret = RESUME_GUEST;
1301                 break;
1302
1303         case EXCCODE_CPU:
1304                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1305
1306                 ++vcpu->stat.cop_unusable_exits;
1307                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1308                 /* XXXKYMA: Might need to return to user space */
1309                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1310                         ret = RESUME_HOST;
1311                 break;
1312
1313         case EXCCODE_MOD:
1314                 ++vcpu->stat.tlbmod_exits;
1315                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1316                 break;
1317
1318         case EXCCODE_TLBS:
1319                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1320                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1321                           badvaddr);
1322
1323                 ++vcpu->stat.tlbmiss_st_exits;
1324                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1325                 break;
1326
1327         case EXCCODE_TLBL:
1328                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1329                           cause, opc, badvaddr);
1330
1331                 ++vcpu->stat.tlbmiss_ld_exits;
1332                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1333                 break;
1334
1335         case EXCCODE_ADES:
1336                 ++vcpu->stat.addrerr_st_exits;
1337                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1338                 break;
1339
1340         case EXCCODE_ADEL:
1341                 ++vcpu->stat.addrerr_ld_exits;
1342                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1343                 break;
1344
1345         case EXCCODE_SYS:
1346                 ++vcpu->stat.syscall_exits;
1347                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1348                 break;
1349
1350         case EXCCODE_RI:
1351                 ++vcpu->stat.resvd_inst_exits;
1352                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1353                 break;
1354
1355         case EXCCODE_BP:
1356                 ++vcpu->stat.break_inst_exits;
1357                 ret = kvm_mips_callbacks->handle_break(vcpu);
1358                 break;
1359
1360         case EXCCODE_TR:
1361                 ++vcpu->stat.trap_inst_exits;
1362                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1363                 break;
1364
1365         case EXCCODE_MSAFPE:
1366                 ++vcpu->stat.msa_fpe_exits;
1367                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1368                 break;
1369
1370         case EXCCODE_FPE:
1371                 ++vcpu->stat.fpe_exits;
1372                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1373                 break;
1374
1375         case EXCCODE_MSADIS:
1376                 ++vcpu->stat.msa_disabled_exits;
1377                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1378                 break;
1379
1380         case EXCCODE_GE:
1381                 /* defer exit accounting to handler */
1382                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1383                 break;
1384
1385         default:
1386                 if (cause & CAUSEF_BD)
1387                         opc += 1;
1388                 inst = 0;
1389                 kvm_get_badinstr(opc, vcpu, &inst);
1390                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1391                         exccode, opc, inst, badvaddr,
1392                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1393                 kvm_arch_vcpu_dump_regs(vcpu);
1394                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1395                 ret = RESUME_HOST;
1396                 break;
1397
1398         }
1399
1400 skip_emul:
1401         local_irq_disable();
1402
1403         if (ret == RESUME_GUEST)
1404                 kvm_vz_acquire_htimer(vcpu);
1405
1406         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1407                 kvm_mips_deliver_interrupts(vcpu, cause);
1408
1409         if (!(ret & RESUME_HOST)) {
1410                 /* Only check for signals if not already exiting to userspace */
1411                 if (signal_pending(current)) {
1412                         run->exit_reason = KVM_EXIT_INTR;
1413                         ret = (-EINTR << 2) | RESUME_HOST;
1414                         ++vcpu->stat.signal_exits;
1415                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1416                 }
1417         }
1418
1419         if (ret == RESUME_GUEST) {
1420                 trace_kvm_reenter(vcpu);
1421
1422                 /*
1423                  * Make sure the read of VCPU requests in vcpu_reenter()
1424                  * callback is not reordered ahead of the write to vcpu->mode,
1425                  * or we could miss a TLB flush request while the requester sees
1426                  * the VCPU as outside of guest mode and not needing an IPI.
1427                  */
1428                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1429
1430                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1431
1432                 /*
1433                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1434                  * is live), restore FCR31 / MSACSR.
1435                  *
1436                  * This should be before returning to the guest exception
1437                  * vector, as it may well cause an [MSA] FP exception if there
1438                  * are pending exception bits unmasked. (see
1439                  * kvm_mips_csr_die_notifier() for how that is handled).
1440                  */
1441                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1442                     read_c0_status() & ST0_CU1)
1443                         __kvm_restore_fcsr(&vcpu->arch);
1444
1445                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1446                     read_c0_config5() & MIPS_CONF5_MSAEN)
1447                         __kvm_restore_msacsr(&vcpu->arch);
1448         }
1449
1450         /* Disable HTW before returning to guest or host */
1451         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1452                 htw_stop();
1453
1454         return ret;
1455 }
1456
1457 /* Enable FPU for guest and restore context */
1458 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1459 {
1460         struct mips_coproc *cop0 = vcpu->arch.cop0;
1461         unsigned int sr, cfg5;
1462
1463         preempt_disable();
1464
1465         sr = kvm_read_c0_guest_status(cop0);
1466
1467         /*
1468          * If MSA state is already live, it is undefined how it interacts with
1469          * FR=0 FPU state, and we don't want to hit reserved instruction
1470          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1471          * play it safe and save it first.
1472          *
1473          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1474          * get called when guest CU1 is set, however we can't trust the guest
1475          * not to clobber the status register directly via the commpage.
1476          */
1477         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1478             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1479                 kvm_lose_fpu(vcpu);
1480
1481         /*
1482          * Enable FPU for guest
1483          * We set FR and FRE according to guest context
1484          */
1485         change_c0_status(ST0_CU1 | ST0_FR, sr);
1486         if (cpu_has_fre) {
1487                 cfg5 = kvm_read_c0_guest_config5(cop0);
1488                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1489         }
1490         enable_fpu_hazard();
1491
1492         /* If guest FPU state not active, restore it now */
1493         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1494                 __kvm_restore_fpu(&vcpu->arch);
1495                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1496                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1497         } else {
1498                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1499         }
1500
1501         preempt_enable();
1502 }
1503
1504 #ifdef CONFIG_CPU_HAS_MSA
1505 /* Enable MSA for guest and restore context */
1506 void kvm_own_msa(struct kvm_vcpu *vcpu)
1507 {
1508         struct mips_coproc *cop0 = vcpu->arch.cop0;
1509         unsigned int sr, cfg5;
1510
1511         preempt_disable();
1512
1513         /*
1514          * Enable FPU if enabled in guest, since we're restoring FPU context
1515          * anyway. We set FR and FRE according to guest context.
1516          */
1517         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1518                 sr = kvm_read_c0_guest_status(cop0);
1519
1520                 /*
1521                  * If FR=0 FPU state is already live, it is undefined how it
1522                  * interacts with MSA state, so play it safe and save it first.
1523                  */
1524                 if (!(sr & ST0_FR) &&
1525                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1526                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1527                         kvm_lose_fpu(vcpu);
1528
1529                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1530                 if (sr & ST0_CU1 && cpu_has_fre) {
1531                         cfg5 = kvm_read_c0_guest_config5(cop0);
1532                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1533                 }
1534         }
1535
1536         /* Enable MSA for guest */
1537         set_c0_config5(MIPS_CONF5_MSAEN);
1538         enable_fpu_hazard();
1539
1540         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1541         case KVM_MIPS_AUX_FPU:
1542                 /*
1543                  * Guest FPU state already loaded, only restore upper MSA state
1544                  */
1545                 __kvm_restore_msa_upper(&vcpu->arch);
1546                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1547                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1548                 break;
1549         case 0:
1550                 /* Neither FPU or MSA already active, restore full MSA state */
1551                 __kvm_restore_msa(&vcpu->arch);
1552                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1553                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1554                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1555                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1556                               KVM_TRACE_AUX_FPU_MSA);
1557                 break;
1558         default:
1559                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1560                 break;
1561         }
1562
1563         preempt_enable();
1564 }
1565 #endif
1566
1567 /* Drop FPU & MSA without saving it */
1568 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1569 {
1570         preempt_disable();
1571         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1572                 disable_msa();
1573                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1574                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1575         }
1576         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1577                 clear_c0_status(ST0_CU1 | ST0_FR);
1578                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1579                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1580         }
1581         preempt_enable();
1582 }
1583
1584 /* Save and disable FPU & MSA */
1585 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1586 {
1587         /*
1588          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1589          * is disabled in guest context (software), but the register state in
1590          * the hardware may still be in use.
1591          * This is why we explicitly re-enable the hardware before saving.
1592          */
1593
1594         preempt_disable();
1595         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1596                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1597                         set_c0_config5(MIPS_CONF5_MSAEN);
1598                         enable_fpu_hazard();
1599                 }
1600
1601                 __kvm_save_msa(&vcpu->arch);
1602                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1603
1604                 /* Disable MSA & FPU */
1605                 disable_msa();
1606                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1607                         clear_c0_status(ST0_CU1 | ST0_FR);
1608                         disable_fpu_hazard();
1609                 }
1610                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1611         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1612                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1613                         set_c0_status(ST0_CU1);
1614                         enable_fpu_hazard();
1615                 }
1616
1617                 __kvm_save_fpu(&vcpu->arch);
1618                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1619                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1620
1621                 /* Disable FPU */
1622                 clear_c0_status(ST0_CU1 | ST0_FR);
1623                 disable_fpu_hazard();
1624         }
1625         preempt_enable();
1626 }
1627
1628 /*
1629  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1630  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1631  * exception if cause bits are set in the value being written.
1632  */
1633 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1634                                    unsigned long cmd, void *ptr)
1635 {
1636         struct die_args *args = (struct die_args *)ptr;
1637         struct pt_regs *regs = args->regs;
1638         unsigned long pc;
1639
1640         /* Only interested in FPE and MSAFPE */
1641         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1642                 return NOTIFY_DONE;
1643
1644         /* Return immediately if guest context isn't active */
1645         if (!(current->flags & PF_VCPU))
1646                 return NOTIFY_DONE;
1647
1648         /* Should never get here from user mode */
1649         BUG_ON(user_mode(regs));
1650
1651         pc = instruction_pointer(regs);
1652         switch (cmd) {
1653         case DIE_FP:
1654                 /* match 2nd instruction in __kvm_restore_fcsr */
1655                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1656                         return NOTIFY_DONE;
1657                 break;
1658         case DIE_MSAFP:
1659                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1660                 if (!cpu_has_msa ||
1661                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1662                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1663                         return NOTIFY_DONE;
1664                 break;
1665         }
1666
1667         /* Move PC forward a little and continue executing */
1668         instruction_pointer(regs) += 4;
1669
1670         return NOTIFY_STOP;
1671 }
1672
1673 static struct notifier_block kvm_mips_csr_die_notifier = {
1674         .notifier_call = kvm_mips_csr_die_notify,
1675 };
1676
1677 static int __init kvm_mips_init(void)
1678 {
1679         int ret;
1680
1681         ret = kvm_mips_entry_setup();
1682         if (ret)
1683                 return ret;
1684
1685         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1686
1687         if (ret)
1688                 return ret;
1689
1690         register_die_notifier(&kvm_mips_csr_die_notifier);
1691
1692         return 0;
1693 }
1694
1695 static void __exit kvm_mips_exit(void)
1696 {
1697         kvm_exit();
1698
1699         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1700 }
1701
1702 module_init(kvm_mips_init);
1703 module_exit(kvm_mips_exit);
1704
1705 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);