arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/fpu.h>
  24 #include <asm/page.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/pgtable.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33 #include "commpage.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "trace.h"
  37
  38 #ifndef VECTORSPACING
  39 #define VECTORSPACING 0x100     /* for EI/VI mode */
  40 #endif
  41
  42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  43 struct kvm_stats_debugfs_item debugfs_entries[] = {
  44         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  45         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  46         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  47         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  48         { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  49         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  50         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  51         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  52         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  53         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  54         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  55         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  56         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  57         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  58         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  59         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  60         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  61         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  62 #ifdef CONFIG_KVM_MIPS_VZ
  63         { "vz_gpsi",      VCPU_STAT(vz_gpsi_exits),      KVM_STAT_VCPU },
  64         { "vz_gsfc",      VCPU_STAT(vz_gsfc_exits),      KVM_STAT_VCPU },
  65         { "vz_hc",        VCPU_STAT(vz_hc_exits),        KVM_STAT_VCPU },
  66         { "vz_grr",       VCPU_STAT(vz_grr_exits),       KVM_STAT_VCPU },
  67         { "vz_gva",       VCPU_STAT(vz_gva_exits),       KVM_STAT_VCPU },
  68         { "vz_ghfc",      VCPU_STAT(vz_ghfc_exits),      KVM_STAT_VCPU },
  69         { "vz_gpa",       VCPU_STAT(vz_gpa_exits),       KVM_STAT_VCPU },
  70         { "vz_resvd",     VCPU_STAT(vz_resvd_exits),     KVM_STAT_VCPU },
  71 #endif
  72         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  73         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  74         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  75         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  76         {NULL}
  77 };
  78
  79 bool kvm_trace_guest_mode_change;
  80
  81 int kvm_guest_mode_change_trace_reg(void)
  82 {
  83         kvm_trace_guest_mode_change = 1;
  84         return 0;
  85 }
  86
  87 void kvm_guest_mode_change_trace_unreg(void)
  88 {
  89         kvm_trace_guest_mode_change = 0;
  90 }
  91
  92 /*
  93  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  94  * Config7, so we are "runnable" if interrupts are pending
  95  */
  96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  97 {
  98         return !!(vcpu->arch.pending_exceptions);
  99 }
 100
 101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 102 {
 103         return false;
 104 }
 105
 106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 107 {
 108         return 1;
 109 }
 110
 111 int kvm_arch_hardware_enable(void)
 112 {
 113         return kvm_mips_callbacks->hardware_enable();
 114 }
 115
 116 void kvm_arch_hardware_disable(void)
 117 {
 118         kvm_mips_callbacks->hardware_disable();
 119 }
 120
 121 int kvm_arch_hardware_setup(void)
 122 {
 123         return 0;
 124 }
 125
 126 void kvm_arch_check_processor_compat(void *rtn)
 127 {
 128         *(int *)rtn = 0;
 129 }
 130
 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 132 {
 133         switch (type) {
 134         case KVM_VM_MIPS_AUTO:
 135                 break;
 136 #ifdef CONFIG_KVM_MIPS_VZ
 137         case KVM_VM_MIPS_VZ:
 138 #else
 139         case KVM_VM_MIPS_TE:
 140 #endif
 141                 break;
 142         default:
 143                 /* Unsupported KVM type */
 144                 return -EINVAL;
 145         };
 146
 147         /* Allocate page table to map GPA -> RPA */
 148         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 149         if (!kvm->arch.gpa_mm.pgd)
 150                 return -ENOMEM;
 151
 152         return 0;
 153 }
 154
 155 bool kvm_arch_has_vcpu_debugfs(void)
 156 {
 157         return false;
 158 }
 159
 160 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
 161 {
 162         return 0;
 163 }
 164
 165 void kvm_mips_free_vcpus(struct kvm *kvm)
 166 {
 167         unsigned int i;
 168         struct kvm_vcpu *vcpu;
 169
 170         kvm_for_each_vcpu(i, vcpu, kvm) {
 171                 kvm_arch_vcpu_free(vcpu);
 172         }
 173
 174         mutex_lock(&kvm->lock);
 175
 176         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 177                 kvm->vcpus[i] = NULL;
 178
 179         atomic_set(&kvm->online_vcpus, 0);
 180
 181         mutex_unlock(&kvm->lock);
 182 }
 183
 184 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 185 {
 186         /* It should always be safe to remove after flushing the whole range */
 187         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 188         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 189 }
 190
 191 void kvm_arch_destroy_vm(struct kvm *kvm)
 192 {
 193         kvm_mips_free_vcpus(kvm);
 194         kvm_mips_free_gpa_pt(kvm);
 195 }
 196
 197 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 198                         unsigned long arg)
 199 {
 200         return -ENOIOCTLCMD;
 201 }
 202
 203 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 204                             unsigned long npages)
 205 {
 206         return 0;
 207 }
 208
 209 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 210 {
 211         /* Flush whole GPA */
 212         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 213
 214         /* Let implementation do the rest */
 215         kvm_mips_callbacks->flush_shadow_all(kvm);
 216 }
 217
 218 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 219                                    struct kvm_memory_slot *slot)
 220 {
 221         /*
 222          * The slot has been made invalid (ready for moving or deletion), so we
 223          * need to ensure that it can no longer be accessed by any guest VCPUs.
 224          */
 225
 226         spin_lock(&kvm->mmu_lock);
 227         /* Flush slot from GPA */
 228         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 229                               slot->base_gfn + slot->npages - 1);
 230         /* Let implementation do the rest */
 231         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 232         spin_unlock(&kvm->mmu_lock);
 233 }
 234
 235 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 236                                    struct kvm_memory_slot *memslot,
 237                                    const struct kvm_userspace_memory_region *mem,
 238                                    enum kvm_mr_change change)
 239 {
 240         return 0;
 241 }
 242
 243 void kvm_arch_commit_memory_region(struct kvm *kvm,
 244                                    const struct kvm_userspace_memory_region *mem,
 245                                    const struct kvm_memory_slot *old,
 246                                    const struct kvm_memory_slot *new,
 247                                    enum kvm_mr_change change)
 248 {
 249         int needs_flush;
 250
 251         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 252                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 253                   mem->memory_size, mem->userspace_addr);
 254
 255         /*
 256          * If dirty page logging is enabled, write protect all pages in the slot
 257          * ready for dirty logging.
 258          *
 259          * There is no need to do this in any of the following cases:
 260          * CREATE:      No dirty mappings will already exist.
 261          * MOVE/DELETE: The old mappings will already have been cleaned up by
 262          *              kvm_arch_flush_shadow_memslot()
 263          */
 264         if (change == KVM_MR_FLAGS_ONLY &&
 265             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 266              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 267                 spin_lock(&kvm->mmu_lock);
 268                 /* Write protect GPA page table entries */
 269                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 270                                         new->base_gfn + new->npages - 1);
 271                 /* Let implementation do the rest */
 272                 if (needs_flush)
 273                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 274                 spin_unlock(&kvm->mmu_lock);
 275         }
 276 }
 277
 278 static inline void dump_handler(const char *symbol, void *start, void *end)
 279 {
 280         u32 *p;
 281
 282         pr_debug("LEAF(%s)\n", symbol);
 283
 284         pr_debug("\t.set push\n");
 285         pr_debug("\t.set noreorder\n");
 286
 287         for (p = start; p < (u32 *)end; ++p)
 288                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 289
 290         pr_debug("\t.set\tpop\n");
 291
 292         pr_debug("\tEND(%s)\n", symbol);
 293 }
 294
 295 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 296 {
 297         int err, size;
 298         void *gebase, *p, *handler, *refill_start, *refill_end;
 299         int i;
 300
 301         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 302
 303         if (!vcpu) {
 304                 err = -ENOMEM;
 305                 goto out;
 306         }
 307
 308         err = kvm_vcpu_init(vcpu, kvm, id);
 309
 310         if (err)
 311                 goto out_free_cpu;
 312
 313         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 314
 315         /*
 316          * Allocate space for host mode exception handlers that handle
 317          * guest mode exits
 318          */
 319         if (cpu_has_veic || cpu_has_vint)
 320                 size = 0x200 + VECTORSPACING * 64;
 321         else
 322                 size = 0x4000;
 323
 324         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 325
 326         if (!gebase) {
 327                 err = -ENOMEM;
 328                 goto out_uninit_cpu;
 329         }
 330         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 331                   ALIGN(size, PAGE_SIZE), gebase);
 332
 333         /*
 334          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 335          * limits us to the low 512MB of physical address space. If the memory
 336          * we allocate is out of range, just give up now.
 337          */
 338         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 339                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 340                         gebase);
 341                 err = -ENOMEM;
 342                 goto out_free_gebase;
 343         }
 344
 345         /* Save new ebase */
 346         vcpu->arch.guest_ebase = gebase;
 347
 348         /* Build guest exception vectors dynamically in unmapped memory */
 349         handler = gebase + 0x2000;
 350
 351         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 352         refill_start = gebase;
 353         if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
 354                 refill_start += 0x080;
 355         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 356
 357         /* General Exception Entry point */
 358         kvm_mips_build_exception(gebase + 0x180, handler);
 359
 360         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 361         for (i = 0; i < 8; i++) {
 362                 kvm_debug("L1 Vectored handler @ %p\n",
 363                           gebase + 0x200 + (i * VECTORSPACING));
 364                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 365                                          handler);
 366         }
 367
 368         /* General exit handler */
 369         p = handler;
 370         p = kvm_mips_build_exit(p);
 371
 372         /* Guest entry routine */
 373         vcpu->arch.vcpu_run = p;
 374         p = kvm_mips_build_vcpu_run(p);
 375
 376         /* Dump the generated code */
 377         pr_debug("#include <asm/asm.h>\n");
 378         pr_debug("#include <asm/regdef.h>\n");
 379         pr_debug("\n");
 380         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 381         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 382         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 383         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 384
 385         /* Invalidate the icache for these ranges */
 386         flush_icache_range((unsigned long)gebase,
 387                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 388
 389         /*
 390          * Allocate comm page for guest kernel, a TLB will be reserved for
 391          * mapping GVA @ 0xFFFF8000 to this page
 392          */
 393         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 394
 395         if (!vcpu->arch.kseg0_commpage) {
 396                 err = -ENOMEM;
 397                 goto out_free_gebase;
 398         }
 399
 400         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 401         kvm_mips_commpage_init(vcpu);
 402
 403         /* Init */
 404         vcpu->arch.last_sched_cpu = -1;
 405         vcpu->arch.last_exec_cpu = -1;
 406
 407         return vcpu;
 408
 409 out_free_gebase:
 410         kfree(gebase);
 411
 412 out_uninit_cpu:
 413         kvm_vcpu_uninit(vcpu);
 414
 415 out_free_cpu:
 416         kfree(vcpu);
 417
 418 out:
 419         return ERR_PTR(err);
 420 }
 421
 422 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 423 {
 424         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 425
 426         kvm_vcpu_uninit(vcpu);
 427
 428         kvm_mips_dump_stats(vcpu);
 429
 430         kvm_mmu_free_memory_caches(vcpu);
 431         kfree(vcpu->arch.guest_ebase);
 432         kfree(vcpu->arch.kseg0_commpage);
 433         kfree(vcpu);
 434 }
 435
 436 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 437 {
 438         kvm_arch_vcpu_free(vcpu);
 439 }
 440
 441 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 442                                         struct kvm_guest_debug *dbg)
 443 {
 444         return -ENOIOCTLCMD;
 445 }
 446
 447 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 448 {
 449         int r = -EINTR;
 450
 451         vcpu_load(vcpu);
 452
 453         kvm_sigset_activate(vcpu);
 454
 455         if (vcpu->mmio_needed) {
 456                 if (!vcpu->mmio_is_write)
 457                         kvm_mips_complete_mmio_load(vcpu, run);
 458                 vcpu->mmio_needed = 0;
 459         }
 460
 461         if (run->immediate_exit)
 462                 goto out;
 463
 464         lose_fpu(1);
 465
 466         local_irq_disable();
 467         guest_enter_irqoff();
 468         trace_kvm_enter(vcpu);
 469
 470         /*
 471          * Make sure the read of VCPU requests in vcpu_run() callback is not
 472          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 473          * flush request while the requester sees the VCPU as outside of guest
 474          * mode and not needing an IPI.
 475          */
 476         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 477
 478         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 479
 480         trace_kvm_out(vcpu);
 481         guest_exit_irqoff();
 482         local_irq_enable();
 483
 484 out:
 485         kvm_sigset_deactivate(vcpu);
 486
 487         vcpu_put(vcpu);
 488         return r;
 489 }
 490
 491 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 492                              struct kvm_mips_interrupt *irq)
 493 {
 494         int intr = (int)irq->irq;
 495         struct kvm_vcpu *dvcpu = NULL;
 496
 497         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 498                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 499                           (int)intr);
 500
 501         if (irq->cpu == -1)
 502                 dvcpu = vcpu;
 503         else
 504                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 505
 506         if (intr == 2 || intr == 3 || intr == 4) {
 507                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 508
 509         } else if (intr == -2 || intr == -3 || intr == -4) {
 510                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 511         } else {
 512                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 513                         irq->cpu, irq->irq);
 514                 return -EINVAL;
 515         }
 516
 517         dvcpu->arch.wait = 0;
 518
 519         if (swq_has_sleeper(&dvcpu->wq))
 520                 swake_up_one(&dvcpu->wq);
 521
 522         return 0;
 523 }
 524
 525 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 526                                     struct kvm_mp_state *mp_state)
 527 {
 528         return -ENOIOCTLCMD;
 529 }
 530
 531 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 532                                     struct kvm_mp_state *mp_state)
 533 {
 534         return -ENOIOCTLCMD;
 535 }
 536
 537 static u64 kvm_mips_get_one_regs[] = {
 538         KVM_REG_MIPS_R0,
 539         KVM_REG_MIPS_R1,
 540         KVM_REG_MIPS_R2,
 541         KVM_REG_MIPS_R3,
 542         KVM_REG_MIPS_R4,
 543         KVM_REG_MIPS_R5,
 544         KVM_REG_MIPS_R6,
 545         KVM_REG_MIPS_R7,
 546         KVM_REG_MIPS_R8,
 547         KVM_REG_MIPS_R9,
 548         KVM_REG_MIPS_R10,
 549         KVM_REG_MIPS_R11,
 550         KVM_REG_MIPS_R12,
 551         KVM_REG_MIPS_R13,
 552         KVM_REG_MIPS_R14,
 553         KVM_REG_MIPS_R15,
 554         KVM_REG_MIPS_R16,
 555         KVM_REG_MIPS_R17,
 556         KVM_REG_MIPS_R18,
 557         KVM_REG_MIPS_R19,
 558         KVM_REG_MIPS_R20,
 559         KVM_REG_MIPS_R21,
 560         KVM_REG_MIPS_R22,
 561         KVM_REG_MIPS_R23,
 562         KVM_REG_MIPS_R24,
 563         KVM_REG_MIPS_R25,
 564         KVM_REG_MIPS_R26,
 565         KVM_REG_MIPS_R27,
 566         KVM_REG_MIPS_R28,
 567         KVM_REG_MIPS_R29,
 568         KVM_REG_MIPS_R30,
 569         KVM_REG_MIPS_R31,
 570
 571 #ifndef CONFIG_CPU_MIPSR6
 572         KVM_REG_MIPS_HI,
 573         KVM_REG_MIPS_LO,
 574 #endif
 575         KVM_REG_MIPS_PC,
 576 };
 577
 578 static u64 kvm_mips_get_one_regs_fpu[] = {
 579         KVM_REG_MIPS_FCR_IR,
 580         KVM_REG_MIPS_FCR_CSR,
 581 };
 582
 583 static u64 kvm_mips_get_one_regs_msa[] = {
 584         KVM_REG_MIPS_MSA_IR,
 585         KVM_REG_MIPS_MSA_CSR,
 586 };
 587
 588 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 589 {
 590         unsigned long ret;
 591
 592         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 593         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 594                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 595                 /* odd doubles */
 596                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 597                         ret += 16;
 598         }
 599         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 600                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 601         ret += kvm_mips_callbacks->num_regs(vcpu);
 602
 603         return ret;
 604 }
 605
 606 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 607 {
 608         u64 index;
 609         unsigned int i;
 610
 611         if (copy_to_user(indices, kvm_mips_get_one_regs,
 612                          sizeof(kvm_mips_get_one_regs)))
 613                 return -EFAULT;
 614         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 615
 616         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 617                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 618                                  sizeof(kvm_mips_get_one_regs_fpu)))
 619                         return -EFAULT;
 620                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 621
 622                 for (i = 0; i < 32; ++i) {
 623                         index = KVM_REG_MIPS_FPR_32(i);
 624                         if (copy_to_user(indices, &index, sizeof(index)))
 625                                 return -EFAULT;
 626                         ++indices;
 627
 628                         /* skip odd doubles if no F64 */
 629                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 630                                 continue;
 631
 632                         index = KVM_REG_MIPS_FPR_64(i);
 633                         if (copy_to_user(indices, &index, sizeof(index)))
 634                                 return -EFAULT;
 635                         ++indices;
 636                 }
 637         }
 638
 639         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 640                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 641                                  sizeof(kvm_mips_get_one_regs_msa)))
 642                         return -EFAULT;
 643                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 644
 645                 for (i = 0; i < 32; ++i) {
 646                         index = KVM_REG_MIPS_VEC_128(i);
 647                         if (copy_to_user(indices, &index, sizeof(index)))
 648                                 return -EFAULT;
 649                         ++indices;
 650                 }
 651         }
 652
 653         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 654 }
 655
 656 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 657                             const struct kvm_one_reg *reg)
 658 {
 659         struct mips_coproc *cop0 = vcpu->arch.cop0;
 660         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 661         int ret;
 662         s64 v;
 663         s64 vs[2];
 664         unsigned int idx;
 665
 666         switch (reg->id) {
 667         /* General purpose registers */
 668         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 669                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 670                 break;
 671 #ifndef CONFIG_CPU_MIPSR6
 672         case KVM_REG_MIPS_HI:
 673                 v = (long)vcpu->arch.hi;
 674                 break;
 675         case KVM_REG_MIPS_LO:
 676                 v = (long)vcpu->arch.lo;
 677                 break;
 678 #endif
 679         case KVM_REG_MIPS_PC:
 680                 v = (long)vcpu->arch.pc;
 681                 break;
 682
 683         /* Floating point registers */
 684         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 685                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 686                         return -EINVAL;
 687                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 688                 /* Odd singles in top of even double when FR=0 */
 689                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 690                         v = get_fpr32(&fpu->fpr[idx], 0);
 691                 else
 692                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 693                 break;
 694         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 695                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 696                         return -EINVAL;
 697                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 698                 /* Can't access odd doubles in FR=0 mode */
 699                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 700                         return -EINVAL;
 701                 v = get_fpr64(&fpu->fpr[idx], 0);
 702                 break;
 703         case KVM_REG_MIPS_FCR_IR:
 704                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 705                         return -EINVAL;
 706                 v = boot_cpu_data.fpu_id;
 707                 break;
 708         case KVM_REG_MIPS_FCR_CSR:
 709                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 710                         return -EINVAL;
 711                 v = fpu->fcr31;
 712                 break;
 713
 714         /* MIPS SIMD Architecture (MSA) registers */
 715         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 716                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 717                         return -EINVAL;
 718                 /* Can't access MSA registers in FR=0 mode */
 719                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 720                         return -EINVAL;
 721                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 722 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 723                 /* least significant byte first */
 724                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 725                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 726 #else
 727                 /* most significant byte first */
 728                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 729                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 730 #endif
 731                 break;
 732         case KVM_REG_MIPS_MSA_IR:
 733                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 734                         return -EINVAL;
 735                 v = boot_cpu_data.msa_id;
 736                 break;
 737         case KVM_REG_MIPS_MSA_CSR:
 738                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 739                         return -EINVAL;
 740                 v = fpu->msacsr;
 741                 break;
 742
 743         /* registers to be handled specially */
 744         default:
 745                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 746                 if (ret)
 747                         return ret;
 748                 break;
 749         }
 750         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 751                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 752
 753                 return put_user(v, uaddr64);
 754         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 755                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 756                 u32 v32 = (u32)v;
 757
 758                 return put_user(v32, uaddr32);
 759         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 760                 void __user *uaddr = (void __user *)(long)reg->addr;
 761
 762                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 763         } else {
 764                 return -EINVAL;
 765         }
 766 }
 767
 768 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 769                             const struct kvm_one_reg *reg)
 770 {
 771         struct mips_coproc *cop0 = vcpu->arch.cop0;
 772         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 773         s64 v;
 774         s64 vs[2];
 775         unsigned int idx;
 776
 777         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 778                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 779
 780                 if (get_user(v, uaddr64) != 0)
 781                         return -EFAULT;
 782         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 783                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 784                 s32 v32;
 785
 786                 if (get_user(v32, uaddr32) != 0)
 787                         return -EFAULT;
 788                 v = (s64)v32;
 789         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 790                 void __user *uaddr = (void __user *)(long)reg->addr;
 791
 792                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 793         } else {
 794                 return -EINVAL;
 795         }
 796
 797         switch (reg->id) {
 798         /* General purpose registers */
 799         case KVM_REG_MIPS_R0:
 800                 /* Silently ignore requests to set $0 */
 801                 break;
 802         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 803                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 804                 break;
 805 #ifndef CONFIG_CPU_MIPSR6
 806         case KVM_REG_MIPS_HI:
 807                 vcpu->arch.hi = v;
 808                 break;
 809         case KVM_REG_MIPS_LO:
 810                 vcpu->arch.lo = v;
 811                 break;
 812 #endif
 813         case KVM_REG_MIPS_PC:
 814                 vcpu->arch.pc = v;
 815                 break;
 816
 817         /* Floating point registers */
 818         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 819                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 820                         return -EINVAL;
 821                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 822                 /* Odd singles in top of even double when FR=0 */
 823                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 824                         set_fpr32(&fpu->fpr[idx], 0, v);
 825                 else
 826                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 827                 break;
 828         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 829                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 830                         return -EINVAL;
 831                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 832                 /* Can't access odd doubles in FR=0 mode */
 833                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 834                         return -EINVAL;
 835                 set_fpr64(&fpu->fpr[idx], 0, v);
 836                 break;
 837         case KVM_REG_MIPS_FCR_IR:
 838                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 839                         return -EINVAL;
 840                 /* Read-only */
 841                 break;
 842         case KVM_REG_MIPS_FCR_CSR:
 843                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 844                         return -EINVAL;
 845                 fpu->fcr31 = v;
 846                 break;
 847
 848         /* MIPS SIMD Architecture (MSA) registers */
 849         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 850                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 851                         return -EINVAL;
 852                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 853 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 854                 /* least significant byte first */
 855                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 856                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 857 #else
 858                 /* most significant byte first */
 859                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 860                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 861 #endif
 862                 break;
 863         case KVM_REG_MIPS_MSA_IR:
 864                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 865                         return -EINVAL;
 866                 /* Read-only */
 867                 break;
 868         case KVM_REG_MIPS_MSA_CSR:
 869                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 870                         return -EINVAL;
 871                 fpu->msacsr = v;
 872                 break;
 873
 874         /* registers to be handled specially */
 875         default:
 876                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 877         }
 878         return 0;
 879 }
 880
 881 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 882                                      struct kvm_enable_cap *cap)
 883 {
 884         int r = 0;
 885
 886         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 887                 return -EINVAL;
 888         if (cap->flags)
 889                 return -EINVAL;
 890         if (cap->args[0])
 891                 return -EINVAL;
 892
 893         switch (cap->cap) {
 894         case KVM_CAP_MIPS_FPU:
 895                 vcpu->arch.fpu_enabled = true;
 896                 break;
 897         case KVM_CAP_MIPS_MSA:
 898                 vcpu->arch.msa_enabled = true;
 899                 break;
 900         default:
 901                 r = -EINVAL;
 902                 break;
 903         }
 904
 905         return r;
 906 }
 907
 908 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
 909                                unsigned long arg)
 910 {
 911         struct kvm_vcpu *vcpu = filp->private_data;
 912         void __user *argp = (void __user *)arg;
 913
 914         if (ioctl == KVM_INTERRUPT) {
 915                 struct kvm_mips_interrupt irq;
 916
 917                 if (copy_from_user(&irq, argp, sizeof(irq)))
 918                         return -EFAULT;
 919                 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 920                           irq.irq);
 921
 922                 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 923         }
 924
 925         return -ENOIOCTLCMD;
 926 }
 927
 928 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 929                          unsigned long arg)
 930 {
 931         struct kvm_vcpu *vcpu = filp->private_data;
 932         void __user *argp = (void __user *)arg;
 933         long r;
 934
 935         vcpu_load(vcpu);
 936
 937         switch (ioctl) {
 938         case KVM_SET_ONE_REG:
 939         case KVM_GET_ONE_REG: {
 940                 struct kvm_one_reg reg;
 941
 942                 r = -EFAULT;
 943                 if (copy_from_user(&reg, argp, sizeof(reg)))
 944                         break;
 945                 if (ioctl == KVM_SET_ONE_REG)
 946                         r = kvm_mips_set_reg(vcpu, &reg);
 947                 else
 948                         r = kvm_mips_get_reg(vcpu, &reg);
 949                 break;
 950         }
 951         case KVM_GET_REG_LIST: {
 952                 struct kvm_reg_list __user *user_list = argp;
 953                 struct kvm_reg_list reg_list;
 954                 unsigned n;
 955
 956                 r = -EFAULT;
 957                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 958                         break;
 959                 n = reg_list.n;
 960                 reg_list.n = kvm_mips_num_regs(vcpu);
 961                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 962                         break;
 963                 r = -E2BIG;
 964                 if (n < reg_list.n)
 965                         break;
 966                 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 967                 break;
 968         }
 969         case KVM_ENABLE_CAP: {
 970                 struct kvm_enable_cap cap;
 971
 972                 r = -EFAULT;
 973                 if (copy_from_user(&cap, argp, sizeof(cap)))
 974                         break;
 975                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 976                 break;
 977         }
 978         default:
 979                 r = -ENOIOCTLCMD;
 980         }
 981
 982         vcpu_put(vcpu);
 983         return r;
 984 }
 985
 986 /**
 987  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
 988  * @kvm: kvm instance
 989  * @log: slot id and address to which we copy the log
 990  *
 991  * Steps 1-4 below provide general overview of dirty page logging. See
 992  * kvm_get_dirty_log_protect() function description for additional details.
 993  *
 994  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
 995  * always flush the TLB (step 4) even if previous step failed  and the dirty
 996  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
 997  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
 998  * writes will be marked dirty for next log read.
 999  *
1000  *   1. Take a snapshot of the bit and clear it if needed.
1001  *   2. Write protect the corresponding page.
1002  *   3. Copy the snapshot to the userspace.
1003  *   4. Flush TLB's if needed.
1004  */
1005 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1006 {
1007         struct kvm_memslots *slots;
1008         struct kvm_memory_slot *memslot;
1009         bool is_dirty = false;
1010         int r;
1011
1012         mutex_lock(&kvm->slots_lock);
1013
1014         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
1015
1016         if (is_dirty) {
1017                 slots = kvm_memslots(kvm);
1018                 memslot = id_to_memslot(slots, log->slot);
1019
1020                 /* Let implementation handle TLB/GVA invalidation */
1021                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1022         }
1023
1024         mutex_unlock(&kvm->slots_lock);
1025         return r;
1026 }
1027
1028 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1029 {
1030         long r;
1031
1032         switch (ioctl) {
1033         default:
1034                 r = -ENOIOCTLCMD;
1035         }
1036
1037         return r;
1038 }
1039
1040 int kvm_arch_init(void *opaque)
1041 {
1042         if (kvm_mips_callbacks) {
1043                 kvm_err("kvm: module already exists\n");
1044                 return -EEXIST;
1045         }
1046
1047         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1048 }
1049
1050 void kvm_arch_exit(void)
1051 {
1052         kvm_mips_callbacks = NULL;
1053 }
1054
1055 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1056                                   struct kvm_sregs *sregs)
1057 {
1058         return -ENOIOCTLCMD;
1059 }
1060
1061 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1062                                   struct kvm_sregs *sregs)
1063 {
1064         return -ENOIOCTLCMD;
1065 }
1066
1067 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1068 {
1069 }
1070
1071 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1072 {
1073         return -ENOIOCTLCMD;
1074 }
1075
1076 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1077 {
1078         return -ENOIOCTLCMD;
1079 }
1080
1081 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1082 {
1083         return VM_FAULT_SIGBUS;
1084 }
1085
1086 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1087 {
1088         int r;
1089
1090         switch (ext) {
1091         case KVM_CAP_ONE_REG:
1092         case KVM_CAP_ENABLE_CAP:
1093         case KVM_CAP_READONLY_MEM:
1094         case KVM_CAP_SYNC_MMU:
1095         case KVM_CAP_IMMEDIATE_EXIT:
1096                 r = 1;
1097                 break;
1098         case KVM_CAP_NR_VCPUS:
1099                 r = num_online_cpus();
1100                 break;
1101         case KVM_CAP_MAX_VCPUS:
1102                 r = KVM_MAX_VCPUS;
1103                 break;
1104         case KVM_CAP_MAX_VCPU_ID:
1105                 r = KVM_MAX_VCPU_ID;
1106                 break;
1107         case KVM_CAP_MIPS_FPU:
1108                 /* We don't handle systems with inconsistent cpu_has_fpu */
1109                 r = !!raw_cpu_has_fpu;
1110                 break;
1111         case KVM_CAP_MIPS_MSA:
1112                 /*
1113                  * We don't support MSA vector partitioning yet:
1114                  * 1) It would require explicit support which can't be tested
1115                  *    yet due to lack of support in current hardware.
1116                  * 2) It extends the state that would need to be saved/restored
1117                  *    by e.g. QEMU for migration.
1118                  *
1119                  * When vector partitioning hardware becomes available, support
1120                  * could be added by requiring a flag when enabling
1121                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1122                  * to save/restore the appropriate extra state.
1123                  */
1124                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1125                 break;
1126         default:
1127                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1128                 break;
1129         }
1130         return r;
1131 }
1132
1133 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1134 {
1135         return kvm_mips_pending_timer(vcpu) ||
1136                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1137 }
1138
1139 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1140 {
1141         int i;
1142         struct mips_coproc *cop0;
1143
1144         if (!vcpu)
1145                 return -1;
1146
1147         kvm_debug("VCPU Register Dump:\n");
1148         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1149         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1150
1151         for (i = 0; i < 32; i += 4) {
1152                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1153                        vcpu->arch.gprs[i],
1154                        vcpu->arch.gprs[i + 1],
1155                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1156         }
1157         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1158         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1159
1160         cop0 = vcpu->arch.cop0;
1161         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1162                   kvm_read_c0_guest_status(cop0),
1163                   kvm_read_c0_guest_cause(cop0));
1164
1165         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1166
1167         return 0;
1168 }
1169
1170 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1171 {
1172         int i;
1173
1174         vcpu_load(vcpu);
1175
1176         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1177                 vcpu->arch.gprs[i] = regs->gpr[i];
1178         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1179         vcpu->arch.hi = regs->hi;
1180         vcpu->arch.lo = regs->lo;
1181         vcpu->arch.pc = regs->pc;
1182
1183         vcpu_put(vcpu);
1184         return 0;
1185 }
1186
1187 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1188 {
1189         int i;
1190
1191         vcpu_load(vcpu);
1192
1193         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1194                 regs->gpr[i] = vcpu->arch.gprs[i];
1195
1196         regs->hi = vcpu->arch.hi;
1197         regs->lo = vcpu->arch.lo;
1198         regs->pc = vcpu->arch.pc;
1199
1200         vcpu_put(vcpu);
1201         return 0;
1202 }
1203
1204 static void kvm_mips_comparecount_func(unsigned long data)
1205 {
1206         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1207
1208         kvm_mips_callbacks->queue_timer_int(vcpu);
1209
1210         vcpu->arch.wait = 0;
1211         if (swq_has_sleeper(&vcpu->wq))
1212                 swake_up_one(&vcpu->wq);
1213 }
1214
1215 /* low level hrtimer wake routine */
1216 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1217 {
1218         struct kvm_vcpu *vcpu;
1219
1220         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1221         kvm_mips_comparecount_func((unsigned long) vcpu);
1222         return kvm_mips_count_timeout(vcpu);
1223 }
1224
1225 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1226 {
1227         int err;
1228
1229         err = kvm_mips_callbacks->vcpu_init(vcpu);
1230         if (err)
1231                 return err;
1232
1233         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1234                      HRTIMER_MODE_REL);
1235         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1236         return 0;
1237 }
1238
1239 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1240 {
1241         kvm_mips_callbacks->vcpu_uninit(vcpu);
1242 }
1243
1244 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1245                                   struct kvm_translation *tr)
1246 {
1247         return 0;
1248 }
1249
1250 /* Initial guest state */
1251 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1252 {
1253         return kvm_mips_callbacks->vcpu_setup(vcpu);
1254 }
1255
1256 static void kvm_mips_set_c0_status(void)
1257 {
1258         u32 status = read_c0_status();
1259
1260         if (cpu_has_dsp)
1261                 status |= (ST0_MX);
1262
1263         write_c0_status(status);
1264         ehb();
1265 }
1266
1267 /*
1268  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1269  */
1270 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1271 {
1272         u32 cause = vcpu->arch.host_cp0_cause;
1273         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1274         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1275         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1276         enum emulation_result er = EMULATE_DONE;
1277         u32 inst;
1278         int ret = RESUME_GUEST;
1279
1280         vcpu->mode = OUTSIDE_GUEST_MODE;
1281
1282         /* re-enable HTW before enabling interrupts */
1283         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1284                 htw_start();
1285
1286         /* Set a default exit reason */
1287         run->exit_reason = KVM_EXIT_UNKNOWN;
1288         run->ready_for_interrupt_injection = 1;
1289
1290         /*
1291          * Set the appropriate status bits based on host CPU features,
1292          * before we hit the scheduler
1293          */
1294         kvm_mips_set_c0_status();
1295
1296         local_irq_enable();
1297
1298         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1299                         cause, opc, run, vcpu);
1300         trace_kvm_exit(vcpu, exccode);
1301
1302         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1303                 /*
1304                  * Do a privilege check, if in UM most of these exit conditions
1305                  * end up causing an exception to be delivered to the Guest
1306                  * Kernel
1307                  */
1308                 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1309                 if (er == EMULATE_PRIV_FAIL) {
1310                         goto skip_emul;
1311                 } else if (er == EMULATE_FAIL) {
1312                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1313                         ret = RESUME_HOST;
1314                         goto skip_emul;
1315                 }
1316         }
1317
1318         switch (exccode) {
1319         case EXCCODE_INT:
1320                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1321
1322                 ++vcpu->stat.int_exits;
1323
1324                 if (need_resched())
1325                         cond_resched();
1326
1327                 ret = RESUME_GUEST;
1328                 break;
1329
1330         case EXCCODE_CPU:
1331                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1332
1333                 ++vcpu->stat.cop_unusable_exits;
1334                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1335                 /* XXXKYMA: Might need to return to user space */
1336                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1337                         ret = RESUME_HOST;
1338                 break;
1339
1340         case EXCCODE_MOD:
1341                 ++vcpu->stat.tlbmod_exits;
1342                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1343                 break;
1344
1345         case EXCCODE_TLBS:
1346                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1347                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1348                           badvaddr);
1349
1350                 ++vcpu->stat.tlbmiss_st_exits;
1351                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1352                 break;
1353
1354         case EXCCODE_TLBL:
1355                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1356                           cause, opc, badvaddr);
1357
1358                 ++vcpu->stat.tlbmiss_ld_exits;
1359                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1360                 break;
1361
1362         case EXCCODE_ADES:
1363                 ++vcpu->stat.addrerr_st_exits;
1364                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1365                 break;
1366
1367         case EXCCODE_ADEL:
1368                 ++vcpu->stat.addrerr_ld_exits;
1369                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1370                 break;
1371
1372         case EXCCODE_SYS:
1373                 ++vcpu->stat.syscall_exits;
1374                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1375                 break;
1376
1377         case EXCCODE_RI:
1378                 ++vcpu->stat.resvd_inst_exits;
1379                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1380                 break;
1381
1382         case EXCCODE_BP:
1383                 ++vcpu->stat.break_inst_exits;
1384                 ret = kvm_mips_callbacks->handle_break(vcpu);
1385                 break;
1386
1387         case EXCCODE_TR:
1388                 ++vcpu->stat.trap_inst_exits;
1389                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1390                 break;
1391
1392         case EXCCODE_MSAFPE:
1393                 ++vcpu->stat.msa_fpe_exits;
1394                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1395                 break;
1396
1397         case EXCCODE_FPE:
1398                 ++vcpu->stat.fpe_exits;
1399                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1400                 break;
1401
1402         case EXCCODE_MSADIS:
1403                 ++vcpu->stat.msa_disabled_exits;
1404                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1405                 break;
1406
1407         case EXCCODE_GE:
1408                 /* defer exit accounting to handler */
1409                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1410                 break;
1411
1412         default:
1413                 if (cause & CAUSEF_BD)
1414                         opc += 1;
1415                 inst = 0;
1416                 kvm_get_badinstr(opc, vcpu, &inst);
1417                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1418                         exccode, opc, inst, badvaddr,
1419                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1420                 kvm_arch_vcpu_dump_regs(vcpu);
1421                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1422                 ret = RESUME_HOST;
1423                 break;
1424
1425         }
1426
1427 skip_emul:
1428         local_irq_disable();
1429
1430         if (ret == RESUME_GUEST)
1431                 kvm_vz_acquire_htimer(vcpu);
1432
1433         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1434                 kvm_mips_deliver_interrupts(vcpu, cause);
1435
1436         if (!(ret & RESUME_HOST)) {
1437                 /* Only check for signals if not already exiting to userspace */
1438                 if (signal_pending(current)) {
1439                         run->exit_reason = KVM_EXIT_INTR;
1440                         ret = (-EINTR << 2) | RESUME_HOST;
1441                         ++vcpu->stat.signal_exits;
1442                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1443                 }
1444         }
1445
1446         if (ret == RESUME_GUEST) {
1447                 trace_kvm_reenter(vcpu);
1448
1449                 /*
1450                  * Make sure the read of VCPU requests in vcpu_reenter()
1451                  * callback is not reordered ahead of the write to vcpu->mode,
1452                  * or we could miss a TLB flush request while the requester sees
1453                  * the VCPU as outside of guest mode and not needing an IPI.
1454                  */
1455                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1456
1457                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1458
1459                 /*
1460                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1461                  * is live), restore FCR31 / MSACSR.
1462                  *
1463                  * This should be before returning to the guest exception
1464                  * vector, as it may well cause an [MSA] FP exception if there
1465                  * are pending exception bits unmasked. (see
1466                  * kvm_mips_csr_die_notifier() for how that is handled).
1467                  */
1468                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1469                     read_c0_status() & ST0_CU1)
1470                         __kvm_restore_fcsr(&vcpu->arch);
1471
1472                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1473                     read_c0_config5() & MIPS_CONF5_MSAEN)
1474                         __kvm_restore_msacsr(&vcpu->arch);
1475         }
1476
1477         /* Disable HTW before returning to guest or host */
1478         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1479                 htw_stop();
1480
1481         return ret;
1482 }
1483
1484 /* Enable FPU for guest and restore context */
1485 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1486 {
1487         struct mips_coproc *cop0 = vcpu->arch.cop0;
1488         unsigned int sr, cfg5;
1489
1490         preempt_disable();
1491
1492         sr = kvm_read_c0_guest_status(cop0);
1493
1494         /*
1495          * If MSA state is already live, it is undefined how it interacts with
1496          * FR=0 FPU state, and we don't want to hit reserved instruction
1497          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1498          * play it safe and save it first.
1499          *
1500          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1501          * get called when guest CU1 is set, however we can't trust the guest
1502          * not to clobber the status register directly via the commpage.
1503          */
1504         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1505             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1506                 kvm_lose_fpu(vcpu);
1507
1508         /*
1509          * Enable FPU for guest
1510          * We set FR and FRE according to guest context
1511          */
1512         change_c0_status(ST0_CU1 | ST0_FR, sr);
1513         if (cpu_has_fre) {
1514                 cfg5 = kvm_read_c0_guest_config5(cop0);
1515                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1516         }
1517         enable_fpu_hazard();
1518
1519         /* If guest FPU state not active, restore it now */
1520         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1521                 __kvm_restore_fpu(&vcpu->arch);
1522                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1523                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1524         } else {
1525                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1526         }
1527
1528         preempt_enable();
1529 }
1530
1531 #ifdef CONFIG_CPU_HAS_MSA
1532 /* Enable MSA for guest and restore context */
1533 void kvm_own_msa(struct kvm_vcpu *vcpu)
1534 {
1535         struct mips_coproc *cop0 = vcpu->arch.cop0;
1536         unsigned int sr, cfg5;
1537
1538         preempt_disable();
1539
1540         /*
1541          * Enable FPU if enabled in guest, since we're restoring FPU context
1542          * anyway. We set FR and FRE according to guest context.
1543          */
1544         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1545                 sr = kvm_read_c0_guest_status(cop0);
1546
1547                 /*
1548                  * If FR=0 FPU state is already live, it is undefined how it
1549                  * interacts with MSA state, so play it safe and save it first.
1550                  */
1551                 if (!(sr & ST0_FR) &&
1552                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1553                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1554                         kvm_lose_fpu(vcpu);
1555
1556                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1557                 if (sr & ST0_CU1 && cpu_has_fre) {
1558                         cfg5 = kvm_read_c0_guest_config5(cop0);
1559                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1560                 }
1561         }
1562
1563         /* Enable MSA for guest */
1564         set_c0_config5(MIPS_CONF5_MSAEN);
1565         enable_fpu_hazard();
1566
1567         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1568         case KVM_MIPS_AUX_FPU:
1569                 /*
1570                  * Guest FPU state already loaded, only restore upper MSA state
1571                  */
1572                 __kvm_restore_msa_upper(&vcpu->arch);
1573                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1574                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1575                 break;
1576         case 0:
1577                 /* Neither FPU or MSA already active, restore full MSA state */
1578                 __kvm_restore_msa(&vcpu->arch);
1579                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1580                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1581                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1582                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1583                               KVM_TRACE_AUX_FPU_MSA);
1584                 break;
1585         default:
1586                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1587                 break;
1588         }
1589
1590         preempt_enable();
1591 }
1592 #endif
1593
1594 /* Drop FPU & MSA without saving it */
1595 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1596 {
1597         preempt_disable();
1598         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1599                 disable_msa();
1600                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1601                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1602         }
1603         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1604                 clear_c0_status(ST0_CU1 | ST0_FR);
1605                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1606                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1607         }
1608         preempt_enable();
1609 }
1610
1611 /* Save and disable FPU & MSA */
1612 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1613 {
1614         /*
1615          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1616          * is disabled in guest context (software), but the register state in
1617          * the hardware may still be in use.
1618          * This is why we explicitly re-enable the hardware before saving.
1619          */
1620
1621         preempt_disable();
1622         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1623                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1624                         set_c0_config5(MIPS_CONF5_MSAEN);
1625                         enable_fpu_hazard();
1626                 }
1627
1628                 __kvm_save_msa(&vcpu->arch);
1629                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1630
1631                 /* Disable MSA & FPU */
1632                 disable_msa();
1633                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1634                         clear_c0_status(ST0_CU1 | ST0_FR);
1635                         disable_fpu_hazard();
1636                 }
1637                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1638         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1639                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1640                         set_c0_status(ST0_CU1);
1641                         enable_fpu_hazard();
1642                 }
1643
1644                 __kvm_save_fpu(&vcpu->arch);
1645                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1646                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1647
1648                 /* Disable FPU */
1649                 clear_c0_status(ST0_CU1 | ST0_FR);
1650                 disable_fpu_hazard();
1651         }
1652         preempt_enable();
1653 }
1654
1655 /*
1656  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1657  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1658  * exception if cause bits are set in the value being written.
1659  */
1660 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1661                                    unsigned long cmd, void *ptr)
1662 {
1663         struct die_args *args = (struct die_args *)ptr;
1664         struct pt_regs *regs = args->regs;
1665         unsigned long pc;
1666
1667         /* Only interested in FPE and MSAFPE */
1668         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1669                 return NOTIFY_DONE;
1670
1671         /* Return immediately if guest context isn't active */
1672         if (!(current->flags & PF_VCPU))
1673                 return NOTIFY_DONE;
1674
1675         /* Should never get here from user mode */
1676         BUG_ON(user_mode(regs));
1677
1678         pc = instruction_pointer(regs);
1679         switch (cmd) {
1680         case DIE_FP:
1681                 /* match 2nd instruction in __kvm_restore_fcsr */
1682                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1683                         return NOTIFY_DONE;
1684                 break;
1685         case DIE_MSAFP:
1686                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1687                 if (!cpu_has_msa ||
1688                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1689                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1690                         return NOTIFY_DONE;
1691                 break;
1692         }
1693
1694         /* Move PC forward a little and continue executing */
1695         instruction_pointer(regs) += 4;
1696
1697         return NOTIFY_STOP;
1698 }
1699
1700 static struct notifier_block kvm_mips_csr_die_notifier = {
1701         .notifier_call = kvm_mips_csr_die_notify,
1702 };
1703
1704 static int __init kvm_mips_init(void)
1705 {
1706         int ret;
1707
1708         ret = kvm_mips_entry_setup();
1709         if (ret)
1710                 return ret;
1711
1712         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1713
1714         if (ret)
1715                 return ret;
1716
1717         register_die_notifier(&kvm_mips_csr_die_notifier);
1718
1719         return 0;
1720 }
1721
1722 static void __exit kvm_mips_exit(void)
1723 {
1724         kvm_exit();
1725
1726         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1727 }
1728
1729 module_init(kvm_mips_init);
1730 module_exit(kvm_mips_exit);
1731
1732 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);