2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Main entry point for the guest, exception handling.
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
13 #include <asm/asmmacro.h>
14 #include <asm/regdef.h>
15 #include <asm/mipsregs.h>
16 #include <asm/stackframe.h>
17 #include <asm/asm-offsets.h>
20 #define MIPSX(name) mips32_ ## name
21 #define CALLFRAME_SIZ 32
25 * exception vector entrypoint
27 #define VECTOR(x, regmask) \
31 #define VECTOR_END(x) \
34 /* Overload, Danger Will Robinson!! */
35 #define PT_HOST_ASID PT_BVADDR
36 #define PT_HOST_USERLOCAL PT_EPC
38 #define CP0_DDATA_LO $28,3
41 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
43 #define RESUME_GUEST 0
44 #define RESUME_HOST RESUME_FLAG_HOST
47 * __kvm_mips_vcpu_run: entry point to the guest
54 FEXPORT(__kvm_mips_vcpu_run)
55 /* k0/k1 not being used in host kernel context */
56 INT_ADDIU k1, sp, -PT_SIZE
69 LONG_S $10, PT_R10(k1)
70 LONG_S $11, PT_R11(k1)
71 LONG_S $12, PT_R12(k1)
72 LONG_S $13, PT_R13(k1)
73 LONG_S $14, PT_R14(k1)
74 LONG_S $15, PT_R15(k1)
75 LONG_S $16, PT_R16(k1)
76 LONG_S $17, PT_R17(k1)
78 LONG_S $18, PT_R18(k1)
79 LONG_S $19, PT_R19(k1)
80 LONG_S $20, PT_R20(k1)
81 LONG_S $21, PT_R21(k1)
82 LONG_S $22, PT_R22(k1)
83 LONG_S $23, PT_R23(k1)
84 LONG_S $24, PT_R24(k1)
85 LONG_S $25, PT_R25(k1)
88 * XXXKYMA k0/k1 not saved, not being used if we got here through
92 LONG_S $28, PT_R28(k1)
93 LONG_S $29, PT_R29(k1)
94 LONG_S $30, PT_R30(k1)
95 LONG_S $31, PT_R31(k1)
103 /* Save host status */
105 LONG_S v0, PT_STATUS(k1)
107 /* Save host ASID, shove it into the BVADDR location */
110 LONG_S v1, PT_HOST_ASID(k1)
112 /* Save DDATA_LO, will be used to store pointer to vcpu */
113 mfc0 v1, CP0_DDATA_LO
114 LONG_S v1, PT_HOST_USERLOCAL(k1)
116 /* DDATA_LO has pointer to vcpu */
117 mtc0 a1, CP0_DDATA_LO
119 /* Offset into vcpu->arch */
120 INT_ADDIU k1, a1, VCPU_HOST_ARCH
123 * Save the host stack to VCPU, used for exception processing
124 * when we exit from the Guest
126 LONG_S sp, VCPU_HOST_STACK(k1)
128 /* Save the kernel gp as well */
129 LONG_S gp, VCPU_HOST_GP(k1)
132 * Setup status register for running the guest in UM, interrupts
135 li k0, (ST0_EXL | KSU_USER | ST0_BEV)
139 /* load up the new EBASE */
140 LONG_L k0, VCPU_GUEST_EBASE(k1)
144 * Now that the new EBASE has been loaded, unset BEV, set
145 * interrupt mask as it was but make sure that timer interrupts
148 li k0, (ST0_EXL | KSU_USER | ST0_IE)
155 LONG_L t0, VCPU_PC(k1)
158 FEXPORT(__kvm_mips_load_asid)
159 /* Set the ASID for the Guest Kernel */
160 PTR_L t0, VCPU_COP0(k1)
161 LONG_L t0, COP0_STATUS(t0)
162 andi t0, KSU_USER | ST0_ERL | ST0_EXL
164 bnez t0, 1f /* If kernel */
165 INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID /* (BD) */
166 INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID /* else user */
168 /* t1: contains the base of the ASID array, need to get the cpu id */
169 LONG_L t2, TI_CPU($28) /* smp_processor_id */
170 INT_SLL t2, t2, 2 /* x4 */
177 /* Disable RDHWR access */
178 mtc0 zero, CP0_HWRENA
180 /* Now load up the Guest Context from VCPU */
181 LONG_L $1, VCPU_R1(k1)
182 LONG_L $2, VCPU_R2(k1)
183 LONG_L $3, VCPU_R3(k1)
185 LONG_L $4, VCPU_R4(k1)
186 LONG_L $5, VCPU_R5(k1)
187 LONG_L $6, VCPU_R6(k1)
188 LONG_L $7, VCPU_R7(k1)
190 LONG_L $8, VCPU_R8(k1)
191 LONG_L $9, VCPU_R9(k1)
192 LONG_L $10, VCPU_R10(k1)
193 LONG_L $11, VCPU_R11(k1)
194 LONG_L $12, VCPU_R12(k1)
195 LONG_L $13, VCPU_R13(k1)
196 LONG_L $14, VCPU_R14(k1)
197 LONG_L $15, VCPU_R15(k1)
198 LONG_L $16, VCPU_R16(k1)
199 LONG_L $17, VCPU_R17(k1)
200 LONG_L $18, VCPU_R18(k1)
201 LONG_L $19, VCPU_R19(k1)
202 LONG_L $20, VCPU_R20(k1)
203 LONG_L $21, VCPU_R21(k1)
204 LONG_L $22, VCPU_R22(k1)
205 LONG_L $23, VCPU_R23(k1)
206 LONG_L $24, VCPU_R24(k1)
207 LONG_L $25, VCPU_R25(k1)
209 /* k0/k1 loaded up later */
211 LONG_L $28, VCPU_R28(k1)
212 LONG_L $29, VCPU_R29(k1)
213 LONG_L $30, VCPU_R30(k1)
214 LONG_L $31, VCPU_R31(k1)
217 LONG_L k0, VCPU_LO(k1)
220 LONG_L k0, VCPU_HI(k1)
223 FEXPORT(__kvm_mips_load_k0k1)
224 /* Restore the guest's k0/k1 registers */
225 LONG_L k0, VCPU_R26(k1)
226 LONG_L k1, VCPU_R27(k1)
230 EXPORT(__kvm_mips_vcpu_run_end)
232 VECTOR(MIPSX(exception), unknown)
233 /* Find out what mode we came from and jump to the proper handler. */
234 mtc0 k0, CP0_ERROREPC #01: Save guest k0
237 mfc0 k0, CP0_EBASE #02: Get EBASE
238 INT_SRL k0, k0, 10 #03: Get rid of CPUNum
239 INT_SLL k0, k0, 10 #04
240 LONG_S k1, 0x3000(k0) #05: Save k1 @ offset 0x3000
241 INT_ADDIU k0, k0, 0x2000 #06: Exception handler is
242 # installed @ offset 0x2000
243 j k0 #07: jump to the function
244 nop #08: branch delay slot
245 VECTOR_END(MIPSX(exceptionEnd))
246 .end MIPSX(exception)
249 * Generic Guest exception handler. We end up here when the guest
250 * does something that causes a trap to kernel mode.
252 NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
253 /* Get the VCPU pointer from DDTATA_LO */
254 mfc0 k1, CP0_DDATA_LO
255 INT_ADDIU k1, k1, VCPU_HOST_ARCH
257 /* Start saving Guest context to VCPU */
258 LONG_S $0, VCPU_R0(k1)
259 LONG_S $1, VCPU_R1(k1)
260 LONG_S $2, VCPU_R2(k1)
261 LONG_S $3, VCPU_R3(k1)
262 LONG_S $4, VCPU_R4(k1)
263 LONG_S $5, VCPU_R5(k1)
264 LONG_S $6, VCPU_R6(k1)
265 LONG_S $7, VCPU_R7(k1)
266 LONG_S $8, VCPU_R8(k1)
267 LONG_S $9, VCPU_R9(k1)
268 LONG_S $10, VCPU_R10(k1)
269 LONG_S $11, VCPU_R11(k1)
270 LONG_S $12, VCPU_R12(k1)
271 LONG_S $13, VCPU_R13(k1)
272 LONG_S $14, VCPU_R14(k1)
273 LONG_S $15, VCPU_R15(k1)
274 LONG_S $16, VCPU_R16(k1)
275 LONG_S $17, VCPU_R17(k1)
276 LONG_S $18, VCPU_R18(k1)
277 LONG_S $19, VCPU_R19(k1)
278 LONG_S $20, VCPU_R20(k1)
279 LONG_S $21, VCPU_R21(k1)
280 LONG_S $22, VCPU_R22(k1)
281 LONG_S $23, VCPU_R23(k1)
282 LONG_S $24, VCPU_R24(k1)
283 LONG_S $25, VCPU_R25(k1)
285 /* Guest k0/k1 saved later */
287 LONG_S $28, VCPU_R28(k1)
288 LONG_S $29, VCPU_R29(k1)
289 LONG_S $30, VCPU_R30(k1)
290 LONG_S $31, VCPU_R31(k1)
292 /* We need to save hi/lo and restore them on the way out */
294 LONG_S t0, VCPU_HI(k1)
297 LONG_S t0, VCPU_LO(k1)
299 /* Finally save guest k0/k1 to VCPU */
300 mfc0 t0, CP0_ERROREPC
301 LONG_S t0, VCPU_R26(k1)
303 /* Get GUEST k1 and save it in VCPU */
307 LONG_L t0, 0x3000(t0)
308 LONG_S t0, VCPU_R27(k1)
310 /* Now that context has been saved, we can use other registers */
313 mfc0 a1, CP0_DDATA_LO
316 /* Restore run (vcpu->run) */
317 LONG_L a0, VCPU_RUN(a1)
318 /* Save pointer to run in s0, will be saved by the compiler */
322 * Save Host level EPC, BadVaddr and Cause to VCPU, useful to
323 * process the exception
326 LONG_S k0, VCPU_PC(k1)
328 mfc0 k0, CP0_BADVADDR
329 LONG_S k0, VCPU_HOST_CP0_BADVADDR(k1)
332 LONG_S k0, VCPU_HOST_CP0_CAUSE(k1)
335 LONG_S k0, VCPU_HOST_ENTRYHI(k1)
337 /* Now restore the host state just enough to run the handlers */
339 /* Swtich EBASE to the one used by Linux */
340 /* load up the host EBASE */
350 LONG_L k0, VCPU_HOST_EBASE(k1)
354 * If FPU is enabled, save FCR31 and clear it so that later ctc1's don't
355 * trigger FPE for pending exceptions.
364 sw t0, VCPU_FCR31(k1)
370 #ifdef CONFIG_CPU_HAS_MSA
372 * If MSA is enabled, save MSACSR and clear it so that later
373 * instructions don't trigger MSAFPE for pending exceptions.
376 ext t0, t0, 28, 1 /* MIPS_CONF3_MSAP */
380 ext t0, t0, 27, 1 /* MIPS_CONF5_MSAEN */
384 sw t0, VCPU_MSA_CSR(k1)
385 _ctcmsa MSA_CSR, zero
389 /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
391 and v0, v0, ~(ST0_EXL | KSU_USER | ST0_IE)
397 /* Load up host GP */
398 LONG_L gp, VCPU_HOST_GP(k1)
400 /* Need a stack before we can jump to "C" */
401 LONG_L sp, VCPU_HOST_STACK(k1)
403 /* Saved host state */
404 INT_ADDIU sp, sp, -PT_SIZE
407 * XXXKYMA do we need to load the host ASID, maybe not because the
408 * kernel entries are marked GLOBAL, need to verify
411 /* Restore host DDATA_LO */
412 LONG_L k0, PT_HOST_USERLOCAL(sp)
413 mtc0 k0, CP0_DDATA_LO
415 /* Restore RDHWR access */
416 PTR_LI k0, 0x2000000F
419 /* Jump to handler */
420 FEXPORT(__kvm_mips_jump_to_handler)
422 * XXXKYMA: not sure if this is safe, how large is the stack??
423 * Now jump to the kvm_mips_handle_exit() to see if we can deal
424 * with this in the kernel
426 PTR_LA t9, kvm_mips_handle_exit
428 INT_ADDIU sp, sp, -CALLFRAME_SIZ /* BD Slot */
430 /* Return from handler Make sure interrupts are disabled */
435 * XXXKYMA: k0/k1 could have been blown away if we processed
436 * an exception while we were handling the exception from the
441 INT_ADDIU k1, k1, VCPU_HOST_ARCH
444 * Check return value, should tell us if we are returning to the
445 * host (handle I/O etc)or resuming the guest
447 andi t0, v0, RESUME_HOST
448 bnez t0, __kvm_mips_return_to_host
451 __kvm_mips_return_to_guest:
452 /* Put the saved pointer to vcpu (s1) back into the DDATA_LO Register */
453 mtc0 s1, CP0_DDATA_LO
455 /* Load up the Guest EBASE to minimize the window where BEV is set */
456 LONG_L t0, VCPU_GUEST_EBASE(k1)
458 /* Switch EBASE back to the one used by KVM */
467 /* Setup status register for running guest in UM */
469 or v1, v1, (ST0_EXL | KSU_USER | ST0_IE)
470 and v1, v1, ~(ST0_CU0 | ST0_MX)
476 LONG_L t0, VCPU_PC(k1)
479 /* Set the ASID for the Guest Kernel */
480 PTR_L t0, VCPU_COP0(k1)
481 LONG_L t0, COP0_STATUS(t0)
482 andi t0, KSU_USER | ST0_ERL | ST0_EXL
484 bnez t0, 1f /* If kernel */
485 INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID /* (BD) */
486 INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID /* else user */
488 /* t1: contains the base of the ASID array, need to get the cpu id */
489 LONG_L t2, TI_CPU($28) /* smp_processor_id */
490 INT_SLL t2, t2, 2 /* x4 */
497 /* Disable RDHWR access */
498 mtc0 zero, CP0_HWRENA
500 /* load the guest context from VCPU and return */
501 LONG_L $0, VCPU_R0(k1)
502 LONG_L $1, VCPU_R1(k1)
503 LONG_L $2, VCPU_R2(k1)
504 LONG_L $3, VCPU_R3(k1)
505 LONG_L $4, VCPU_R4(k1)
506 LONG_L $5, VCPU_R5(k1)
507 LONG_L $6, VCPU_R6(k1)
508 LONG_L $7, VCPU_R7(k1)
509 LONG_L $8, VCPU_R8(k1)
510 LONG_L $9, VCPU_R9(k1)
511 LONG_L $10, VCPU_R10(k1)
512 LONG_L $11, VCPU_R11(k1)
513 LONG_L $12, VCPU_R12(k1)
514 LONG_L $13, VCPU_R13(k1)
515 LONG_L $14, VCPU_R14(k1)
516 LONG_L $15, VCPU_R15(k1)
517 LONG_L $16, VCPU_R16(k1)
518 LONG_L $17, VCPU_R17(k1)
519 LONG_L $18, VCPU_R18(k1)
520 LONG_L $19, VCPU_R19(k1)
521 LONG_L $20, VCPU_R20(k1)
522 LONG_L $21, VCPU_R21(k1)
523 LONG_L $22, VCPU_R22(k1)
524 LONG_L $23, VCPU_R23(k1)
525 LONG_L $24, VCPU_R24(k1)
526 LONG_L $25, VCPU_R25(k1)
528 /* $/k1 loaded later */
529 LONG_L $28, VCPU_R28(k1)
530 LONG_L $29, VCPU_R29(k1)
531 LONG_L $30, VCPU_R30(k1)
532 LONG_L $31, VCPU_R31(k1)
534 FEXPORT(__kvm_mips_skip_guest_restore)
535 LONG_L k0, VCPU_HI(k1)
538 LONG_L k0, VCPU_LO(k1)
541 LONG_L k0, VCPU_R26(k1)
542 LONG_L k1, VCPU_R27(k1)
546 __kvm_mips_return_to_host:
547 /* EBASE is already pointing to Linux */
548 LONG_L k1, VCPU_HOST_STACK(k1)
549 INT_ADDIU k1,k1, -PT_SIZE
551 /* Restore host DDATA_LO */
552 LONG_L k0, PT_HOST_USERLOCAL(k1)
553 mtc0 k0, CP0_DDATA_LO
555 /* Restore host ASID */
556 LONG_L k0, PT_HOST_ASID(sp)
561 /* Load context saved on the host stack */
566 * r2/v0 is the return code, shift it down by 2 (arithmetic)
567 * to recover the err code
579 LONG_L $10, PT_R10(k1)
580 LONG_L $11, PT_R11(k1)
581 LONG_L $12, PT_R12(k1)
582 LONG_L $13, PT_R13(k1)
583 LONG_L $14, PT_R14(k1)
584 LONG_L $15, PT_R15(k1)
585 LONG_L $16, PT_R16(k1)
586 LONG_L $17, PT_R17(k1)
587 LONG_L $18, PT_R18(k1)
588 LONG_L $19, PT_R19(k1)
589 LONG_L $20, PT_R20(k1)
590 LONG_L $21, PT_R21(k1)
591 LONG_L $22, PT_R22(k1)
592 LONG_L $23, PT_R23(k1)
593 LONG_L $24, PT_R24(k1)
594 LONG_L $25, PT_R25(k1)
596 /* Host k0/k1 were not saved */
598 LONG_L $28, PT_R28(k1)
599 LONG_L $29, PT_R29(k1)
600 LONG_L $30, PT_R30(k1)
608 /* Restore RDHWR access */
609 PTR_LI k0, 0x2000000F
612 /* Restore RA, which is the address we will return to */
613 LONG_L ra, PT_R31(k1)
617 VECTOR_END(MIPSX(GuestExceptionEnd))
618 .end MIPSX(GuestException)
622 ##### The exception handlers.
624 .word _C_LABEL(MIPSX(GuestException)) # 0
625 .word _C_LABEL(MIPSX(GuestException)) # 1
626 .word _C_LABEL(MIPSX(GuestException)) # 2
627 .word _C_LABEL(MIPSX(GuestException)) # 3
628 .word _C_LABEL(MIPSX(GuestException)) # 4
629 .word _C_LABEL(MIPSX(GuestException)) # 5
630 .word _C_LABEL(MIPSX(GuestException)) # 6
631 .word _C_LABEL(MIPSX(GuestException)) # 7
632 .word _C_LABEL(MIPSX(GuestException)) # 8
633 .word _C_LABEL(MIPSX(GuestException)) # 9
634 .word _C_LABEL(MIPSX(GuestException)) # 10
635 .word _C_LABEL(MIPSX(GuestException)) # 11
636 .word _C_LABEL(MIPSX(GuestException)) # 12
637 .word _C_LABEL(MIPSX(GuestException)) # 13
638 .word _C_LABEL(MIPSX(GuestException)) # 14
639 .word _C_LABEL(MIPSX(GuestException)) # 15
640 .word _C_LABEL(MIPSX(GuestException)) # 16
641 .word _C_LABEL(MIPSX(GuestException)) # 17
642 .word _C_LABEL(MIPSX(GuestException)) # 18
643 .word _C_LABEL(MIPSX(GuestException)) # 19
644 .word _C_LABEL(MIPSX(GuestException)) # 20
645 .word _C_LABEL(MIPSX(GuestException)) # 21
646 .word _C_LABEL(MIPSX(GuestException)) # 22
647 .word _C_LABEL(MIPSX(GuestException)) # 23
648 .word _C_LABEL(MIPSX(GuestException)) # 24
649 .word _C_LABEL(MIPSX(GuestException)) # 25
650 .word _C_LABEL(MIPSX(GuestException)) # 26
651 .word _C_LABEL(MIPSX(GuestException)) # 27
652 .word _C_LABEL(MIPSX(GuestException)) # 28
653 .word _C_LABEL(MIPSX(GuestException)) # 29
654 .word _C_LABEL(MIPSX(GuestException)) # 30
655 .word _C_LABEL(MIPSX(GuestException)) # 31