2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: Instruction/Exception emulation
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/ktime.h>
15 #include <linux/kvm_host.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
19 #include <linux/bootmem.h>
20 #include <linux/random.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cpu-info.h>
24 #include <asm/mmu_context.h>
25 #include <asm/tlbflush.h>
29 #include <asm/r4kcache.h>
30 #define CONFIG_MIPS_MT
33 #include "interrupt.h"
39 * Compute the return address and do emulate branch simulation, if required.
40 * This function should be called only in branch delay slot active.
42 unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu,
45 unsigned int dspcontrol;
46 union mips_instruction insn;
47 struct kvm_vcpu_arch *arch = &vcpu->arch;
49 long nextpc = KVM_INVALID_INST;
54 /* Read the instruction */
55 insn.word = kvm_get_inst((uint32_t *) epc, vcpu);
57 if (insn.word == KVM_INVALID_INST)
58 return KVM_INVALID_INST;
60 switch (insn.i_format.opcode) {
61 /* jr and jalr are in r_format format. */
63 switch (insn.r_format.func) {
65 arch->gprs[insn.r_format.rd] = epc + 8;
68 nextpc = arch->gprs[insn.r_format.rs];
74 * This group contains:
75 * bltz_op, bgez_op, bltzl_op, bgezl_op,
76 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
79 switch (insn.i_format.rt) {
82 if ((long)arch->gprs[insn.i_format.rs] < 0)
83 epc = epc + 4 + (insn.i_format.simmediate << 2);
91 if ((long)arch->gprs[insn.i_format.rs] >= 0)
92 epc = epc + 4 + (insn.i_format.simmediate << 2);
100 arch->gprs[31] = epc + 8;
101 if ((long)arch->gprs[insn.i_format.rs] < 0)
102 epc = epc + 4 + (insn.i_format.simmediate << 2);
110 arch->gprs[31] = epc + 8;
111 if ((long)arch->gprs[insn.i_format.rs] >= 0)
112 epc = epc + 4 + (insn.i_format.simmediate << 2);
121 dspcontrol = rddsp(0x01);
123 if (dspcontrol >= 32)
124 epc = epc + 4 + (insn.i_format.simmediate << 2);
132 /* These are unconditional and in j_format. */
134 arch->gprs[31] = instpc + 8;
139 epc |= (insn.j_format.target << 2);
143 /* These are conditional and in i_format. */
146 if (arch->gprs[insn.i_format.rs] ==
147 arch->gprs[insn.i_format.rt])
148 epc = epc + 4 + (insn.i_format.simmediate << 2);
156 if (arch->gprs[insn.i_format.rs] !=
157 arch->gprs[insn.i_format.rt])
158 epc = epc + 4 + (insn.i_format.simmediate << 2);
164 case blez_op: /* not really i_format */
166 /* rt field assumed to be zero */
167 if ((long)arch->gprs[insn.i_format.rs] <= 0)
168 epc = epc + 4 + (insn.i_format.simmediate << 2);
176 /* rt field assumed to be zero */
177 if ((long)arch->gprs[insn.i_format.rs] > 0)
178 epc = epc + 4 + (insn.i_format.simmediate << 2);
184 /* And now the FPA/cp1 branch instructions. */
186 kvm_err("%s: unsupported cop1_op\n", __func__);
193 kvm_err("%s: unaligned epc\n", __func__);
197 kvm_err("%s: DSP branch but not DSP ASE\n", __func__);
201 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause)
203 unsigned long branch_pc;
204 enum emulation_result er = EMULATE_DONE;
206 if (cause & CAUSEF_BD) {
207 branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc);
208 if (branch_pc == KVM_INVALID_INST) {
211 vcpu->arch.pc = branch_pc;
212 kvm_debug("BD update_pc(): New PC: %#lx\n",
218 kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
224 * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
225 * @vcpu: Virtual CPU.
227 * Returns: 1 if the CP0_Count timer is disabled by either the guest
228 * CP0_Cause.DC bit or the count_ctl.DC bit.
229 * 0 otherwise (in which case CP0_Count timer is running).
231 static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
233 struct mips_coproc *cop0 = vcpu->arch.cop0;
235 return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
236 (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
240 * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
242 * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
244 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
246 static uint32_t kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
251 now_ns = ktime_to_ns(now);
252 delta = now_ns + vcpu->arch.count_dyn_bias;
254 if (delta >= vcpu->arch.count_period) {
255 /* If delta is out of safe range the bias needs adjusting */
256 periods = div64_s64(now_ns, vcpu->arch.count_period);
257 vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
258 /* Recalculate delta with new bias */
259 delta = now_ns + vcpu->arch.count_dyn_bias;
263 * We've ensured that:
264 * delta < count_period
266 * Therefore the intermediate delta*count_hz will never overflow since
267 * at the boundary condition:
268 * delta = count_period
269 * delta = NSEC_PER_SEC * 2^32 / count_hz
270 * delta * count_hz = NSEC_PER_SEC * 2^32
272 return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
276 * kvm_mips_count_time() - Get effective current time.
277 * @vcpu: Virtual CPU.
279 * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
280 * except when the master disable bit is set in count_ctl, in which case it is
281 * count_resume, i.e. the time that the count was disabled.
283 * Returns: Effective monotonic ktime for CP0_Count.
285 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
287 if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
288 return vcpu->arch.count_resume;
294 * kvm_mips_read_count_running() - Read the current count value as if running.
295 * @vcpu: Virtual CPU.
296 * @now: Kernel time to read CP0_Count at.
298 * Returns the current guest CP0_Count register at time @now and handles if the
299 * timer interrupt is pending and hasn't been handled yet.
301 * Returns: The current value of the guest CP0_Count register.
303 static uint32_t kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
305 struct mips_coproc *cop0 = vcpu->arch.cop0;
306 ktime_t expires, threshold;
307 uint32_t count, compare;
310 /* Calculate the biased and scaled guest CP0_Count */
311 count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
312 compare = kvm_read_c0_guest_compare(cop0);
315 * Find whether CP0_Count has reached the closest timer interrupt. If
316 * not, we shouldn't inject it.
318 if ((int32_t)(count - compare) < 0)
322 * The CP0_Count we're going to return has already reached the closest
323 * timer interrupt. Quickly check if it really is a new interrupt by
324 * looking at whether the interval until the hrtimer expiry time is
325 * less than 1/4 of the timer period.
327 expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
328 threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
329 if (ktime_before(expires, threshold)) {
331 * Cancel it while we handle it so there's no chance of
332 * interference with the timeout handler.
334 running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
336 /* Nothing should be waiting on the timeout */
337 kvm_mips_callbacks->queue_timer_int(vcpu);
340 * Restart the timer if it was running based on the expiry time
341 * we read, so that we don't push it back 2 periods.
344 expires = ktime_add_ns(expires,
345 vcpu->arch.count_period);
346 hrtimer_start(&vcpu->arch.comparecount_timer, expires,
355 * kvm_mips_read_count() - Read the current count value.
356 * @vcpu: Virtual CPU.
358 * Read the current guest CP0_Count value, taking into account whether the timer
361 * Returns: The current guest CP0_Count value.
363 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu)
365 struct mips_coproc *cop0 = vcpu->arch.cop0;
367 /* If count disabled just read static copy of count */
368 if (kvm_mips_count_disabled(vcpu))
369 return kvm_read_c0_guest_count(cop0);
371 return kvm_mips_read_count_running(vcpu, ktime_get());
375 * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
376 * @vcpu: Virtual CPU.
377 * @count: Output pointer for CP0_Count value at point of freeze.
379 * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
380 * at the point it was frozen. It is guaranteed that any pending interrupts at
381 * the point it was frozen are handled, and none after that point.
383 * This is useful where the time/CP0_Count is needed in the calculation of the
386 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
388 * Returns: The ktime at the point of freeze.
390 static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu,
395 /* stop hrtimer before finding time */
396 hrtimer_cancel(&vcpu->arch.comparecount_timer);
399 /* find count at this point and handle pending hrtimer */
400 *count = kvm_mips_read_count_running(vcpu, now);
406 * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
407 * @vcpu: Virtual CPU.
408 * @now: ktime at point of resume.
409 * @count: CP0_Count at point of resume.
411 * Resumes the timer and updates the timer expiry based on @now and @count.
412 * This can be used in conjunction with kvm_mips_freeze_timer() when timer
413 * parameters need to be changed.
415 * It is guaranteed that a timer interrupt immediately after resume will be
416 * handled, but not if CP_Compare is exactly at @count. That case is already
417 * handled by kvm_mips_freeze_timer().
419 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
421 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
422 ktime_t now, uint32_t count)
424 struct mips_coproc *cop0 = vcpu->arch.cop0;
429 /* Calculate timeout (wrap 0 to 2^32) */
430 compare = kvm_read_c0_guest_compare(cop0);
431 delta = (u64)(uint32_t)(compare - count - 1) + 1;
432 delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
433 expire = ktime_add_ns(now, delta);
435 /* Update hrtimer to use new timeout */
436 hrtimer_cancel(&vcpu->arch.comparecount_timer);
437 hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
441 * kvm_mips_write_count() - Modify the count and update timer.
442 * @vcpu: Virtual CPU.
443 * @count: Guest CP0_Count value to set.
445 * Sets the CP0_Count value and updates the timer accordingly.
447 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count)
449 struct mips_coproc *cop0 = vcpu->arch.cop0;
453 now = kvm_mips_count_time(vcpu);
454 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
456 if (kvm_mips_count_disabled(vcpu))
457 /* The timer's disabled, adjust the static count */
458 kvm_write_c0_guest_count(cop0, count);
461 kvm_mips_resume_hrtimer(vcpu, now, count);
465 * kvm_mips_init_count() - Initialise timer.
466 * @vcpu: Virtual CPU.
468 * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set
469 * it going if it's enabled.
471 void kvm_mips_init_count(struct kvm_vcpu *vcpu)
474 vcpu->arch.count_hz = 100*1000*1000;
475 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32,
476 vcpu->arch.count_hz);
477 vcpu->arch.count_dyn_bias = 0;
480 kvm_mips_write_count(vcpu, 0);
484 * kvm_mips_set_count_hz() - Update the frequency of the timer.
485 * @vcpu: Virtual CPU.
486 * @count_hz: Frequency of CP0_Count timer in Hz.
488 * Change the frequency of the CP0_Count timer. This is done atomically so that
489 * CP0_Count is continuous and no timer interrupt is lost.
491 * Returns: -EINVAL if @count_hz is out of range.
494 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
496 struct mips_coproc *cop0 = vcpu->arch.cop0;
501 /* ensure the frequency is in a sensible range... */
502 if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
504 /* ... and has actually changed */
505 if (vcpu->arch.count_hz == count_hz)
508 /* Safely freeze timer so we can keep it continuous */
509 dc = kvm_mips_count_disabled(vcpu);
511 now = kvm_mips_count_time(vcpu);
512 count = kvm_read_c0_guest_count(cop0);
514 now = kvm_mips_freeze_hrtimer(vcpu, &count);
517 /* Update the frequency */
518 vcpu->arch.count_hz = count_hz;
519 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
520 vcpu->arch.count_dyn_bias = 0;
522 /* Calculate adjusted bias so dynamic count is unchanged */
523 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
525 /* Update and resume hrtimer */
527 kvm_mips_resume_hrtimer(vcpu, now, count);
532 * kvm_mips_write_compare() - Modify compare and update timer.
533 * @vcpu: Virtual CPU.
534 * @compare: New CP0_Compare value.
535 * @ack: Whether to acknowledge timer interrupt.
537 * Update CP0_Compare to a new value and update the timeout.
538 * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
539 * any pending timer interrupt is preserved.
541 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare, bool ack)
543 struct mips_coproc *cop0 = vcpu->arch.cop0;
545 u32 old_compare = kvm_read_c0_guest_compare(cop0);
549 /* if unchanged, must just be an ack */
550 if (old_compare == compare) {
553 kvm_mips_callbacks->dequeue_timer_int(vcpu);
554 kvm_write_c0_guest_compare(cop0, compare);
558 /* freeze_hrtimer() takes care of timer interrupts <= count */
559 dc = kvm_mips_count_disabled(vcpu);
561 now = kvm_mips_freeze_hrtimer(vcpu, &count);
564 kvm_mips_callbacks->dequeue_timer_int(vcpu);
566 kvm_write_c0_guest_compare(cop0, compare);
568 /* resume_hrtimer() takes care of timer interrupts > count */
570 kvm_mips_resume_hrtimer(vcpu, now, count);
574 * kvm_mips_count_disable() - Disable count.
575 * @vcpu: Virtual CPU.
577 * Disable the CP0_Count timer. A timer interrupt on or before the final stop
578 * time will be handled but not after.
580 * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
581 * count_ctl.DC has been set (count disabled).
583 * Returns: The time that the timer was stopped.
585 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
587 struct mips_coproc *cop0 = vcpu->arch.cop0;
592 hrtimer_cancel(&vcpu->arch.comparecount_timer);
594 /* Set the static count from the dynamic count, handling pending TI */
596 count = kvm_mips_read_count_running(vcpu, now);
597 kvm_write_c0_guest_count(cop0, count);
603 * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
604 * @vcpu: Virtual CPU.
606 * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
607 * before the final stop time will be handled if the timer isn't disabled by
608 * count_ctl.DC, but not after.
610 * Assumes CP0_Cause.DC is clear (count enabled).
612 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
614 struct mips_coproc *cop0 = vcpu->arch.cop0;
616 kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
617 if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
618 kvm_mips_count_disable(vcpu);
622 * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
623 * @vcpu: Virtual CPU.
625 * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
626 * the start time will be handled if the timer isn't disabled by count_ctl.DC,
627 * potentially before even returning, so the caller should be careful with
628 * ordering of CP0_Cause modifications so as not to lose it.
630 * Assumes CP0_Cause.DC is set (count disabled).
632 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
634 struct mips_coproc *cop0 = vcpu->arch.cop0;
637 kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
640 * Set the dynamic count to match the static count.
641 * This starts the hrtimer if count_ctl.DC allows it.
642 * Otherwise it conveniently updates the biases.
644 count = kvm_read_c0_guest_count(cop0);
645 kvm_mips_write_count(vcpu, count);
649 * kvm_mips_set_count_ctl() - Update the count control KVM register.
650 * @vcpu: Virtual CPU.
651 * @count_ctl: Count control register new value.
653 * Set the count control KVM register. The timer is updated accordingly.
655 * Returns: -EINVAL if reserved bits are set.
658 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
660 struct mips_coproc *cop0 = vcpu->arch.cop0;
661 s64 changed = count_ctl ^ vcpu->arch.count_ctl;
664 uint32_t count, compare;
666 /* Only allow defined bits to be changed */
667 if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
670 /* Apply new value */
671 vcpu->arch.count_ctl = count_ctl;
673 /* Master CP0_Count disable */
674 if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
675 /* Is CP0_Cause.DC already disabling CP0_Count? */
676 if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
677 if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
678 /* Just record the current time */
679 vcpu->arch.count_resume = ktime_get();
680 } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
681 /* disable timer and record current time */
682 vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
685 * Calculate timeout relative to static count at resume
686 * time (wrap 0 to 2^32).
688 count = kvm_read_c0_guest_count(cop0);
689 compare = kvm_read_c0_guest_compare(cop0);
690 delta = (u64)(uint32_t)(compare - count - 1) + 1;
691 delta = div_u64(delta * NSEC_PER_SEC,
692 vcpu->arch.count_hz);
693 expire = ktime_add_ns(vcpu->arch.count_resume, delta);
695 /* Handle pending interrupt */
697 if (ktime_compare(now, expire) >= 0)
698 /* Nothing should be waiting on the timeout */
699 kvm_mips_callbacks->queue_timer_int(vcpu);
701 /* Resume hrtimer without changing bias */
702 count = kvm_mips_read_count_running(vcpu, now);
703 kvm_mips_resume_hrtimer(vcpu, now, count);
711 * kvm_mips_set_count_resume() - Update the count resume KVM register.
712 * @vcpu: Virtual CPU.
713 * @count_resume: Count resume register new value.
715 * Set the count resume KVM register.
717 * Returns: -EINVAL if out of valid range (0..now).
720 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
723 * It doesn't make sense for the resume time to be in the future, as it
724 * would be possible for the next interrupt to be more than a full
725 * period in the future.
727 if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
730 vcpu->arch.count_resume = ns_to_ktime(count_resume);
735 * kvm_mips_count_timeout() - Push timer forward on timeout.
736 * @vcpu: Virtual CPU.
738 * Handle an hrtimer event by push the hrtimer forward a period.
740 * Returns: The hrtimer_restart value to return to the hrtimer subsystem.
742 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
744 /* Add the Count period to the current expiry time */
745 hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
746 vcpu->arch.count_period);
747 return HRTIMER_RESTART;
750 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
752 struct mips_coproc *cop0 = vcpu->arch.cop0;
753 enum emulation_result er = EMULATE_DONE;
755 if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
756 kvm_clear_c0_guest_status(cop0, ST0_ERL);
757 vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
758 } else if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
759 kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
760 kvm_read_c0_guest_epc(cop0));
761 kvm_clear_c0_guest_status(cop0, ST0_EXL);
762 vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
765 kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
773 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
775 kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
776 vcpu->arch.pending_exceptions);
778 ++vcpu->stat.wait_exits;
779 trace_kvm_exit(vcpu, WAIT_EXITS);
780 if (!vcpu->arch.pending_exceptions) {
782 kvm_vcpu_block(vcpu);
785 * We we are runnable, then definitely go off to user space to
786 * check if any I/O interrupts are pending.
788 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
789 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
790 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
798 * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that
799 * we can catch this, if things ever change
801 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
803 struct mips_coproc *cop0 = vcpu->arch.cop0;
804 uint32_t pc = vcpu->arch.pc;
806 kvm_err("[%#x] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0));
811 * kvm_mips_invalidate_guest_tlb() - Indicates a change in guest MMU map.
812 * @vcpu: VCPU with changed mappings.
813 * @tlb: TLB entry being removed.
815 * This is called to indicate a single change in guest MMU mappings, so that we
816 * can arrange TLB flushes on this and other CPUs.
818 static void kvm_mips_invalidate_guest_tlb(struct kvm_vcpu *vcpu,
819 struct kvm_mips_tlb *tlb)
824 /* No need to flush for entries which are already invalid */
825 if (!((tlb->tlb_lo0 | tlb->tlb_lo1) & MIPS3_PG_V))
827 /* User address space doesn't need flushing for KSeg2/3 changes */
828 user = tlb->tlb_hi < KVM_GUEST_KSEG0;
833 * Probe the shadow host TLB for the entry being overwritten, if one
834 * matches, invalidate it
836 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
838 /* Invalidate the whole ASID on other CPUs */
839 cpu = smp_processor_id();
840 for_each_possible_cpu(i) {
844 vcpu->arch.guest_user_asid[i] = 0;
845 vcpu->arch.guest_kernel_asid[i] = 0;
851 /* Write Guest TLB Entry @ Index */
852 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
854 struct mips_coproc *cop0 = vcpu->arch.cop0;
855 int index = kvm_read_c0_guest_index(cop0);
856 struct kvm_mips_tlb *tlb = NULL;
857 uint32_t pc = vcpu->arch.pc;
859 if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
860 kvm_debug("%s: illegal index: %d\n", __func__, index);
861 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
862 pc, index, kvm_read_c0_guest_entryhi(cop0),
863 kvm_read_c0_guest_entrylo0(cop0),
864 kvm_read_c0_guest_entrylo1(cop0),
865 kvm_read_c0_guest_pagemask(cop0));
866 index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
869 tlb = &vcpu->arch.guest_tlb[index];
871 kvm_mips_invalidate_guest_tlb(vcpu, tlb);
873 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
874 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
875 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
876 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
878 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
879 pc, index, kvm_read_c0_guest_entryhi(cop0),
880 kvm_read_c0_guest_entrylo0(cop0),
881 kvm_read_c0_guest_entrylo1(cop0),
882 kvm_read_c0_guest_pagemask(cop0));
887 /* Write Guest TLB Entry @ Random Index */
888 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
890 struct mips_coproc *cop0 = vcpu->arch.cop0;
891 struct kvm_mips_tlb *tlb = NULL;
892 uint32_t pc = vcpu->arch.pc;
895 get_random_bytes(&index, sizeof(index));
896 index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
898 tlb = &vcpu->arch.guest_tlb[index];
900 kvm_mips_invalidate_guest_tlb(vcpu, tlb);
902 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
903 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
904 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
905 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
907 kvm_debug("[%#x] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
908 pc, index, kvm_read_c0_guest_entryhi(cop0),
909 kvm_read_c0_guest_entrylo0(cop0),
910 kvm_read_c0_guest_entrylo1(cop0));
915 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
917 struct mips_coproc *cop0 = vcpu->arch.cop0;
918 long entryhi = kvm_read_c0_guest_entryhi(cop0);
919 uint32_t pc = vcpu->arch.pc;
922 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
924 kvm_write_c0_guest_index(cop0, index);
926 kvm_debug("[%#x] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
933 * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
934 * @vcpu: Virtual CPU.
936 * Finds the mask of bits which are writable in the guest's Config1 CP0
937 * register, by userland (currently read-only to the guest).
939 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
941 unsigned int mask = 0;
943 /* Permit FPU to be present if FPU is supported */
944 if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
945 mask |= MIPS_CONF1_FP;
951 * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
952 * @vcpu: Virtual CPU.
954 * Finds the mask of bits which are writable in the guest's Config3 CP0
955 * register, by userland (currently read-only to the guest).
957 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
959 /* Config4 is optional */
960 unsigned int mask = MIPS_CONF_M;
962 /* Permit MSA to be present if MSA is supported */
963 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
964 mask |= MIPS_CONF3_MSA;
970 * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
971 * @vcpu: Virtual CPU.
973 * Finds the mask of bits which are writable in the guest's Config4 CP0
974 * register, by userland (currently read-only to the guest).
976 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
978 /* Config5 is optional */
983 * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
984 * @vcpu: Virtual CPU.
986 * Finds the mask of bits which are writable in the guest's Config5 CP0
987 * register, by the guest itself.
989 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
991 unsigned int mask = 0;
993 /* Permit MSAEn changes if MSA supported and enabled */
994 if (kvm_mips_guest_has_msa(&vcpu->arch))
995 mask |= MIPS_CONF5_MSAEN;
998 * Permit guest FPU mode changes if FPU is enabled and the relevant
999 * feature exists according to FIR register.
1001 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1003 mask |= MIPS_CONF5_FRE;
1004 /* We don't support UFR or UFE */
1010 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
1011 uint32_t cause, struct kvm_run *run,
1012 struct kvm_vcpu *vcpu)
1014 struct mips_coproc *cop0 = vcpu->arch.cop0;
1015 enum emulation_result er = EMULATE_DONE;
1016 int32_t rt, rd, copz, sel, co_bit, op;
1017 uint32_t pc = vcpu->arch.pc;
1018 unsigned long curr_pc;
1022 * Update PC and hold onto current PC in case there is
1023 * an error and we want to rollback the PC
1025 curr_pc = vcpu->arch.pc;
1026 er = update_pc(vcpu, cause);
1027 if (er == EMULATE_FAIL)
1030 copz = (inst >> 21) & 0x1f;
1031 rt = (inst >> 16) & 0x1f;
1032 rd = (inst >> 11) & 0x1f;
1034 co_bit = (inst >> 25) & 1;
1040 case tlbr_op: /* Read indexed TLB entry */
1041 er = kvm_mips_emul_tlbr(vcpu);
1043 case tlbwi_op: /* Write indexed */
1044 er = kvm_mips_emul_tlbwi(vcpu);
1046 case tlbwr_op: /* Write random */
1047 er = kvm_mips_emul_tlbwr(vcpu);
1049 case tlbp_op: /* TLB Probe */
1050 er = kvm_mips_emul_tlbp(vcpu);
1053 kvm_err("!!!COP0_RFE!!!\n");
1056 er = kvm_mips_emul_eret(vcpu);
1057 goto dont_update_pc;
1060 er = kvm_mips_emul_wait(vcpu);
1066 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1067 cop0->stat[rd][sel]++;
1070 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1071 vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);
1072 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
1073 vcpu->arch.gprs[rt] = 0x0;
1074 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1075 kvm_mips_trans_mfc0(inst, opc, vcpu);
1078 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1080 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1081 kvm_mips_trans_mfc0(inst, opc, vcpu);
1086 ("[%#x] MFCz[%d][%d], vcpu->arch.gprs[%d]: %#lx\n",
1087 pc, rd, sel, rt, vcpu->arch.gprs[rt]);
1092 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1096 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1097 cop0->stat[rd][sel]++;
1099 if ((rd == MIPS_CP0_TLB_INDEX)
1100 && (vcpu->arch.gprs[rt] >=
1101 KVM_MIPS_GUEST_TLB_SIZE)) {
1102 kvm_err("Invalid TLB Index: %ld",
1103 vcpu->arch.gprs[rt]);
1107 #define C0_EBASE_CORE_MASK 0xff
1108 if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
1109 /* Preserve CORE number */
1110 kvm_change_c0_guest_ebase(cop0,
1111 ~(C0_EBASE_CORE_MASK),
1112 vcpu->arch.gprs[rt]);
1113 kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n",
1114 kvm_read_c0_guest_ebase(cop0));
1115 } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
1117 vcpu->arch.gprs[rt] & ASID_MASK;
1118 if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
1119 ((kvm_read_c0_guest_entryhi(cop0) &
1120 ASID_MASK) != nasid)) {
1121 kvm_debug("MTCz, change ASID from %#lx to %#lx\n",
1122 kvm_read_c0_guest_entryhi(cop0)
1128 /* Blow away the shadow host TLBs */
1129 kvm_mips_flush_host_tlb(1);
1130 cpu = smp_processor_id();
1131 for_each_possible_cpu(i)
1133 vcpu->arch.guest_user_asid[i] = 0;
1134 vcpu->arch.guest_kernel_asid[i] = 0;
1138 kvm_write_c0_guest_entryhi(cop0,
1139 vcpu->arch.gprs[rt]);
1141 /* Are we writing to COUNT */
1142 else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1143 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1145 } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
1146 kvm_debug("[%#x] MTCz, COMPARE %#lx <- %#lx\n",
1147 pc, kvm_read_c0_guest_compare(cop0),
1148 vcpu->arch.gprs[rt]);
1150 /* If we are writing to COMPARE */
1151 /* Clear pending timer interrupt, if any */
1152 kvm_mips_write_compare(vcpu,
1153 vcpu->arch.gprs[rt],
1155 } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1156 unsigned int old_val, val, change;
1158 old_val = kvm_read_c0_guest_status(cop0);
1159 val = vcpu->arch.gprs[rt];
1160 change = val ^ old_val;
1162 /* Make sure that the NMI bit is never set */
1166 * Don't allow CU1 or FR to be set unless FPU
1167 * capability enabled and exists in guest
1170 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1171 val &= ~(ST0_CU1 | ST0_FR);
1174 * Also don't allow FR to be set if host doesn't
1177 if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
1181 /* Handle changes in FPU mode */
1185 * FPU and Vector register state is made
1186 * UNPREDICTABLE by a change of FR, so don't
1187 * even bother saving it.
1189 if (change & ST0_FR)
1193 * If MSA state is already live, it is undefined
1194 * how it interacts with FR=0 FPU state, and we
1195 * don't want to hit reserved instruction
1196 * exceptions trying to save the MSA state later
1197 * when CU=1 && FR=1, so play it safe and save
1200 if (change & ST0_CU1 && !(val & ST0_FR) &&
1201 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1205 * Propagate CU1 (FPU enable) changes
1206 * immediately if the FPU context is already
1207 * loaded. When disabling we leave the context
1208 * loaded so it can be quickly enabled again in
1211 if (change & ST0_CU1 &&
1212 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1213 change_c0_status(ST0_CU1, val);
1217 kvm_write_c0_guest_status(cop0, val);
1219 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1221 * If FPU present, we need CU1/FR bits to take
1222 * effect fairly soon.
1224 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1225 kvm_mips_trans_mtc0(inst, opc, vcpu);
1227 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1228 unsigned int old_val, val, change, wrmask;
1230 old_val = kvm_read_c0_guest_config5(cop0);
1231 val = vcpu->arch.gprs[rt];
1233 /* Only a few bits are writable in Config5 */
1234 wrmask = kvm_mips_config5_wrmask(vcpu);
1235 change = (val ^ old_val) & wrmask;
1236 val = old_val ^ change;
1239 /* Handle changes in FPU/MSA modes */
1243 * Propagate FRE changes immediately if the FPU
1244 * context is already loaded.
1246 if (change & MIPS_CONF5_FRE &&
1247 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1248 change_c0_config5(MIPS_CONF5_FRE, val);
1251 * Propagate MSAEn changes immediately if the
1252 * MSA context is already loaded. When disabling
1253 * we leave the context loaded so it can be
1254 * quickly enabled again in the near future.
1256 if (change & MIPS_CONF5_MSAEN &&
1257 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1258 change_c0_config5(MIPS_CONF5_MSAEN,
1263 kvm_write_c0_guest_config5(cop0, val);
1264 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1265 uint32_t old_cause, new_cause;
1267 old_cause = kvm_read_c0_guest_cause(cop0);
1268 new_cause = vcpu->arch.gprs[rt];
1269 /* Update R/W bits */
1270 kvm_change_c0_guest_cause(cop0, 0x08800300,
1272 /* DC bit enabling/disabling timer? */
1273 if ((old_cause ^ new_cause) & CAUSEF_DC) {
1274 if (new_cause & CAUSEF_DC)
1275 kvm_mips_count_disable_cause(vcpu);
1277 kvm_mips_count_enable_cause(vcpu);
1280 cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
1281 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1282 kvm_mips_trans_mtc0(inst, opc, vcpu);
1286 kvm_debug("[%#x] MTCz, cop0->reg[%d][%d]: %#lx\n", pc,
1287 rd, sel, cop0->reg[rd][sel]);
1291 kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
1292 vcpu->arch.pc, rt, rd, sel);
1297 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
1298 cop0->stat[MIPS_CP0_STATUS][0]++;
1301 vcpu->arch.gprs[rt] =
1302 kvm_read_c0_guest_status(cop0);
1306 kvm_debug("[%#lx] mfmcz_op: EI\n",
1308 kvm_set_c0_guest_status(cop0, ST0_IE);
1310 kvm_debug("[%#lx] mfmcz_op: DI\n",
1312 kvm_clear_c0_guest_status(cop0, ST0_IE);
1320 cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
1322 (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
1324 * We don't support any shadow register sets, so
1325 * SRSCtl[PSS] == SRSCtl[CSS] = 0
1331 kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
1332 vcpu->arch.gprs[rt]);
1333 vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
1337 kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
1338 vcpu->arch.pc, copz);
1345 /* Rollback PC only if emulation was unsuccessful */
1346 if (er == EMULATE_FAIL)
1347 vcpu->arch.pc = curr_pc;
1351 * This is for special instructions whose emulation
1352 * updates the PC, so do not overwrite the PC under
1359 enum emulation_result kvm_mips_emulate_store(uint32_t inst, uint32_t cause,
1360 struct kvm_run *run,
1361 struct kvm_vcpu *vcpu)
1363 enum emulation_result er = EMULATE_DO_MMIO;
1364 int32_t op, base, rt, offset;
1366 void *data = run->mmio.data;
1367 unsigned long curr_pc;
1370 * Update PC and hold onto current PC in case there is
1371 * an error and we want to rollback the PC
1373 curr_pc = vcpu->arch.pc;
1374 er = update_pc(vcpu, cause);
1375 if (er == EMULATE_FAIL)
1378 rt = (inst >> 16) & 0x1f;
1379 base = (inst >> 21) & 0x1f;
1380 offset = inst & 0xffff;
1381 op = (inst >> 26) & 0x3f;
1386 if (bytes > sizeof(run->mmio.data)) {
1387 kvm_err("%s: bad MMIO length: %d\n", __func__,
1390 run->mmio.phys_addr =
1391 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1393 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1397 run->mmio.len = bytes;
1398 run->mmio.is_write = 1;
1399 vcpu->mmio_needed = 1;
1400 vcpu->mmio_is_write = 1;
1401 *(u8 *) data = vcpu->arch.gprs[rt];
1402 kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1403 vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt],
1410 if (bytes > sizeof(run->mmio.data)) {
1411 kvm_err("%s: bad MMIO length: %d\n", __func__,
1414 run->mmio.phys_addr =
1415 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1417 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1422 run->mmio.len = bytes;
1423 run->mmio.is_write = 1;
1424 vcpu->mmio_needed = 1;
1425 vcpu->mmio_is_write = 1;
1426 *(uint32_t *) data = vcpu->arch.gprs[rt];
1428 kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1429 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1430 vcpu->arch.gprs[rt], *(uint32_t *) data);
1435 if (bytes > sizeof(run->mmio.data)) {
1436 kvm_err("%s: bad MMIO length: %d\n", __func__,
1439 run->mmio.phys_addr =
1440 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1442 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1447 run->mmio.len = bytes;
1448 run->mmio.is_write = 1;
1449 vcpu->mmio_needed = 1;
1450 vcpu->mmio_is_write = 1;
1451 *(uint16_t *) data = vcpu->arch.gprs[rt];
1453 kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1454 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1455 vcpu->arch.gprs[rt], *(uint32_t *) data);
1459 kvm_err("Store not yet supported");
1464 /* Rollback PC if emulation was unsuccessful */
1465 if (er == EMULATE_FAIL)
1466 vcpu->arch.pc = curr_pc;
1471 enum emulation_result kvm_mips_emulate_load(uint32_t inst, uint32_t cause,
1472 struct kvm_run *run,
1473 struct kvm_vcpu *vcpu)
1475 enum emulation_result er = EMULATE_DO_MMIO;
1476 unsigned long curr_pc;
1477 int32_t op, base, rt, offset;
1480 rt = (inst >> 16) & 0x1f;
1481 base = (inst >> 21) & 0x1f;
1482 offset = inst & 0xffff;
1483 op = (inst >> 26) & 0x3f;
1486 * Find the resume PC now while we have safe and easy access to the
1487 * prior branch instruction, and save it for
1488 * kvm_mips_complete_mmio_load() to restore later.
1490 curr_pc = vcpu->arch.pc;
1491 er = update_pc(vcpu, cause);
1492 if (er == EMULATE_FAIL)
1494 vcpu->arch.io_pc = vcpu->arch.pc;
1495 vcpu->arch.pc = curr_pc;
1497 vcpu->arch.io_gpr = rt;
1502 if (bytes > sizeof(run->mmio.data)) {
1503 kvm_err("%s: bad MMIO length: %d\n", __func__,
1508 run->mmio.phys_addr =
1509 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1511 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1516 run->mmio.len = bytes;
1517 run->mmio.is_write = 0;
1518 vcpu->mmio_needed = 1;
1519 vcpu->mmio_is_write = 0;
1525 if (bytes > sizeof(run->mmio.data)) {
1526 kvm_err("%s: bad MMIO length: %d\n", __func__,
1531 run->mmio.phys_addr =
1532 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1534 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1539 run->mmio.len = bytes;
1540 run->mmio.is_write = 0;
1541 vcpu->mmio_needed = 1;
1542 vcpu->mmio_is_write = 0;
1545 vcpu->mmio_needed = 2;
1547 vcpu->mmio_needed = 1;
1554 if (bytes > sizeof(run->mmio.data)) {
1555 kvm_err("%s: bad MMIO length: %d\n", __func__,
1560 run->mmio.phys_addr =
1561 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1563 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1568 run->mmio.len = bytes;
1569 run->mmio.is_write = 0;
1570 vcpu->mmio_is_write = 0;
1573 vcpu->mmio_needed = 2;
1575 vcpu->mmio_needed = 1;
1580 kvm_err("Load not yet supported");
1588 int kvm_mips_sync_icache(unsigned long va, struct kvm_vcpu *vcpu)
1590 unsigned long offset = (va & ~PAGE_MASK);
1591 struct kvm *kvm = vcpu->kvm;
1596 gfn = va >> PAGE_SHIFT;
1598 if (gfn >= kvm->arch.guest_pmap_npages) {
1599 kvm_err("%s: Invalid gfn: %#llx\n", __func__, gfn);
1600 kvm_mips_dump_host_tlbs();
1601 kvm_arch_vcpu_dump_regs(vcpu);
1604 pfn = kvm->arch.guest_pmap[gfn];
1605 pa = (pfn << PAGE_SHIFT) | offset;
1607 kvm_debug("%s: va: %#lx, unmapped: %#x\n", __func__, va,
1610 local_flush_icache_range(CKSEG0ADDR(pa), 32);
1614 #define MIPS_CACHE_OP_INDEX_INV 0x0
1615 #define MIPS_CACHE_OP_INDEX_LD_TAG 0x1
1616 #define MIPS_CACHE_OP_INDEX_ST_TAG 0x2
1617 #define MIPS_CACHE_OP_IMP 0x3
1618 #define MIPS_CACHE_OP_HIT_INV 0x4
1619 #define MIPS_CACHE_OP_FILL_WB_INV 0x5
1620 #define MIPS_CACHE_OP_HIT_HB 0x6
1621 #define MIPS_CACHE_OP_FETCH_LOCK 0x7
1623 #define MIPS_CACHE_ICACHE 0x0
1624 #define MIPS_CACHE_DCACHE 0x1
1625 #define MIPS_CACHE_SEC 0x3
1627 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
1629 struct kvm_run *run,
1630 struct kvm_vcpu *vcpu)
1632 struct mips_coproc *cop0 = vcpu->arch.cop0;
1633 enum emulation_result er = EMULATE_DONE;
1634 int32_t offset, cache, op_inst, op, base;
1635 struct kvm_vcpu_arch *arch = &vcpu->arch;
1637 unsigned long curr_pc;
1640 * Update PC and hold onto current PC in case there is
1641 * an error and we want to rollback the PC
1643 curr_pc = vcpu->arch.pc;
1644 er = update_pc(vcpu, cause);
1645 if (er == EMULATE_FAIL)
1648 base = (inst >> 21) & 0x1f;
1649 op_inst = (inst >> 16) & 0x1f;
1650 offset = (int16_t)inst;
1651 cache = (inst >> 16) & 0x3;
1652 op = (inst >> 18) & 0x7;
1654 va = arch->gprs[base] + offset;
1656 kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1657 cache, op, base, arch->gprs[base], offset);
1660 * Treat INDEX_INV as a nop, basically issued by Linux on startup to
1661 * invalidate the caches entirely by stepping through all the
1664 if (op == MIPS_CACHE_OP_INDEX_INV) {
1665 kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1666 vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
1667 arch->gprs[base], offset);
1669 if (cache == MIPS_CACHE_DCACHE)
1671 else if (cache == MIPS_CACHE_ICACHE)
1674 kvm_err("%s: unsupported CACHE INDEX operation\n",
1676 return EMULATE_FAIL;
1679 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1680 kvm_mips_trans_cache_index(inst, opc, vcpu);
1686 if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) {
1687 if (kvm_mips_host_tlb_lookup(vcpu, va) < 0 &&
1688 kvm_mips_handle_kseg0_tlb_fault(va, vcpu)) {
1689 kvm_err("%s: handling mapped kseg0 tlb fault for %lx, vcpu: %p, ASID: %#lx\n",
1690 __func__, va, vcpu, read_c0_entryhi());
1695 } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) ||
1696 KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) {
1699 /* If an entry already exists then skip */
1700 if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0)
1704 * If address not in the guest TLB, then give the guest a fault,
1705 * the resulting handler will do the right thing
1707 index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
1708 (kvm_read_c0_guest_entryhi
1709 (cop0) & ASID_MASK));
1712 vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
1713 vcpu->arch.host_cp0_badvaddr = va;
1714 er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
1717 goto dont_update_pc;
1719 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
1721 * Check if the entry is valid, if not then setup a TLB
1722 * invalid exception to the guest
1724 if (!TLB_IS_VALID(*tlb, va)) {
1725 er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
1728 goto dont_update_pc;
1731 * We fault an entry from the guest tlb to the
1734 if (kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb,
1736 kvm_err("%s: handling mapped seg tlb fault for %lx, index: %u, vcpu: %p, ASID: %#lx\n",
1737 __func__, va, index, vcpu,
1745 kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1746 cache, op, base, arch->gprs[base], offset);
1749 goto dont_update_pc;
1754 /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
1755 if (cache == MIPS_CACHE_DCACHE
1756 && (op == MIPS_CACHE_OP_FILL_WB_INV
1757 || op == MIPS_CACHE_OP_HIT_INV)) {
1758 flush_dcache_line(va);
1760 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1762 * Replace the CACHE instruction, with a SYNCI, not the same,
1765 kvm_mips_trans_cache_va(inst, opc, vcpu);
1767 } else if (op == MIPS_CACHE_OP_HIT_INV && cache == MIPS_CACHE_ICACHE) {
1768 flush_dcache_line(va);
1769 flush_icache_line(va);
1771 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1772 /* Replace the CACHE instruction, with a SYNCI */
1773 kvm_mips_trans_cache_va(inst, opc, vcpu);
1776 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1777 cache, op, base, arch->gprs[base], offset);
1780 goto dont_update_pc;
1787 vcpu->arch.pc = curr_pc;
1792 enum emulation_result kvm_mips_emulate_inst(unsigned long cause, uint32_t *opc,
1793 struct kvm_run *run,
1794 struct kvm_vcpu *vcpu)
1796 enum emulation_result er = EMULATE_DONE;
1799 /* Fetch the instruction. */
1800 if (cause & CAUSEF_BD)
1803 inst = kvm_get_inst(opc, vcpu);
1805 switch (((union mips_instruction)inst).r_format.opcode) {
1807 er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
1812 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1819 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1823 ++vcpu->stat.cache_exits;
1824 trace_kvm_exit(vcpu, CACHE_EXITS);
1825 er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
1829 kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
1831 kvm_arch_vcpu_dump_regs(vcpu);
1839 enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
1841 struct kvm_run *run,
1842 struct kvm_vcpu *vcpu)
1844 struct mips_coproc *cop0 = vcpu->arch.cop0;
1845 struct kvm_vcpu_arch *arch = &vcpu->arch;
1846 enum emulation_result er = EMULATE_DONE;
1848 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1850 kvm_write_c0_guest_epc(cop0, arch->pc);
1851 kvm_set_c0_guest_status(cop0, ST0_EXL);
1853 if (cause & CAUSEF_BD)
1854 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1856 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1858 kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
1860 kvm_change_c0_guest_cause(cop0, (0xff),
1861 (T_SYSCALL << CAUSEB_EXCCODE));
1863 /* Set PC to the exception entry point */
1864 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1867 kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
1874 enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
1876 struct kvm_run *run,
1877 struct kvm_vcpu *vcpu)
1879 struct mips_coproc *cop0 = vcpu->arch.cop0;
1880 struct kvm_vcpu_arch *arch = &vcpu->arch;
1881 unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
1882 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1884 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1886 kvm_write_c0_guest_epc(cop0, arch->pc);
1887 kvm_set_c0_guest_status(cop0, ST0_EXL);
1889 if (cause & CAUSEF_BD)
1890 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1892 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1894 kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
1897 /* set pc to the exception entry point */
1898 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1901 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1904 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1907 kvm_change_c0_guest_cause(cop0, (0xff),
1908 (T_TLB_LD_MISS << CAUSEB_EXCCODE));
1910 /* setup badvaddr, context and entryhi registers for the guest */
1911 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1912 /* XXXKYMA: is the context register used by linux??? */
1913 kvm_write_c0_guest_entryhi(cop0, entryhi);
1914 /* Blow away the shadow host TLBs */
1915 kvm_mips_flush_host_tlb(1);
1917 return EMULATE_DONE;
1920 enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
1922 struct kvm_run *run,
1923 struct kvm_vcpu *vcpu)
1925 struct mips_coproc *cop0 = vcpu->arch.cop0;
1926 struct kvm_vcpu_arch *arch = &vcpu->arch;
1927 unsigned long entryhi =
1928 (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1929 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1931 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1933 kvm_write_c0_guest_epc(cop0, arch->pc);
1934 kvm_set_c0_guest_status(cop0, ST0_EXL);
1936 if (cause & CAUSEF_BD)
1937 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1939 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1941 kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
1944 /* set pc to the exception entry point */
1945 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1948 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1950 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1953 kvm_change_c0_guest_cause(cop0, (0xff),
1954 (T_TLB_LD_MISS << CAUSEB_EXCCODE));
1956 /* setup badvaddr, context and entryhi registers for the guest */
1957 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1958 /* XXXKYMA: is the context register used by linux??? */
1959 kvm_write_c0_guest_entryhi(cop0, entryhi);
1960 /* Blow away the shadow host TLBs */
1961 kvm_mips_flush_host_tlb(1);
1963 return EMULATE_DONE;
1966 enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
1968 struct kvm_run *run,
1969 struct kvm_vcpu *vcpu)
1971 struct mips_coproc *cop0 = vcpu->arch.cop0;
1972 struct kvm_vcpu_arch *arch = &vcpu->arch;
1973 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1974 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1976 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1978 kvm_write_c0_guest_epc(cop0, arch->pc);
1979 kvm_set_c0_guest_status(cop0, ST0_EXL);
1981 if (cause & CAUSEF_BD)
1982 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1984 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1986 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1989 /* Set PC to the exception entry point */
1990 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1992 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1994 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1997 kvm_change_c0_guest_cause(cop0, (0xff),
1998 (T_TLB_ST_MISS << CAUSEB_EXCCODE));
2000 /* setup badvaddr, context and entryhi registers for the guest */
2001 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2002 /* XXXKYMA: is the context register used by linux??? */
2003 kvm_write_c0_guest_entryhi(cop0, entryhi);
2004 /* Blow away the shadow host TLBs */
2005 kvm_mips_flush_host_tlb(1);
2007 return EMULATE_DONE;
2010 enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
2012 struct kvm_run *run,
2013 struct kvm_vcpu *vcpu)
2015 struct mips_coproc *cop0 = vcpu->arch.cop0;
2016 struct kvm_vcpu_arch *arch = &vcpu->arch;
2017 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2018 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
2020 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2022 kvm_write_c0_guest_epc(cop0, arch->pc);
2023 kvm_set_c0_guest_status(cop0, ST0_EXL);
2025 if (cause & CAUSEF_BD)
2026 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2028 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2030 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
2033 /* Set PC to the exception entry point */
2034 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2036 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
2038 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2041 kvm_change_c0_guest_cause(cop0, (0xff),
2042 (T_TLB_ST_MISS << CAUSEB_EXCCODE));
2044 /* setup badvaddr, context and entryhi registers for the guest */
2045 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2046 /* XXXKYMA: is the context register used by linux??? */
2047 kvm_write_c0_guest_entryhi(cop0, entryhi);
2048 /* Blow away the shadow host TLBs */
2049 kvm_mips_flush_host_tlb(1);
2051 return EMULATE_DONE;
2054 /* TLBMOD: store into address matching TLB with Dirty bit off */
2055 enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, uint32_t *opc,
2056 struct kvm_run *run,
2057 struct kvm_vcpu *vcpu)
2059 enum emulation_result er = EMULATE_DONE;
2061 struct mips_coproc *cop0 = vcpu->arch.cop0;
2062 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2063 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
2066 /* If address not in the guest TLB, then we are in trouble */
2067 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
2069 /* XXXKYMA Invalidate and retry */
2070 kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr);
2071 kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n",
2073 kvm_mips_dump_guest_tlbs(vcpu);
2074 kvm_mips_dump_host_tlbs();
2075 return EMULATE_FAIL;
2079 er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu);
2083 enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
2085 struct kvm_run *run,
2086 struct kvm_vcpu *vcpu)
2088 struct mips_coproc *cop0 = vcpu->arch.cop0;
2089 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2090 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
2091 struct kvm_vcpu_arch *arch = &vcpu->arch;
2093 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2095 kvm_write_c0_guest_epc(cop0, arch->pc);
2096 kvm_set_c0_guest_status(cop0, ST0_EXL);
2098 if (cause & CAUSEF_BD)
2099 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2101 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2103 kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
2106 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2108 kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
2110 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2113 kvm_change_c0_guest_cause(cop0, (0xff), (T_TLB_MOD << CAUSEB_EXCCODE));
2115 /* setup badvaddr, context and entryhi registers for the guest */
2116 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2117 /* XXXKYMA: is the context register used by linux??? */
2118 kvm_write_c0_guest_entryhi(cop0, entryhi);
2119 /* Blow away the shadow host TLBs */
2120 kvm_mips_flush_host_tlb(1);
2122 return EMULATE_DONE;
2125 enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
2127 struct kvm_run *run,
2128 struct kvm_vcpu *vcpu)
2130 struct mips_coproc *cop0 = vcpu->arch.cop0;
2131 struct kvm_vcpu_arch *arch = &vcpu->arch;
2133 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2135 kvm_write_c0_guest_epc(cop0, arch->pc);
2136 kvm_set_c0_guest_status(cop0, ST0_EXL);
2138 if (cause & CAUSEF_BD)
2139 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2141 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2145 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2147 kvm_change_c0_guest_cause(cop0, (0xff),
2148 (T_COP_UNUSABLE << CAUSEB_EXCCODE));
2149 kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
2151 return EMULATE_DONE;
2154 enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
2156 struct kvm_run *run,
2157 struct kvm_vcpu *vcpu)
2159 struct mips_coproc *cop0 = vcpu->arch.cop0;
2160 struct kvm_vcpu_arch *arch = &vcpu->arch;
2161 enum emulation_result er = EMULATE_DONE;
2163 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2165 kvm_write_c0_guest_epc(cop0, arch->pc);
2166 kvm_set_c0_guest_status(cop0, ST0_EXL);
2168 if (cause & CAUSEF_BD)
2169 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2171 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2173 kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
2175 kvm_change_c0_guest_cause(cop0, (0xff),
2176 (T_RES_INST << CAUSEB_EXCCODE));
2178 /* Set PC to the exception entry point */
2179 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2182 kvm_err("Trying to deliver RI when EXL is already set\n");
2189 enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
2191 struct kvm_run *run,
2192 struct kvm_vcpu *vcpu)
2194 struct mips_coproc *cop0 = vcpu->arch.cop0;
2195 struct kvm_vcpu_arch *arch = &vcpu->arch;
2196 enum emulation_result er = EMULATE_DONE;
2198 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2200 kvm_write_c0_guest_epc(cop0, arch->pc);
2201 kvm_set_c0_guest_status(cop0, ST0_EXL);
2203 if (cause & CAUSEF_BD)
2204 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2206 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2208 kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
2210 kvm_change_c0_guest_cause(cop0, (0xff),
2211 (T_BREAK << CAUSEB_EXCCODE));
2213 /* Set PC to the exception entry point */
2214 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2217 kvm_err("Trying to deliver BP when EXL is already set\n");
2224 enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
2226 struct kvm_run *run,
2227 struct kvm_vcpu *vcpu)
2229 struct mips_coproc *cop0 = vcpu->arch.cop0;
2230 struct kvm_vcpu_arch *arch = &vcpu->arch;
2231 enum emulation_result er = EMULATE_DONE;
2233 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2235 kvm_write_c0_guest_epc(cop0, arch->pc);
2236 kvm_set_c0_guest_status(cop0, ST0_EXL);
2238 if (cause & CAUSEF_BD)
2239 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2241 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2243 kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
2245 kvm_change_c0_guest_cause(cop0, (0xff),
2246 (T_TRAP << CAUSEB_EXCCODE));
2248 /* Set PC to the exception entry point */
2249 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2252 kvm_err("Trying to deliver TRAP when EXL is already set\n");
2259 enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
2261 struct kvm_run *run,
2262 struct kvm_vcpu *vcpu)
2264 struct mips_coproc *cop0 = vcpu->arch.cop0;
2265 struct kvm_vcpu_arch *arch = &vcpu->arch;
2266 enum emulation_result er = EMULATE_DONE;
2268 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2270 kvm_write_c0_guest_epc(cop0, arch->pc);
2271 kvm_set_c0_guest_status(cop0, ST0_EXL);
2273 if (cause & CAUSEF_BD)
2274 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2276 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2278 kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
2280 kvm_change_c0_guest_cause(cop0, (0xff),
2281 (T_MSAFPE << CAUSEB_EXCCODE));
2283 /* Set PC to the exception entry point */
2284 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2287 kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
2294 enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
2296 struct kvm_run *run,
2297 struct kvm_vcpu *vcpu)
2299 struct mips_coproc *cop0 = vcpu->arch.cop0;
2300 struct kvm_vcpu_arch *arch = &vcpu->arch;
2301 enum emulation_result er = EMULATE_DONE;
2303 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2305 kvm_write_c0_guest_epc(cop0, arch->pc);
2306 kvm_set_c0_guest_status(cop0, ST0_EXL);
2308 if (cause & CAUSEF_BD)
2309 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2311 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2313 kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
2315 kvm_change_c0_guest_cause(cop0, (0xff),
2316 (T_FPE << CAUSEB_EXCCODE));
2318 /* Set PC to the exception entry point */
2319 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2322 kvm_err("Trying to deliver FPE when EXL is already set\n");
2329 enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
2331 struct kvm_run *run,
2332 struct kvm_vcpu *vcpu)
2334 struct mips_coproc *cop0 = vcpu->arch.cop0;
2335 struct kvm_vcpu_arch *arch = &vcpu->arch;
2336 enum emulation_result er = EMULATE_DONE;
2338 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2340 kvm_write_c0_guest_epc(cop0, arch->pc);
2341 kvm_set_c0_guest_status(cop0, ST0_EXL);
2343 if (cause & CAUSEF_BD)
2344 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2346 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2348 kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
2350 kvm_change_c0_guest_cause(cop0, (0xff),
2351 (T_MSADIS << CAUSEB_EXCCODE));
2353 /* Set PC to the exception entry point */
2354 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2357 kvm_err("Trying to deliver MSADIS when EXL is already set\n");
2364 /* ll/sc, rdhwr, sync emulation */
2366 #define OPCODE 0xfc000000
2367 #define BASE 0x03e00000
2368 #define RT 0x001f0000
2369 #define OFFSET 0x0000ffff
2370 #define LL 0xc0000000
2371 #define SC 0xe0000000
2372 #define SPEC0 0x00000000
2373 #define SPEC3 0x7c000000
2374 #define RD 0x0000f800
2375 #define FUNC 0x0000003f
2376 #define SYNC 0x0000000f
2377 #define RDHWR 0x0000003b
2379 enum emulation_result kvm_mips_handle_ri(unsigned long cause, uint32_t *opc,
2380 struct kvm_run *run,
2381 struct kvm_vcpu *vcpu)
2383 struct mips_coproc *cop0 = vcpu->arch.cop0;
2384 struct kvm_vcpu_arch *arch = &vcpu->arch;
2385 enum emulation_result er = EMULATE_DONE;
2386 unsigned long curr_pc;
2390 * Update PC and hold onto current PC in case there is
2391 * an error and we want to rollback the PC
2393 curr_pc = vcpu->arch.pc;
2394 er = update_pc(vcpu, cause);
2395 if (er == EMULATE_FAIL)
2398 /* Fetch the instruction. */
2399 if (cause & CAUSEF_BD)
2402 inst = kvm_get_inst(opc, vcpu);
2404 if (inst == KVM_INVALID_INST) {
2405 kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
2406 return EMULATE_FAIL;
2409 if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
2410 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2411 int rd = (inst & RD) >> 11;
2412 int rt = (inst & RT) >> 16;
2413 /* If usermode, check RDHWR rd is allowed by guest HWREna */
2414 if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
2415 kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
2420 case 0: /* CPU number */
2423 case 1: /* SYNCI length */
2424 arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
2425 current_cpu_data.icache.linesz);
2427 case 2: /* Read count register */
2428 arch->gprs[rt] = kvm_mips_read_count(vcpu);
2430 case 3: /* Count register resolution */
2431 switch (current_cpu_data.cputype) {
2441 arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
2445 kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
2449 kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
2453 return EMULATE_DONE;
2457 * Rollback PC (if in branch delay slot then the PC already points to
2458 * branch target), and pass the RI exception to the guest OS.
2460 vcpu->arch.pc = curr_pc;
2461 return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
2464 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
2465 struct kvm_run *run)
2467 unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
2468 enum emulation_result er = EMULATE_DONE;
2470 if (run->mmio.len > sizeof(*gpr)) {
2471 kvm_err("Bad MMIO length: %d", run->mmio.len);
2476 /* Restore saved resume PC */
2477 vcpu->arch.pc = vcpu->arch.io_pc;
2479 switch (run->mmio.len) {
2481 *gpr = *(int32_t *) run->mmio.data;
2485 if (vcpu->mmio_needed == 2)
2486 *gpr = *(int16_t *) run->mmio.data;
2488 *gpr = *(uint16_t *)run->mmio.data;
2492 if (vcpu->mmio_needed == 2)
2493 *gpr = *(int8_t *) run->mmio.data;
2495 *gpr = *(u8 *) run->mmio.data;
2503 static enum emulation_result kvm_mips_emulate_exc(unsigned long cause,
2505 struct kvm_run *run,
2506 struct kvm_vcpu *vcpu)
2508 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2509 struct mips_coproc *cop0 = vcpu->arch.cop0;
2510 struct kvm_vcpu_arch *arch = &vcpu->arch;
2511 enum emulation_result er = EMULATE_DONE;
2513 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2515 kvm_write_c0_guest_epc(cop0, arch->pc);
2516 kvm_set_c0_guest_status(cop0, ST0_EXL);
2518 if (cause & CAUSEF_BD)
2519 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2521 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2523 kvm_change_c0_guest_cause(cop0, (0xff),
2524 (exccode << CAUSEB_EXCCODE));
2526 /* Set PC to the exception entry point */
2527 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2528 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2530 kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
2531 exccode, kvm_read_c0_guest_epc(cop0),
2532 kvm_read_c0_guest_badvaddr(cop0));
2534 kvm_err("Trying to deliver EXC when EXL is already set\n");
2541 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
2543 struct kvm_run *run,
2544 struct kvm_vcpu *vcpu)
2546 enum emulation_result er = EMULATE_DONE;
2547 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2548 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
2550 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2564 case T_COP_UNUSABLE:
2565 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
2566 er = EMULATE_PRIV_FAIL;
2574 * We we are accessing Guest kernel space, then send an
2575 * address error exception to the guest
2577 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2578 kvm_debug("%s: LD MISS @ %#lx\n", __func__,
2581 cause |= (T_ADDR_ERR_LD << CAUSEB_EXCCODE);
2582 er = EMULATE_PRIV_FAIL;
2588 * We we are accessing Guest kernel space, then send an
2589 * address error exception to the guest
2591 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2592 kvm_debug("%s: ST MISS @ %#lx\n", __func__,
2595 cause |= (T_ADDR_ERR_ST << CAUSEB_EXCCODE);
2596 er = EMULATE_PRIV_FAIL;
2601 kvm_debug("%s: address error ST @ %#lx\n", __func__,
2603 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2605 cause |= (T_TLB_ST_MISS << CAUSEB_EXCCODE);
2607 er = EMULATE_PRIV_FAIL;
2610 kvm_debug("%s: address error LD @ %#lx\n", __func__,
2612 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2614 cause |= (T_TLB_LD_MISS << CAUSEB_EXCCODE);
2616 er = EMULATE_PRIV_FAIL;
2619 er = EMULATE_PRIV_FAIL;
2624 if (er == EMULATE_PRIV_FAIL)
2625 kvm_mips_emulate_exc(cause, opc, run, vcpu);
2631 * User Address (UA) fault, this could happen if
2632 * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
2633 * case we pass on the fault to the guest kernel and let it handle it.
2634 * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
2635 * case we inject the TLB from the Guest TLB into the shadow host TLB
2637 enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
2639 struct kvm_run *run,
2640 struct kvm_vcpu *vcpu)
2642 enum emulation_result er = EMULATE_DONE;
2643 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2644 unsigned long va = vcpu->arch.host_cp0_badvaddr;
2647 kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx, entryhi: %#lx\n",
2648 vcpu->arch.host_cp0_badvaddr, vcpu->arch.host_cp0_entryhi);
2651 * KVM would not have got the exception if this entry was valid in the
2652 * shadow host TLB. Check the Guest TLB, if the entry is not there then
2653 * send the guest an exception. The guest exc handler should then inject
2654 * an entry into the guest TLB.
2656 index = kvm_mips_guest_tlb_lookup(vcpu,
2658 (kvm_read_c0_guest_entryhi
2659 (vcpu->arch.cop0) & ASID_MASK));
2661 if (exccode == T_TLB_LD_MISS) {
2662 er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
2663 } else if (exccode == T_TLB_ST_MISS) {
2664 er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu);
2666 kvm_err("%s: invalid exc code: %d\n", __func__,
2671 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
2674 * Check if the entry is valid, if not then setup a TLB invalid
2675 * exception to the guest
2677 if (!TLB_IS_VALID(*tlb, va)) {
2678 if (exccode == T_TLB_LD_MISS) {
2679 er = kvm_mips_emulate_tlbinv_ld(cause, opc, run,
2681 } else if (exccode == T_TLB_ST_MISS) {
2682 er = kvm_mips_emulate_tlbinv_st(cause, opc, run,
2685 kvm_err("%s: invalid exc code: %d\n", __func__,
2690 kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
2691 tlb->tlb_hi, tlb->tlb_lo0, tlb->tlb_lo1);
2693 * OK we have a Guest TLB entry, now inject it into the
2696 if (kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb,
2698 kvm_err("%s: handling mapped seg tlb fault for %lx, index: %u, vcpu: %p, ASID: %#lx\n",
2699 __func__, va, index, vcpu,