1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
7 #include <linux/kernel.h>
8 #include <linux/ptrace.h>
9 #include <linux/stddef.h>
12 #include <asm/mipsregs.h>
13 #include <asm/r4kcache.h>
14 #include <asm/hazards.h>
17 * These definitions are correct for the 24K/34K/74K SPRAM sample
18 * implementation. The 4KS interpreted the tags differently...
20 #define SPRAM_TAG0_ENABLE 0x00000080
21 #define SPRAM_TAG0_PA_MASK 0xfffff000
22 #define SPRAM_TAG1_SIZE_MASK 0xfffff000
24 #define SPRAM_TAG_STRIDE 8
26 #define ERRCTL_SPRAM (1 << 28)
29 #define read_c0_errctl(x) read_c0_ecc(x)
30 #define write_c0_errctl(x) write_c0_ecc(x)
33 * Different semantics to the set_c0_* function built by __BUILD_SET_C0
35 static unsigned int bis_c0_errctl(unsigned int set)
38 res = read_c0_errctl();
39 write_c0_errctl(res | set);
43 static void ispram_store_tag(unsigned int offset, unsigned int data)
47 /* enable SPRAM tag access */
48 errctl = bis_c0_errctl(ERRCTL_SPRAM);
54 cache_op(Index_Store_Tag_I, CKSEG0|offset);
57 write_c0_errctl(errctl);
62 static unsigned int ispram_load_tag(unsigned int offset)
67 /* enable SPRAM tag access */
68 errctl = bis_c0_errctl(ERRCTL_SPRAM);
70 cache_op(Index_Load_Tag_I, CKSEG0 | offset);
72 data = read_c0_taglo();
74 write_c0_errctl(errctl);
80 static void dspram_store_tag(unsigned int offset, unsigned int data)
84 /* enable SPRAM tag access */
85 errctl = bis_c0_errctl(ERRCTL_SPRAM);
87 write_c0_dtaglo(data);
89 cache_op(Index_Store_Tag_D, CKSEG0 | offset);
91 write_c0_errctl(errctl);
96 static unsigned int dspram_load_tag(unsigned int offset)
101 errctl = bis_c0_errctl(ERRCTL_SPRAM);
103 cache_op(Index_Load_Tag_D, CKSEG0 | offset);
105 data = read_c0_dtaglo();
107 write_c0_errctl(errctl);
113 static void probe_spram(char *type,
115 unsigned int (*read)(unsigned int),
116 void (*write)(unsigned int, unsigned int))
118 unsigned int firstsize = 0, lastsize = 0;
119 unsigned int firstpa = 0, lastpa = 0, pa = 0;
120 unsigned int offset = 0;
121 unsigned int size, tag0, tag1;
122 unsigned int enabled;
126 * The limit is arbitrary but avoids the loop running away if
127 * the SPRAM tags are implemented differently
130 for (i = 0; i < 8; i++) {
132 tag1 = read(offset+SPRAM_TAG_STRIDE);
133 pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
134 type, i, tag0, tag1);
136 size = tag1 & SPRAM_TAG1_SIZE_MASK;
142 /* tags may repeat... */
143 if ((pa == firstpa && size == firstsize) ||
144 (pa == lastpa && size == lastsize))
148 /* Align base with size */
149 base = (base + size - 1) & ~(size-1);
151 /* reprogram the base address base address and enable */
152 tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
159 pa = tag0 & SPRAM_TAG0_PA_MASK;
160 enabled = tag0 & SPRAM_TAG0_ENABLE;
170 if (strcmp(type, "DSPRAM") == 0) {
171 unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
173 #define TDAT 0x5a5aa5a5
181 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
185 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
189 pr_info("%s%d: PA=%08x,Size=%08x%s\n",
190 type, i, pa, size, enabled ? ",enabled" : "");
191 offset += 2 * SPRAM_TAG_STRIDE;
194 void spram_config(void)
196 unsigned int config0;
198 switch (current_cpu_type()) {
207 case CPU_QEMU_GENERIC:
210 config0 = read_c0_config();
211 /* FIXME: addresses are Malta specific */
212 if (config0 & MIPS_CONF_ISP) {
213 probe_spram("ISPRAM", 0x1c000000,
214 &ispram_load_tag, &ispram_store_tag);
216 if (config0 & MIPS_CONF_DSP)
217 probe_spram("DSPRAM", 0x1c100000,
218 &dspram_load_tag, &dspram_store_tag);