1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
7 #include <linux/kernel.h>
8 #include <linux/ptrace.h>
9 #include <linux/stddef.h>
12 #include <asm/mipsregs.h>
13 #include <asm/r4kcache.h>
14 #include <asm/hazards.h>
15 #include <asm/spram.h>
18 * These definitions are correct for the 24K/34K/74K SPRAM sample
19 * implementation. The 4KS interpreted the tags differently...
21 #define SPRAM_TAG0_ENABLE 0x00000080
22 #define SPRAM_TAG0_PA_MASK 0xfffff000
23 #define SPRAM_TAG1_SIZE_MASK 0xfffff000
25 #define SPRAM_TAG_STRIDE 8
27 #define ERRCTL_SPRAM (1 << 28)
30 #define read_c0_errctl(x) read_c0_ecc(x)
31 #define write_c0_errctl(x) write_c0_ecc(x)
34 * Different semantics to the set_c0_* function built by __BUILD_SET_C0
36 static unsigned int bis_c0_errctl(unsigned int set)
39 res = read_c0_errctl();
40 write_c0_errctl(res | set);
44 static void ispram_store_tag(unsigned int offset, unsigned int data)
48 /* enable SPRAM tag access */
49 errctl = bis_c0_errctl(ERRCTL_SPRAM);
55 cache_op(Index_Store_Tag_I, CKSEG0|offset);
58 write_c0_errctl(errctl);
63 static unsigned int ispram_load_tag(unsigned int offset)
68 /* enable SPRAM tag access */
69 errctl = bis_c0_errctl(ERRCTL_SPRAM);
71 cache_op(Index_Load_Tag_I, CKSEG0 | offset);
73 data = read_c0_taglo();
75 write_c0_errctl(errctl);
81 static void dspram_store_tag(unsigned int offset, unsigned int data)
85 /* enable SPRAM tag access */
86 errctl = bis_c0_errctl(ERRCTL_SPRAM);
88 write_c0_dtaglo(data);
90 cache_op(Index_Store_Tag_D, CKSEG0 | offset);
92 write_c0_errctl(errctl);
97 static unsigned int dspram_load_tag(unsigned int offset)
102 errctl = bis_c0_errctl(ERRCTL_SPRAM);
104 cache_op(Index_Load_Tag_D, CKSEG0 | offset);
106 data = read_c0_dtaglo();
108 write_c0_errctl(errctl);
114 static void probe_spram(char *type,
116 unsigned int (*read)(unsigned int),
117 void (*write)(unsigned int, unsigned int))
119 unsigned int firstsize = 0, lastsize = 0;
120 unsigned int firstpa = 0, lastpa = 0, pa = 0;
121 unsigned int offset = 0;
122 unsigned int size, tag0, tag1;
123 unsigned int enabled;
127 * The limit is arbitrary but avoids the loop running away if
128 * the SPRAM tags are implemented differently
131 for (i = 0; i < 8; i++) {
133 tag1 = read(offset+SPRAM_TAG_STRIDE);
134 pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
135 type, i, tag0, tag1);
137 size = tag1 & SPRAM_TAG1_SIZE_MASK;
143 /* tags may repeat... */
144 if ((pa == firstpa && size == firstsize) ||
145 (pa == lastpa && size == lastsize))
149 /* Align base with size */
150 base = (base + size - 1) & ~(size-1);
152 /* reprogram the base address base address and enable */
153 tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
160 pa = tag0 & SPRAM_TAG0_PA_MASK;
161 enabled = tag0 & SPRAM_TAG0_ENABLE;
171 if (strcmp(type, "DSPRAM") == 0) {
172 unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
174 #define TDAT 0x5a5aa5a5
182 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
186 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
190 pr_info("%s%d: PA=%08x,Size=%08x%s\n",
191 type, i, pa, size, enabled ? ",enabled" : "");
192 offset += 2 * SPRAM_TAG_STRIDE;
195 void spram_config(void)
197 unsigned int config0;
199 switch (current_cpu_type()) {
208 case CPU_QEMU_GENERIC:
211 config0 = read_c0_config();
212 /* FIXME: addresses are Malta specific */
213 if (config0 & MIPS_CONF_ISP) {
214 probe_spram("ISPRAM", 0x1c000000,
215 &ispram_load_tag, &ispram_store_tag);
217 if (config0 & MIPS_CONF_DSP)
218 probe_spram("DSPRAM", 0x1c100000,
219 &dspram_load_tag, &dspram_store_tag);