2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
8 * SMP support for BMIPS
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/sched/hotplug.h>
14 #include <linux/sched/task_stack.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20 #include <linux/cpu.h>
21 #include <linux/cpumask.h>
22 #include <linux/reboot.h>
24 #include <linux/compiler.h>
25 #include <linux/linkage.h>
26 #include <linux/bug.h>
27 #include <linux/kernel.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/bootinfo.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mipsregs.h>
37 #include <asm/bmips.h>
38 #include <asm/traps.h>
39 #include <asm/barrier.h>
40 #include <asm/cpu-features.h>
42 static int __maybe_unused max_cpus = 1;
44 /* these may be configured by the platform code */
45 int bmips_smp_enabled = 1;
47 cpumask_t bmips_booted_mask;
48 unsigned long bmips_tp1_irqs = IE_IRQ1;
50 #define RESET_FROM_KSEG0 0x80080800
51 #define RESET_FROM_KSEG1 0xa0080800
53 static void bmips_set_reset_vec(int cpu, u32 val);
57 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
58 unsigned long bmips_smp_boot_sp;
59 unsigned long bmips_smp_boot_gp;
61 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
62 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
63 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
64 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
66 /* SW interrupts 0,1 are used for interprocessor signaling */
67 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
68 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
70 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
71 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
72 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
73 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
75 static void __init bmips_smp_setup(void)
77 int i, cpu = 1, boot_cpu = 0;
80 switch (current_cpu_type()) {
83 /* arbitration priority */
84 clear_c0_brcm_cmt_ctrl(0x30);
86 /* NBK and weak order flags */
87 set_c0_brcm_config_0(0x30000);
89 /* Find out if we are running on TP0 or TP1 */
90 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
93 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
95 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
96 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
103 change_c0_brcm_cmt_intr(0xf8018000,
104 (cpu_hw_intr << 27) | (0x03 << 15));
106 /* single core, 2 threads (2 pipelines) */
111 /* enable raceless SW interrupts */
112 set_c0_brcm_config(0x03 << 22);
114 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
115 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
117 /* N cores, 2 threads per core */
118 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
120 /* clear any pending SW interrupts */
121 for (i = 0; i < max_cpus; i++) {
122 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
123 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
131 if (!bmips_smp_enabled)
134 /* this can be overridden by the BSP */
135 if (!board_ebase_setup)
136 board_ebase_setup = &bmips_ebase_setup;
138 __cpu_number_map[boot_cpu] = 0;
139 __cpu_logical_map[0] = boot_cpu;
141 for (i = 0; i < max_cpus; i++) {
143 __cpu_number_map[i] = cpu;
144 __cpu_logical_map[cpu] = i;
147 set_cpu_possible(i, 1);
148 set_cpu_present(i, 1);
153 * IPI IRQ setup - runs on CPU0
155 static void bmips_prepare_cpus(unsigned int max_cpus)
157 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
159 switch (current_cpu_type()) {
162 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
165 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
171 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
172 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
173 panic("Can't request IPI0 interrupt");
174 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
175 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
176 panic("Can't request IPI1 interrupt");
180 * Tell the hardware to boot CPUx - runs on CPU0
182 static int bmips_boot_secondary(int cpu, struct task_struct *idle)
184 bmips_smp_boot_sp = __KSTK_TOS(idle);
185 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
189 * Initial boot sequence for secondary CPU:
190 * bmips_reset_nmi_vec @ a000_0000 ->
192 * plat_wired_tlb_setup (cached function call; optional) ->
193 * start_secondary (cached jump)
195 * Warm restart sequence:
196 * play_dead WAIT loop ->
197 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
198 * eret to play_dead ->
199 * bmips_secondary_reentry ->
203 pr_info("SMP: Booting CPU%d...\n", cpu);
205 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
206 /* kseg1 might not exist if this CPU enabled XKS01 */
207 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
209 switch (current_cpu_type()) {
212 bmips43xx_send_ipi_single(cpu, 0);
215 bmips5000_send_ipi_single(cpu, 0);
219 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
221 switch (current_cpu_type()) {
224 /* Reset slave TP1 if booting from TP0 */
225 if (cpu_logical_map(cpu) == 1)
226 set_c0_brcm_cmt_ctrl(0x01);
229 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
232 cpumask_set_cpu(cpu, &bmips_booted_mask);
239 * Early setup - runs on secondary CPU after cache probe
241 static void bmips_init_secondary(void)
245 switch (current_cpu_type()) {
248 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
251 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
252 cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3);
258 * Late setup - runs on secondary CPU before entering the idle loop
260 static void bmips_smp_finish(void)
262 pr_info("SMP: CPU%d is running\n", smp_processor_id());
264 /* make sure there won't be a timer interrupt for a little while */
265 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
268 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
273 * BMIPS5000 raceless IPIs
275 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
276 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
277 * IPI1 is used for SMP_CALL_FUNCTION
280 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
282 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
285 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
287 int action = irq - IPI0_IRQ;
289 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
294 generic_smp_call_function_interrupt();
299 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
304 for_each_cpu(i, mask)
305 bmips5000_send_ipi_single(i, action);
309 * BMIPS43xx racey IPIs
311 * We use one inbound SW IRQ for each CPU.
313 * A spinlock must be held in order to keep CPUx from accidentally clearing
314 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
315 * same spinlock is used to protect the action masks.
318 static DEFINE_SPINLOCK(ipi_lock);
319 static DEFINE_PER_CPU(int, ipi_action_mask);
321 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
325 spin_lock_irqsave(&ipi_lock, flags);
326 set_c0_cause(cpu ? C_SW1 : C_SW0);
327 per_cpu(ipi_action_mask, cpu) |= action;
329 spin_unlock_irqrestore(&ipi_lock, flags);
332 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
335 int action, cpu = irq - IPI0_IRQ;
337 spin_lock_irqsave(&ipi_lock, flags);
338 action = __this_cpu_read(ipi_action_mask);
339 per_cpu(ipi_action_mask, cpu) = 0;
340 clear_c0_cause(cpu ? C_SW1 : C_SW0);
341 spin_unlock_irqrestore(&ipi_lock, flags);
343 if (action & SMP_RESCHEDULE_YOURSELF)
345 if (action & SMP_CALL_FUNCTION)
346 generic_smp_call_function_interrupt();
351 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
356 for_each_cpu(i, mask)
357 bmips43xx_send_ipi_single(i, action);
360 #ifdef CONFIG_HOTPLUG_CPU
362 static int bmips_cpu_disable(void)
364 unsigned int cpu = smp_processor_id();
369 pr_info("SMP: CPU%d is offline\n", cpu);
371 set_cpu_online(cpu, false);
372 calculate_cpu_foreign_map();
374 clear_c0_status(IE_IRQ5);
376 local_flush_tlb_all();
377 local_flush_icache_range(0, ~0);
382 static void bmips_cpu_die(unsigned int cpu)
386 void __ref play_dead(void)
390 /* flush data cache */
391 _dma_cache_wback_inv(0, ~0);
394 * Wakeup is on SW0 or SW1; disable everything else
395 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
396 * IRQ handlers; this clears ST0_IE and returns immediately.
398 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
400 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
401 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
402 irq_disable_hazard();
405 * wait for SW interrupt from bmips_boot_secondary(), then jump
406 * back to start_secondary()
408 __asm__ __volatile__(
410 " j bmips_secondary_reentry\n"
414 #endif /* CONFIG_HOTPLUG_CPU */
416 const struct plat_smp_ops bmips43xx_smp_ops = {
417 .smp_setup = bmips_smp_setup,
418 .prepare_cpus = bmips_prepare_cpus,
419 .boot_secondary = bmips_boot_secondary,
420 .smp_finish = bmips_smp_finish,
421 .init_secondary = bmips_init_secondary,
422 .send_ipi_single = bmips43xx_send_ipi_single,
423 .send_ipi_mask = bmips43xx_send_ipi_mask,
424 #ifdef CONFIG_HOTPLUG_CPU
425 .cpu_disable = bmips_cpu_disable,
426 .cpu_die = bmips_cpu_die,
430 const struct plat_smp_ops bmips5000_smp_ops = {
431 .smp_setup = bmips_smp_setup,
432 .prepare_cpus = bmips_prepare_cpus,
433 .boot_secondary = bmips_boot_secondary,
434 .smp_finish = bmips_smp_finish,
435 .init_secondary = bmips_init_secondary,
436 .send_ipi_single = bmips5000_send_ipi_single,
437 .send_ipi_mask = bmips5000_send_ipi_mask,
438 #ifdef CONFIG_HOTPLUG_CPU
439 .cpu_disable = bmips_cpu_disable,
440 .cpu_die = bmips_cpu_die,
444 #endif /* CONFIG_SMP */
446 /***********************************************************************
447 * BMIPS vector relocation
448 * This is primarily used for SMP boot, but it is applicable to some
449 * UP BMIPS systems as well.
450 ***********************************************************************/
452 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
454 memcpy((void *)dst, start, end - start);
455 dma_cache_wback(dst, end - start);
456 local_flush_icache_range(dst, dst + (end - start));
457 instruction_hazard();
460 static inline void bmips_nmi_handler_setup(void)
462 bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
463 bmips_reset_nmi_vec_end);
464 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
465 bmips_smp_int_vec_end);
468 struct reset_vec_info {
473 static void bmips_set_reset_vec_remote(void *vinfo)
475 struct reset_vec_info *info = vinfo;
476 int shift = info->cpu & 0x01 ? 16 : 0;
477 u32 mask = ~(0xffff << shift), val = info->val >> 16;
480 if (smp_processor_id() > 0) {
481 smp_call_function_single(0, &bmips_set_reset_vec_remote,
484 if (info->cpu & 0x02) {
485 /* BMIPS5200 "should" use mask/shift, but it's buggy */
486 bmips_write_zscm_reg(0xa0, (val << 16) | val);
487 bmips_read_zscm_reg(0xa0);
489 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
496 static void bmips_set_reset_vec(int cpu, u32 val)
498 struct reset_vec_info info;
500 if (current_cpu_type() == CPU_BMIPS5000) {
501 /* this needs to run from CPU0 (which is always online) */
504 bmips_set_reset_vec_remote(&info);
506 void __iomem *cbr = BMIPS_GET_CBR();
509 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
511 if (current_cpu_type() != CPU_BMIPS4380)
513 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
517 back_to_back_c0_hazard();
520 void bmips_ebase_setup(void)
522 unsigned long new_ebase = ebase;
524 BUG_ON(ebase != CKSEG0);
526 switch (current_cpu_type()) {
529 * BMIPS4350 cannot relocate the normal vectors, but it
530 * can relocate the BEV=1 vectors. So CPU1 starts up at
531 * the relocated BEV=1, IV=0 general exception vector @
534 * set_uncached_handler() is used here because:
535 * - CPU1 will run this from uncached space
536 * - None of the cacheflush functions are set up yet
538 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
539 &bmips_smp_int_vec, 0x80);
545 * 0x8000_0000: reset/NMI (initially in kseg1)
546 * 0x8000_0400: normal vectors
548 new_ebase = 0x80000400;
549 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
553 * 0x8000_0000: reset/NMI (initially in kseg1)
554 * 0x8000_1000: normal vectors
556 new_ebase = 0x80001000;
557 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
558 write_c0_ebase(new_ebase);
564 board_nmi_handler_setup = &bmips_nmi_handler_setup;
568 asmlinkage void __weak plat_wired_tlb_setup(void)
571 * Called when starting/restarting a secondary CPU.
572 * Kernel stacks and other important data might only be accessible
573 * once the wired entries are present.
577 void bmips_cpu_setup(void)
579 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
580 u32 __maybe_unused cfg;
582 switch (current_cpu_type()) {
584 /* Set BIU to async mode */
585 set_c0_brcm_bus_pll(BIT(22));
588 /* put the BIU back in sync mode */
589 clear_c0_brcm_bus_pll(BIT(22));
591 /* clear BHTD to enable branch history table */
592 clear_c0_brcm_reset(BIT(16));
594 /* Flush and enable RAC */
595 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
596 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
597 __raw_readl(cbr + BMIPS_RAC_CONFIG);
599 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
600 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
601 __raw_readl(cbr + BMIPS_RAC_CONFIG);
603 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
604 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
605 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
609 /* CBG workaround for early BMIPS4380 CPUs */
610 switch (read_c0_prid()) {
615 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
616 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
617 __raw_readl(cbr + BMIPS_L2_CONFIG);
620 /* clear BHTD to enable branch history table */
621 clear_c0_brcm_config_0(BIT(21));
624 set_c0_brcm_config_0(BIT(23));
625 set_c0_brcm_cmt_ctrl(BIT(15));
629 /* enable RDHWR, BRDHWR */
630 set_c0_brcm_config(BIT(17) | BIT(21));
633 __asm__ __volatile__(
635 " li $8, 0x5a455048\n"
636 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
637 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
638 " li $9, 0x00008000\n"
640 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
643 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
648 set_c0_brcm_config(BIT(27));
650 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
651 __asm__ __volatile__(
652 " li $8, 0x5a455048\n"
653 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
655 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
658 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */