GNU Linux-libre 4.19.286-gnu1
[releases.git] / arch / mips / kernel / mips-cm.c
1 /*
2  * Copyright (C) 2013 Imagination Technologies
3  * Author: Paul Burton <paul.burton@mips.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation;  either version 2 of the  License, or (at your
8  * option) any later version.
9  */
10
11 #include <linux/errno.h>
12 #include <linux/percpu.h>
13 #include <linux/spinlock.h>
14
15 #include <asm/mips-cps.h>
16 #include <asm/mipsregs.h>
17
18 void __iomem *mips_gcr_base;
19 void __iomem *mips_cm_l2sync_base;
20 int mips_cm_is64;
21
22 static char *cm2_tr[8] = {
23         "mem",  "gcr",  "gic",  "mmio",
24         "0x04", "cpc", "0x06", "0x07"
25 };
26
27 /* CM3 Tag ECC transaction type */
28 static char *cm3_tr[16] = {
29         [0x0] = "ReqNoData",
30         [0x1] = "0x1",
31         [0x2] = "ReqWData",
32         [0x3] = "0x3",
33         [0x4] = "IReqNoResp",
34         [0x5] = "IReqWResp",
35         [0x6] = "IReqNoRespDat",
36         [0x7] = "IReqWRespDat",
37         [0x8] = "RespNoData",
38         [0x9] = "RespDataFol",
39         [0xa] = "RespWData",
40         [0xb] = "RespDataOnly",
41         [0xc] = "IRespNoData",
42         [0xd] = "IRespDataFol",
43         [0xe] = "IRespWData",
44         [0xf] = "IRespDataOnly"
45 };
46
47 static char *cm2_cmd[32] = {
48         [0x00] = "0x00",
49         [0x01] = "Legacy Write",
50         [0x02] = "Legacy Read",
51         [0x03] = "0x03",
52         [0x04] = "0x04",
53         [0x05] = "0x05",
54         [0x06] = "0x06",
55         [0x07] = "0x07",
56         [0x08] = "Coherent Read Own",
57         [0x09] = "Coherent Read Share",
58         [0x0a] = "Coherent Read Discard",
59         [0x0b] = "Coherent Ready Share Always",
60         [0x0c] = "Coherent Upgrade",
61         [0x0d] = "Coherent Writeback",
62         [0x0e] = "0x0e",
63         [0x0f] = "0x0f",
64         [0x10] = "Coherent Copyback",
65         [0x11] = "Coherent Copyback Invalidate",
66         [0x12] = "Coherent Invalidate",
67         [0x13] = "Coherent Write Invalidate",
68         [0x14] = "Coherent Completion Sync",
69         [0x15] = "0x15",
70         [0x16] = "0x16",
71         [0x17] = "0x17",
72         [0x18] = "0x18",
73         [0x19] = "0x19",
74         [0x1a] = "0x1a",
75         [0x1b] = "0x1b",
76         [0x1c] = "0x1c",
77         [0x1d] = "0x1d",
78         [0x1e] = "0x1e",
79         [0x1f] = "0x1f"
80 };
81
82 /* CM3 Tag ECC command type */
83 static char *cm3_cmd[16] = {
84         [0x0] = "Legacy Read",
85         [0x1] = "Legacy Write",
86         [0x2] = "Coherent Read Own",
87         [0x3] = "Coherent Read Share",
88         [0x4] = "Coherent Read Discard",
89         [0x5] = "Coherent Evicted",
90         [0x6] = "Coherent Upgrade",
91         [0x7] = "Coherent Upgrade for Store Conditional",
92         [0x8] = "Coherent Writeback",
93         [0x9] = "Coherent Write Invalidate",
94         [0xa] = "0xa",
95         [0xb] = "0xb",
96         [0xc] = "0xc",
97         [0xd] = "0xd",
98         [0xe] = "0xe",
99         [0xf] = "0xf"
100 };
101
102 /* CM3 Tag ECC command group */
103 static char *cm3_cmd_group[8] = {
104         [0x0] = "Normal",
105         [0x1] = "Registers",
106         [0x2] = "TLB",
107         [0x3] = "0x3",
108         [0x4] = "L1I",
109         [0x5] = "L1D",
110         [0x6] = "L3",
111         [0x7] = "L2"
112 };
113
114 static char *cm2_core[8] = {
115         "Invalid/OK",   "Invalid/Data",
116         "Shared/OK",    "Shared/Data",
117         "Modified/OK",  "Modified/Data",
118         "Exclusive/OK", "Exclusive/Data"
119 };
120
121 static char *cm2_causes[32] = {
122         "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
123         "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
124         "0x08", "0x09", "0x0a", "0x0b",
125         "0x0c", "0x0d", "0x0e", "0x0f",
126         "0x10", "INTVN_WR_ERR", "INTVN_RD_ERR", "0x13",
127         "0x14", "0x15", "0x16", "0x17",
128         "0x18", "0x19", "0x1a", "0x1b",
129         "0x1c", "0x1d", "0x1e", "0x1f"
130 };
131
132 static char *cm3_causes[32] = {
133         "0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
134         "MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
135         "CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
136         "0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
137         "0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
138         "0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
139 };
140
141 static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
142 static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
143
144 phys_addr_t __mips_cm_phys_base(void)
145 {
146         u32 config3 = read_c0_config3();
147         unsigned long cmgcr;
148
149         /* Check the CMGCRBase register is implemented */
150         if (!(config3 & MIPS_CONF3_CMGCR))
151                 return 0;
152
153         /* Read the address from CMGCRBase */
154         cmgcr = read_c0_cmgcrbase();
155         return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
156 }
157
158 phys_addr_t mips_cm_phys_base(void)
159         __attribute__((weak, alias("__mips_cm_phys_base")));
160
161 phys_addr_t __mips_cm_l2sync_phys_base(void)
162 {
163         u32 base_reg;
164
165         /*
166          * If the L2-only sync region is already enabled then leave it at it's
167          * current location.
168          */
169         base_reg = read_gcr_l2_only_sync_base();
170         if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
171                 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
172
173         /* Default to following the CM */
174         return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
175 }
176
177 phys_addr_t mips_cm_l2sync_phys_base(void)
178         __attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
179
180 static void mips_cm_probe_l2sync(void)
181 {
182         unsigned major_rev;
183         phys_addr_t addr;
184
185         /* L2-only sync was introduced with CM major revision 6 */
186         major_rev = FIELD_GET(CM_GCR_REV_MAJOR, read_gcr_rev());
187         if (major_rev < 6)
188                 return;
189
190         /* Find a location for the L2 sync region */
191         addr = mips_cm_l2sync_phys_base();
192         BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE) != addr);
193         if (!addr)
194                 return;
195
196         /* Set the region base address & enable it */
197         write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);
198
199         /* Map the region */
200         mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
201 }
202
203 int mips_cm_probe(void)
204 {
205         phys_addr_t addr;
206         u32 base_reg;
207         unsigned cpu;
208
209         /*
210          * No need to probe again if we have already been
211          * here before.
212          */
213         if (mips_gcr_base)
214                 return 0;
215
216         addr = mips_cm_phys_base();
217         BUG_ON((addr & CM_GCR_BASE_GCRBASE) != addr);
218         if (!addr)
219                 return -ENODEV;
220
221         mips_gcr_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
222         if (!mips_gcr_base)
223                 return -ENXIO;
224
225         /* sanity check that we're looking at a CM */
226         base_reg = read_gcr_base();
227         if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
228                 pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
229                        (unsigned long)addr);
230                 mips_gcr_base = NULL;
231                 return -ENODEV;
232         }
233
234         /* set default target to memory */
235         change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM);
236
237         /* disable CM regions */
238         write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR);
239         write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK);
240         write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR);
241         write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK);
242         write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR);
243         write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK);
244         write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR);
245         write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK);
246
247         /* probe for an L2-only sync region */
248         mips_cm_probe_l2sync();
249
250         /* determine register width for this CM */
251         mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
252
253         for_each_possible_cpu(cpu)
254                 spin_lock_init(&per_cpu(cm_core_lock, cpu));
255
256         return 0;
257 }
258
259 void mips_cm_lock_other(unsigned int cluster, unsigned int core,
260                         unsigned int vp, unsigned int block)
261 {
262         unsigned int curr_core, cm_rev;
263         u32 val;
264
265         cm_rev = mips_cm_revision();
266         preempt_disable();
267
268         if (cm_rev >= CM_REV_CM3) {
269                 val = FIELD_PREP(CM3_GCR_Cx_OTHER_CORE, core) |
270                       FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp);
271
272                 if (cm_rev >= CM_REV_CM3_5) {
273                         val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
274                         val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster);
275                         val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block);
276                 } else {
277                         WARN_ON(cluster != 0);
278                         WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
279                 }
280
281                 /*
282                  * We need to disable interrupts in SMP systems in order to
283                  * ensure that we don't interrupt the caller with code which
284                  * may modify the redirect register. We do so here in a
285                  * slightly obscure way by using a spin lock, since this has
286                  * the neat property of also catching any nested uses of
287                  * mips_cm_lock_other() leading to a deadlock or a nice warning
288                  * with lockdep enabled.
289                  */
290                 spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
291                                   *this_cpu_ptr(&cm_core_lock_flags));
292         } else {
293                 WARN_ON(cluster != 0);
294                 WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
295
296                 /*
297                  * We only have a GCR_CL_OTHER per core in systems with
298                  * CM 2.5 & older, so have to ensure other VP(E)s don't
299                  * race with us.
300                  */
301                 curr_core = cpu_core(&current_cpu_data);
302                 spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
303                                   per_cpu(cm_core_lock_flags, curr_core));
304
305                 val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core);
306         }
307
308         write_gcr_cl_other(val);
309
310         /*
311          * Ensure the core-other region reflects the appropriate core &
312          * VP before any accesses to it occur.
313          */
314         mb();
315 }
316
317 void mips_cm_unlock_other(void)
318 {
319         unsigned int curr_core;
320
321         if (mips_cm_revision() < CM_REV_CM3) {
322                 curr_core = cpu_core(&current_cpu_data);
323                 spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
324                                        per_cpu(cm_core_lock_flags, curr_core));
325         } else {
326                 spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
327                                        *this_cpu_ptr(&cm_core_lock_flags));
328         }
329
330         preempt_enable();
331 }
332
333 void mips_cm_error_report(void)
334 {
335         u64 cm_error, cm_addr, cm_other;
336         unsigned long revision;
337         int ocause, cause;
338         char buf[256];
339
340         if (!mips_cm_present())
341                 return;
342
343         revision = mips_cm_revision();
344         cm_error = read_gcr_error_cause();
345         cm_addr = read_gcr_error_addr();
346         cm_other = read_gcr_error_mult();
347
348         if (revision < CM_REV_CM3) { /* CM2 */
349                 cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
350                 ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
351
352                 if (!cause)
353                         return;
354
355                 if (cause < 16) {
356                         unsigned long cca_bits = (cm_error >> 15) & 7;
357                         unsigned long tr_bits = (cm_error >> 12) & 7;
358                         unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
359                         unsigned long stag_bits = (cm_error >> 3) & 15;
360                         unsigned long sport_bits = (cm_error >> 0) & 7;
361
362                         snprintf(buf, sizeof(buf),
363                                  "CCA=%lu TR=%s MCmd=%s STag=%lu "
364                                  "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
365                                  cm2_cmd[cmd_bits], stag_bits, sport_bits);
366                 } else {
367                         /* glob state & sresp together */
368                         unsigned long c3_bits = (cm_error >> 18) & 7;
369                         unsigned long c2_bits = (cm_error >> 15) & 7;
370                         unsigned long c1_bits = (cm_error >> 12) & 7;
371                         unsigned long c0_bits = (cm_error >> 9) & 7;
372                         unsigned long sc_bit = (cm_error >> 8) & 1;
373                         unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
374                         unsigned long sport_bits = (cm_error >> 0) & 7;
375
376                         snprintf(buf, sizeof(buf),
377                                  "C3=%s C2=%s C1=%s C0=%s SC=%s "
378                                  "MCmd=%s SPort=%lu\n",
379                                  cm2_core[c3_bits], cm2_core[c2_bits],
380                                  cm2_core[c1_bits], cm2_core[c0_bits],
381                                  sc_bit ? "True" : "False",
382                                  cm2_cmd[cmd_bits], sport_bits);
383                 }
384                         pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
385                                cm2_causes[cause], buf);
386                 pr_err("CM_ADDR =%08llx\n", cm_addr);
387                 pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
388         } else { /* CM3 */
389                 ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
390                 ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
391
392                 cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
393                 ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
394
395                 if (!cause)
396                         return;
397
398                 /* Used by cause == {1,2,3} */
399                 core_id_bits = (cm_error >> 22) & 0xf;
400                 vp_id_bits = (cm_error >> 18) & 0xf;
401                 cmd_bits = (cm_error >> 14) & 0xf;
402                 cmd_group_bits = (cm_error >> 11) & 0xf;
403                 cm3_cca_bits = (cm_error >> 8) & 7;
404                 mcp_bits = (cm_error >> 5) & 0xf;
405                 cm3_tr_bits = (cm_error >> 1) & 0xf;
406                 sched_bit = cm_error & 0x1;
407
408                 if (cause == 1 || cause == 3) { /* Tag ECC */
409                         unsigned long tag_ecc = (cm_error >> 57) & 0x1;
410                         unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
411                         unsigned long dword_bits = (cm_error >> 49) & 0xff;
412                         unsigned long data_way_bits = (cm_error >> 45) & 0xf;
413                         unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
414                         unsigned long bank_bit = (cm_error >> 28) & 0x1;
415                         snprintf(buf, sizeof(buf),
416                                  "%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
417                                  "Bank=%lu CoreID=%lu VPID=%lu Command=%s"
418                                  "Command Group=%s CCA=%lu MCP=%d"
419                                  "Transaction type=%s Scheduler=%lu\n",
420                                  tag_ecc ? "TAG" : "DATA",
421                                  tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
422                                  data_way_bits, bank_bit, dword_bits,
423                                  data_sets_bits,
424                                  core_id_bits, vp_id_bits,
425                                  cm3_cmd[cmd_bits],
426                                  cm3_cmd_group[cmd_group_bits],
427                                  cm3_cca_bits, 1 << mcp_bits,
428                                  cm3_tr[cm3_tr_bits], sched_bit);
429                 } else if (cause == 2) {
430                         unsigned long data_error_type = (cm_error >> 41) & 0xfff;
431                         unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
432                         unsigned long data_decode_group = (cm_error >> 34) & 0x7;
433                         unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;
434
435                         snprintf(buf, sizeof(buf),
436                                  "Decode Request Error: Type=%lu, Command=%lu"
437                                  "Command Group=%lu Destination ID=%lu"
438                                  "CoreID=%lu VPID=%lu Command=%s"
439                                  "Command Group=%s CCA=%lu MCP=%d"
440                                  "Transaction type=%s Scheduler=%lu\n",
441                                  data_error_type, data_decode_cmd,
442                                  data_decode_group, data_decode_destination_id,
443                                  core_id_bits, vp_id_bits,
444                                  cm3_cmd[cmd_bits],
445                                  cm3_cmd_group[cmd_group_bits],
446                                  cm3_cca_bits, 1 << mcp_bits,
447                                  cm3_tr[cm3_tr_bits], sched_bit);
448                 } else {
449                         buf[0] = 0;
450                 }
451
452                 pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
453                        cm3_causes[cause], buf);
454                 pr_err("CM_ADDR =%llx\n", cm_addr);
455                 pr_err("CM_OTHER=%llx %s\n", cm_other, cm3_causes[ocause]);
456         }
457
458         /* reprime cause register */
459         write_gcr_error_cause(cm_error);
460 }