2 * MIPS idle loop and WAIT instruction support.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/cpu.h>
15 #include <linux/export.h>
16 #include <linux/init.h>
17 #include <linux/irqflags.h>
18 #include <linux/printk.h>
19 #include <linux/sched.h>
21 #include <asm/cpu-info.h>
22 #include <asm/cpu-type.h>
24 #include <asm/mipsregs.h>
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
33 void (*cpu_wait)(void);
34 EXPORT_SYMBOL(cpu_wait);
36 static void __cpuidle r3081_wait(void)
38 unsigned long cfg = read_c0_conf();
39 write_c0_conf(cfg | R30XX_CONF_HALT);
43 static void __cpuidle r39xx_wait(void)
46 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
50 void __cpuidle r4k_wait(void)
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
63 void __cpuidle r4k_wait_irqoff(void)
75 * The RM7000 variant has to handle erratum 38. The workaround is to not
76 * have any pending stores when the WAIT instruction is executed.
78 static void __cpuidle rm7k_wait_irqoff(void)
87 " mtc0 $1, $12 # stalls until W stage \n"
89 " mtc0 $1, $12 # stalls until W stage \n"
95 * Au1 'wait' is only useful when the 32kHz counter is used as timer,
96 * since coreclock (and the cp0 counter) stops upon executing it. Only an
97 * interrupt can wake it, so they must be enabled before entering idle modes.
99 static void __cpuidle au1k_wait(void)
101 unsigned long c0status = read_c0_status() | 1; /* irqs on */
104 " .set arch=r4000 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
108 " mtc0 %1, $12 \n" /* wr c0status */
115 : : "r" (au1k_wait), "r" (c0status));
118 static int __initdata nowait;
120 static int __init wait_disable(char *s)
127 __setup("nowait", wait_disable);
129 void __init check_wait(void)
131 struct cpuinfo_mips *c = ¤t_cpu_data;
134 printk("Wait instruction disabled.\n");
139 * MIPSr6 specifies that masked interrupts should unblock an executing
140 * wait instruction, and thus that it is safe for us to use
141 * r4k_wait_irqoff. Yippee!
143 if (cpu_has_mips_r6) {
144 cpu_wait = r4k_wait_irqoff;
148 switch (current_cpu_type()) {
151 cpu_wait = r3081_wait;
154 cpu_wait = r39xx_wait;
157 /* case CPU_R4300: */
175 case CPU_CAVIUM_OCTEON:
176 case CPU_CAVIUM_OCTEON_PLUS:
177 case CPU_CAVIUM_OCTEON2:
178 case CPU_CAVIUM_OCTEON3:
186 if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
191 cpu_wait = r4k_wait_irqoff;
194 cpu_wait = rm7k_wait_irqoff;
200 * Incoming Fast Debug Channel (FDC) data during a wait
201 * instruction causes the wait never to resume, even if an
202 * interrupt is received. Avoid using wait at all if FDC data is
203 * likely to be received.
205 if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
216 case CPU_QEMU_GENERIC:
218 if (read_c0_config7() & MIPS_CONF7_WII)
219 cpu_wait = r4k_wait_irqoff;
224 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
225 cpu_wait = r4k_wait_irqoff;
229 cpu_wait = r4k_wait_irqoff;
232 cpu_wait = au1k_wait;
236 * WAIT on Rev1.0 has E1, E2, E3 and E16.
237 * WAIT on Rev2.0 and Rev3.0 has E16.
238 * Rev3.1 WAIT is nop, why bother
240 if ((c->processor_id & 0xff) <= 0x64)
244 * Another rev is incremeting c0_count at a reduced clock
245 * rate while in WAIT mode. So we basically have the choice
246 * between using the cp0 timer as clocksource or avoiding
247 * the WAIT instruction. Until more details are known,
248 * disable the use of WAIT for 20Kc entirely.
257 void arch_cpu_idle(void)
265 #ifdef CONFIG_CPU_IDLE
267 int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
268 struct cpuidle_driver *drv, int index)