GNU Linux-libre 4.19.286-gnu1
[releases.git] / arch / mips / kernel / idle.c
1 /*
2  * MIPS idle loop and WAIT instruction support.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/cpu.h>
15 #include <linux/export.h>
16 #include <linux/init.h>
17 #include <linux/irqflags.h>
18 #include <linux/printk.h>
19 #include <linux/sched.h>
20 #include <asm/cpu.h>
21 #include <asm/cpu-info.h>
22 #include <asm/cpu-type.h>
23 #include <asm/idle.h>
24 #include <asm/mipsregs.h>
25
26 /*
27  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28  * the implementation of the "wait" feature differs between CPU families. This
29  * points to the function that implements CPU specific wait.
30  * The wait instruction stops the pipeline and reduces the power consumption of
31  * the CPU very much.
32  */
33 void (*cpu_wait)(void);
34 EXPORT_SYMBOL(cpu_wait);
35
36 static void __cpuidle r3081_wait(void)
37 {
38         unsigned long cfg = read_c0_conf();
39         write_c0_conf(cfg | R30XX_CONF_HALT);
40         local_irq_enable();
41 }
42
43 static void __cpuidle r39xx_wait(void)
44 {
45         if (!need_resched())
46                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
47         local_irq_enable();
48 }
49
50 void __cpuidle r4k_wait(void)
51 {
52         local_irq_enable();
53         __r4k_wait();
54 }
55
56 /*
57  * This variant is preferable as it allows testing need_resched and going to
58  * sleep depending on the outcome atomically.  Unfortunately the "It is
59  * implementation-dependent whether the pipeline restarts when a non-enabled
60  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61  * using this version a gamble.
62  */
63 void __cpuidle r4k_wait_irqoff(void)
64 {
65         if (!need_resched())
66                 __asm__(
67                 "       .set    push            \n"
68                 "       .set    arch=r4000      \n"
69                 "       wait                    \n"
70                 "       .set    pop             \n");
71         local_irq_enable();
72 }
73
74 /*
75  * The RM7000 variant has to handle erratum 38.  The workaround is to not
76  * have any pending stores when the WAIT instruction is executed.
77  */
78 static void __cpuidle rm7k_wait_irqoff(void)
79 {
80         if (!need_resched())
81                 __asm__(
82                 "       .set    push                                    \n"
83                 "       .set    arch=r4000                              \n"
84                 "       .set    noat                                    \n"
85                 "       mfc0    $1, $12                                 \n"
86                 "       sync                                            \n"
87                 "       mtc0    $1, $12         # stalls until W stage  \n"
88                 "       wait                                            \n"
89                 "       mtc0    $1, $12         # stalls until W stage  \n"
90                 "       .set    pop                                     \n");
91         local_irq_enable();
92 }
93
94 /*
95  * Au1 'wait' is only useful when the 32kHz counter is used as timer,
96  * since coreclock (and the cp0 counter) stops upon executing it. Only an
97  * interrupt can wake it, so they must be enabled before entering idle modes.
98  */
99 static void __cpuidle au1k_wait(void)
100 {
101         unsigned long c0status = read_c0_status() | 1;  /* irqs on */
102
103         __asm__(
104         "       .set    arch=r4000                      \n"
105         "       cache   0x14, 0(%0)             \n"
106         "       cache   0x14, 32(%0)            \n"
107         "       sync                            \n"
108         "       mtc0    %1, $12                 \n" /* wr c0status */
109         "       wait                            \n"
110         "       nop                             \n"
111         "       nop                             \n"
112         "       nop                             \n"
113         "       nop                             \n"
114         "       .set    mips0                   \n"
115         : : "r" (au1k_wait), "r" (c0status));
116 }
117
118 static int __initdata nowait;
119
120 static int __init wait_disable(char *s)
121 {
122         nowait = 1;
123
124         return 1;
125 }
126
127 __setup("nowait", wait_disable);
128
129 void __init check_wait(void)
130 {
131         struct cpuinfo_mips *c = &current_cpu_data;
132
133         if (nowait) {
134                 printk("Wait instruction disabled.\n");
135                 return;
136         }
137
138         /*
139          * MIPSr6 specifies that masked interrupts should unblock an executing
140          * wait instruction, and thus that it is safe for us to use
141          * r4k_wait_irqoff. Yippee!
142          */
143         if (cpu_has_mips_r6) {
144                 cpu_wait = r4k_wait_irqoff;
145                 return;
146         }
147
148         switch (current_cpu_type()) {
149         case CPU_R3081:
150         case CPU_R3081E:
151                 cpu_wait = r3081_wait;
152                 break;
153         case CPU_TX3927:
154                 cpu_wait = r39xx_wait;
155                 break;
156         case CPU_R4200:
157 /*      case CPU_R4300: */
158         case CPU_R4600:
159         case CPU_R4640:
160         case CPU_R4650:
161         case CPU_R4700:
162         case CPU_R5000:
163         case CPU_R5500:
164         case CPU_NEVADA:
165         case CPU_4KC:
166         case CPU_4KEC:
167         case CPU_4KSC:
168         case CPU_5KC:
169         case CPU_5KE:
170         case CPU_25KF:
171         case CPU_PR4450:
172         case CPU_BMIPS3300:
173         case CPU_BMIPS4350:
174         case CPU_BMIPS4380:
175         case CPU_CAVIUM_OCTEON:
176         case CPU_CAVIUM_OCTEON_PLUS:
177         case CPU_CAVIUM_OCTEON2:
178         case CPU_CAVIUM_OCTEON3:
179         case CPU_JZRISC:
180         case CPU_LOONGSON1:
181         case CPU_XLR:
182         case CPU_XLP:
183                 cpu_wait = r4k_wait;
184                 break;
185         case CPU_LOONGSON3:
186                 if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
187                         cpu_wait = r4k_wait;
188                 break;
189
190         case CPU_BMIPS5000:
191                 cpu_wait = r4k_wait_irqoff;
192                 break;
193         case CPU_RM7000:
194                 cpu_wait = rm7k_wait_irqoff;
195                 break;
196
197         case CPU_PROAPTIV:
198         case CPU_P5600:
199                 /*
200                  * Incoming Fast Debug Channel (FDC) data during a wait
201                  * instruction causes the wait never to resume, even if an
202                  * interrupt is received. Avoid using wait at all if FDC data is
203                  * likely to be received.
204                  */
205                 if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
206                         break;
207                 /* fall through */
208         case CPU_M14KC:
209         case CPU_M14KEC:
210         case CPU_24K:
211         case CPU_34K:
212         case CPU_1004K:
213         case CPU_1074K:
214         case CPU_INTERAPTIV:
215         case CPU_M5150:
216         case CPU_QEMU_GENERIC:
217                 cpu_wait = r4k_wait;
218                 if (read_c0_config7() & MIPS_CONF7_WII)
219                         cpu_wait = r4k_wait_irqoff;
220                 break;
221
222         case CPU_74K:
223                 cpu_wait = r4k_wait;
224                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
225                         cpu_wait = r4k_wait_irqoff;
226                 break;
227
228         case CPU_TX49XX:
229                 cpu_wait = r4k_wait_irqoff;
230                 break;
231         case CPU_ALCHEMY:
232                 cpu_wait = au1k_wait;
233                 break;
234         case CPU_20KC:
235                 /*
236                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
237                  * WAIT on Rev2.0 and Rev3.0 has E16.
238                  * Rev3.1 WAIT is nop, why bother
239                  */
240                 if ((c->processor_id & 0xff) <= 0x64)
241                         break;
242
243                 /*
244                  * Another rev is incremeting c0_count at a reduced clock
245                  * rate while in WAIT mode.  So we basically have the choice
246                  * between using the cp0 timer as clocksource or avoiding
247                  * the WAIT instruction.  Until more details are known,
248                  * disable the use of WAIT for 20Kc entirely.
249                    cpu_wait = r4k_wait;
250                  */
251                 break;
252         default:
253                 break;
254         }
255 }
256
257 void arch_cpu_idle(void)
258 {
259         if (cpu_wait)
260                 cpu_wait();
261         else
262                 local_irq_enable();
263 }
264
265 #ifdef CONFIG_CPU_IDLE
266
267 int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
268                             struct cpuidle_driver *drv, int index)
269 {
270         arch_cpu_idle();
271         return index;
272 }
273
274 #endif