1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Format of an instruction in memory.
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * Copyright (C) 1996, 2000 by Ralf Baechle
10 * Copyright (C) 2006 by Thiemo Seufer
11 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
12 * Copyright (C) 2014 Imagination Technologies Ltd.
14 #ifndef _UAPI_ASM_INST_H
15 #define _UAPI_ASM_INST_H
17 #include <asm/bitfield.h>
20 * Major opcodes; before MIPS IV cop1x was called cop3.
23 spec_op, bcond_op, j_op, jal_op,
24 beq_op, bne_op, blez_op, bgtz_op,
25 addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op,
26 andi_op, ori_op, xori_op, lui_op,
27 cop0_op, cop1_op, cop2_op, cop1x_op,
28 beql_op, bnel_op, blezl_op, bgtzl_op,
29 daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op,
30 spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
31 lb_op, lh_op, lwl_op, lw_op,
32 lbu_op, lhu_op, lwr_op, lwu_op,
33 sb_op, sh_op, swl_op, sw_op,
34 sdl_op, sdr_op, swr_op, cache_op,
35 ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
36 lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op,
37 sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
38 scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op
42 * func field of spec opcode.
45 sll_op, movc_op, srl_op, sra_op,
46 sllv_op, pmon_op, srlv_op, srav_op,
47 jr_op, jalr_op, movz_op, movn_op,
48 syscall_op, break_op, spim_op, sync_op,
49 mfhi_op, mthi_op, mflo_op, mtlo_op,
50 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
51 mult_op, multu_op, div_op, divu_op,
52 dmult_op, dmultu_op, ddiv_op, ddivu_op,
53 add_op, addu_op, sub_op, subu_op,
54 and_op, or_op, xor_op, nor_op,
55 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
56 dadd_op, daddu_op, dsub_op, dsubu_op,
57 tge_op, tgeu_op, tlt_op, tltu_op,
58 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
59 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
60 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
64 * func field of spec2 opcode.
67 madd_op, maddu_op, mul_op, spec2_3_unused_op,
68 msub_op, msubu_op, /* more unused ops */
69 clz_op = 0x20, clo_op,
70 dclz_op = 0x24, dclo_op,
75 * func field of spec3 opcode.
78 ext_op, dextm_op, dextu_op, dext_op,
79 ins_op, dinsm_op, dinsu_op, dins_op,
80 yield_op = 0x09, lx_op = 0x0a,
81 lwle_op = 0x19, lwre_op = 0x1a,
82 cachee_op = 0x1b, sbe_op = 0x1c,
83 she_op = 0x1d, sce_op = 0x1e,
84 swe_op = 0x1f, bshfl_op = 0x20,
85 swle_op = 0x21, swre_op = 0x22,
86 prefe_op = 0x23, dbshfl_op = 0x24,
87 cache6_op = 0x25, sc6_op = 0x26,
88 scd6_op = 0x27, lbue_op = 0x28,
89 lhue_op = 0x29, lbe_op = 0x2c,
90 lhe_op = 0x2d, lle_op = 0x2e,
91 lwe_op = 0x2f, pref6_op = 0x35,
92 ll6_op = 0x36, lld6_op = 0x37,
97 * Bits 10-6 minor opcode for r6 spec mult/div encodings
105 multu_multu_op = 0x0,
120 dmult_dmult_op = 0x0,
125 dmultu_dmultu_op = 0x0,
126 dmultu_dmulu_op = 0x2,
127 dmultu_dmuhu_op = 0x3,
135 ddivu_ddivu_op = 0x0,
136 ddivu_ddivu6_op = 0x2,
137 ddivu_dmodu_op = 0x3,
141 * rt field of bcond opcodes.
144 bltz_op, bgez_op, bltzl_op, bgezl_op,
145 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
146 tgei_op, tgeiu_op, tlti_op, tltiu_op,
147 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
148 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
149 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
150 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
151 bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
155 * rs field of cop opcodes.
158 mfc_op = 0x00, dmfc_op = 0x01,
159 cfc_op = 0x02, mfhc0_op = 0x02,
160 mfhc_op = 0x03, mtc_op = 0x04,
161 dmtc_op = 0x05, ctc_op = 0x06,
162 mthc0_op = 0x06, mthc_op = 0x07,
163 bc_op = 0x08, bc1eqz_op = 0x09,
164 mfmc0_op = 0x0b, bc1nez_op = 0x0d,
165 wrpgpr_op = 0x0e, cop_op = 0x10,
170 * rt field of cop.bc_op opcodes
173 bcf_op, bct_op, bcfl_op, bctl_op
177 * func field of cop0 coi opcodes.
180 tlbr_op = 0x01, tlbwi_op = 0x02,
181 tlbwr_op = 0x06, tlbp_op = 0x08,
182 rfe_op = 0x10, eret_op = 0x18,
183 wait_op = 0x20, hypcall_op = 0x28
187 * func field of cop0 com opcodes.
190 tlbr1_op = 0x01, tlbw_op = 0x02,
191 tlbp1_op = 0x08, dctr_op = 0x09,
196 * fmt field of cop1 opcodes.
199 s_fmt, d_fmt, e_fmt, q_fmt,
204 * func field of cop1 instructions using d, s or w format.
207 fadd_op = 0x00, fsub_op = 0x01,
208 fmul_op = 0x02, fdiv_op = 0x03,
209 fsqrt_op = 0x04, fabs_op = 0x05,
210 fmov_op = 0x06, fneg_op = 0x07,
211 froundl_op = 0x08, ftruncl_op = 0x09,
212 fceill_op = 0x0a, ffloorl_op = 0x0b,
213 fround_op = 0x0c, ftrunc_op = 0x0d,
214 fceil_op = 0x0e, ffloor_op = 0x0f,
216 fmovc_op = 0x11, fmovz_op = 0x12,
217 fmovn_op = 0x13, fseleqz_op = 0x14,
218 frecip_op = 0x15, frsqrt_op = 0x16,
219 fselnez_op = 0x17, fmaddf_op = 0x18,
220 fmsubf_op = 0x19, frint_op = 0x1a,
221 fclass_op = 0x1b, fmin_op = 0x1c,
222 fmina_op = 0x1d, fmax_op = 0x1e,
223 fmaxa_op = 0x1f, fcvts_op = 0x20,
224 fcvtd_op = 0x21, fcvte_op = 0x22,
225 fcvtw_op = 0x24, fcvtl_op = 0x25,
230 * func field of cop1x opcodes (MIPS IV).
233 lwxc1_op = 0x00, ldxc1_op = 0x01,
234 swxc1_op = 0x08, sdxc1_op = 0x09,
235 pfetch_op = 0x0f, madd_s_op = 0x20,
236 madd_d_op = 0x21, madd_e_op = 0x22,
237 msub_s_op = 0x28, msub_d_op = 0x29,
238 msub_e_op = 0x2a, nmadd_s_op = 0x30,
239 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
240 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
245 * func field for mad opcodes (MIPS IV).
248 madd_fp_op = 0x08, msub_fp_op = 0x0a,
249 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
253 * func field for page table walker (Loongson-3).
263 * func field for special3 lx opcodes (Cavium Octeon).
308 * func field for MSA MI10 format.
316 * MSA 2 bit format fields.
326 * (microMIPS) Major opcodes.
329 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
330 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
331 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
332 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
333 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
334 mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op,
335 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
336 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
337 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
338 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
339 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
340 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
341 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
342 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
343 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
344 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
348 * (microMIPS) POOL32I minor opcodes.
350 enum mm_32i_minor_op {
351 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
352 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
353 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
354 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
355 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
356 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
357 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
358 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
359 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
363 * (microMIPS) POOL32A minor opcodes.
365 enum mm_32a_minor_op {
368 mm_sllv32_op = 0x010,
370 mm_pool32axf_op = 0x03c,
372 mm_srlv32_op = 0x050,
376 mm_addu32_op = 0x150,
377 mm_subu32_op = 0x1d0,
388 * (microMIPS) POOL32B functions.
407 * (microMIPS) POOL32C functions.
418 * (microMIPS) POOL32AXF minor opcodes.
420 enum mm_32axf_minor_op {
424 mm_mfhi32_op = 0x035,
427 mm_mflo32_op = 0x075,
428 mm_jalrhb_op = 0x07c,
430 mm_mthi32_op = 0x0b5,
432 mm_mtlo32_op = 0x0f5,
435 mm_jalrshb_op = 0x17c,
437 mm_syscall_op = 0x22d,
444 * (microMIPS) POOL32F minor opcodes.
446 enum mm_32f_minor_op {
468 * (microMIPS) POOL32F secondary minor opcodes.
470 enum mm_32f_10_minor_op {
480 mm_lwxc1_func = 0x048,
481 mm_swxc1_func = 0x088,
482 mm_ldxc1_func = 0x0c8,
483 mm_sdxc1_func = 0x108,
487 * (microMIPS) POOL32F secondary minor opcodes.
489 enum mm_32f_40_minor_op {
495 * (microMIPS) POOL32F secondary minor opcodes.
497 enum mm_32f_60_minor_op {
505 * (microMIPS) POOL32F secondary minor opcodes.
507 enum mm_32f_70_minor_op {
513 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
515 enum mm_32f_73_minor_op {
520 mm_ffloorl_op = 0x0c,
525 mm_ffloorw_op = 0x2c,
537 mm_ftruncl_op = 0x8c,
541 mm_ftruncw_op = 0xac,
544 mm_froundl_op = 0xcc,
547 mm_froundw_op = 0xec,
552 * (microMIPS) POOL32S minor opcodes.
554 enum mm_32s_minor_op {
555 mm_32s_elm_op = 0x16,
559 * (microMIPS) POOL16C minor opcodes.
561 enum mm_16c_minor_op {
567 mm_jalrs16_op = 0x0f,
568 mm_jraddiusp_op = 0x18,
572 * (microMIPS) POOL16D minor opcodes.
574 enum mm_16d_minor_op {
583 MIPS16e_jal_op = 003,
589 MIPS16e_lwsp_op = 022,
591 MIPS16e_lbu_op = 024,
592 MIPS16e_lhu_op = 025,
593 MIPS16e_lwpc_op = 026,
594 MIPS16e_lwu_op = 027,
597 MIPS16e_swsp_op = 032,
600 MIPS16e_extend_op = 036,
601 MIPS16e_i64_op = 037,
604 enum MIPS16e_i64_func {
612 enum MIPS16e_rr_func {
616 enum MIPS6e_i8_func {
617 MIPS16e_swrasp_func = 02,
621 * (microMIPS) NOP instruction.
623 #define MM_NOP16 0x0c00
626 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
627 __BITFIELD_FIELD(unsigned int target : 26,
631 struct i_format { /* signed immediate format */
632 __BITFIELD_FIELD(unsigned int opcode : 6,
633 __BITFIELD_FIELD(unsigned int rs : 5,
634 __BITFIELD_FIELD(unsigned int rt : 5,
635 __BITFIELD_FIELD(signed int simmediate : 16,
639 struct u_format { /* unsigned immediate format */
640 __BITFIELD_FIELD(unsigned int opcode : 6,
641 __BITFIELD_FIELD(unsigned int rs : 5,
642 __BITFIELD_FIELD(unsigned int rt : 5,
643 __BITFIELD_FIELD(unsigned int uimmediate : 16,
647 struct c_format { /* Cache (>= R6000) format */
648 __BITFIELD_FIELD(unsigned int opcode : 6,
649 __BITFIELD_FIELD(unsigned int rs : 5,
650 __BITFIELD_FIELD(unsigned int c_op : 3,
651 __BITFIELD_FIELD(unsigned int cache : 2,
652 __BITFIELD_FIELD(unsigned int simmediate : 16,
656 struct r_format { /* Register format */
657 __BITFIELD_FIELD(unsigned int opcode : 6,
658 __BITFIELD_FIELD(unsigned int rs : 5,
659 __BITFIELD_FIELD(unsigned int rt : 5,
660 __BITFIELD_FIELD(unsigned int rd : 5,
661 __BITFIELD_FIELD(unsigned int re : 5,
662 __BITFIELD_FIELD(unsigned int func : 6,
666 struct c0r_format { /* C0 register format */
667 __BITFIELD_FIELD(unsigned int opcode : 6,
668 __BITFIELD_FIELD(unsigned int rs : 5,
669 __BITFIELD_FIELD(unsigned int rt : 5,
670 __BITFIELD_FIELD(unsigned int rd : 5,
671 __BITFIELD_FIELD(unsigned int z: 8,
672 __BITFIELD_FIELD(unsigned int sel : 3,
676 struct mfmc0_format { /* MFMC0 register format */
677 __BITFIELD_FIELD(unsigned int opcode : 6,
678 __BITFIELD_FIELD(unsigned int rs : 5,
679 __BITFIELD_FIELD(unsigned int rt : 5,
680 __BITFIELD_FIELD(unsigned int rd : 5,
681 __BITFIELD_FIELD(unsigned int re : 5,
682 __BITFIELD_FIELD(unsigned int sc : 1,
683 __BITFIELD_FIELD(unsigned int : 2,
684 __BITFIELD_FIELD(unsigned int sel : 3,
688 struct co_format { /* C0 CO format */
689 __BITFIELD_FIELD(unsigned int opcode : 6,
690 __BITFIELD_FIELD(unsigned int co : 1,
691 __BITFIELD_FIELD(unsigned int code : 19,
692 __BITFIELD_FIELD(unsigned int func : 6,
696 struct p_format { /* Performance counter format (R10000) */
697 __BITFIELD_FIELD(unsigned int opcode : 6,
698 __BITFIELD_FIELD(unsigned int rs : 5,
699 __BITFIELD_FIELD(unsigned int rt : 5,
700 __BITFIELD_FIELD(unsigned int rd : 5,
701 __BITFIELD_FIELD(unsigned int re : 5,
702 __BITFIELD_FIELD(unsigned int func : 6,
706 struct f_format { /* FPU register format */
707 __BITFIELD_FIELD(unsigned int opcode : 6,
708 __BITFIELD_FIELD(unsigned int : 1,
709 __BITFIELD_FIELD(unsigned int fmt : 4,
710 __BITFIELD_FIELD(unsigned int rt : 5,
711 __BITFIELD_FIELD(unsigned int rd : 5,
712 __BITFIELD_FIELD(unsigned int re : 5,
713 __BITFIELD_FIELD(unsigned int func : 6,
717 struct ma_format { /* FPU multiply and add format (MIPS IV) */
718 __BITFIELD_FIELD(unsigned int opcode : 6,
719 __BITFIELD_FIELD(unsigned int fr : 5,
720 __BITFIELD_FIELD(unsigned int ft : 5,
721 __BITFIELD_FIELD(unsigned int fs : 5,
722 __BITFIELD_FIELD(unsigned int fd : 5,
723 __BITFIELD_FIELD(unsigned int func : 4,
724 __BITFIELD_FIELD(unsigned int fmt : 2,
728 struct b_format { /* BREAK and SYSCALL */
729 __BITFIELD_FIELD(unsigned int opcode : 6,
730 __BITFIELD_FIELD(unsigned int code : 20,
731 __BITFIELD_FIELD(unsigned int func : 6,
735 struct ps_format { /* MIPS-3D / paired single format */
736 __BITFIELD_FIELD(unsigned int opcode : 6,
737 __BITFIELD_FIELD(unsigned int rs : 5,
738 __BITFIELD_FIELD(unsigned int ft : 5,
739 __BITFIELD_FIELD(unsigned int fs : 5,
740 __BITFIELD_FIELD(unsigned int fd : 5,
741 __BITFIELD_FIELD(unsigned int func : 6,
745 struct v_format { /* MDMX vector format */
746 __BITFIELD_FIELD(unsigned int opcode : 6,
747 __BITFIELD_FIELD(unsigned int sel : 4,
748 __BITFIELD_FIELD(unsigned int fmt : 1,
749 __BITFIELD_FIELD(unsigned int vt : 5,
750 __BITFIELD_FIELD(unsigned int vs : 5,
751 __BITFIELD_FIELD(unsigned int vd : 5,
752 __BITFIELD_FIELD(unsigned int func : 6,
756 struct msa_mi10_format { /* MSA MI10 */
757 __BITFIELD_FIELD(unsigned int opcode : 6,
758 __BITFIELD_FIELD(signed int s10 : 10,
759 __BITFIELD_FIELD(unsigned int rs : 5,
760 __BITFIELD_FIELD(unsigned int wd : 5,
761 __BITFIELD_FIELD(unsigned int func : 4,
762 __BITFIELD_FIELD(unsigned int df : 2,
766 struct dsp_format { /* SPEC3 DSP format instructions */
767 __BITFIELD_FIELD(unsigned int opcode : 6,
768 __BITFIELD_FIELD(unsigned int base : 5,
769 __BITFIELD_FIELD(unsigned int index : 5,
770 __BITFIELD_FIELD(unsigned int rd : 5,
771 __BITFIELD_FIELD(unsigned int op : 5,
772 __BITFIELD_FIELD(unsigned int func : 6,
776 struct spec3_format { /* SPEC3 */
777 __BITFIELD_FIELD(unsigned int opcode:6,
778 __BITFIELD_FIELD(unsigned int rs:5,
779 __BITFIELD_FIELD(unsigned int rt:5,
780 __BITFIELD_FIELD(signed int simmediate:9,
781 __BITFIELD_FIELD(unsigned int func:7,
786 * microMIPS instruction formats (32-bit length)
789 * Parenthesis denote whether the format is a microMIPS instruction or
790 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
792 struct fb_format { /* FPU branch format (MIPS32) */
793 __BITFIELD_FIELD(unsigned int opcode : 6,
794 __BITFIELD_FIELD(unsigned int bc : 5,
795 __BITFIELD_FIELD(unsigned int cc : 3,
796 __BITFIELD_FIELD(unsigned int flag : 2,
797 __BITFIELD_FIELD(signed int simmediate : 16,
801 struct fp0_format { /* FPU multiply and add format (MIPS32) */
802 __BITFIELD_FIELD(unsigned int opcode : 6,
803 __BITFIELD_FIELD(unsigned int fmt : 5,
804 __BITFIELD_FIELD(unsigned int ft : 5,
805 __BITFIELD_FIELD(unsigned int fs : 5,
806 __BITFIELD_FIELD(unsigned int fd : 5,
807 __BITFIELD_FIELD(unsigned int func : 6,
811 struct mm_fp0_format { /* FPU multiply and add format (microMIPS) */
812 __BITFIELD_FIELD(unsigned int opcode : 6,
813 __BITFIELD_FIELD(unsigned int ft : 5,
814 __BITFIELD_FIELD(unsigned int fs : 5,
815 __BITFIELD_FIELD(unsigned int fd : 5,
816 __BITFIELD_FIELD(unsigned int fmt : 3,
817 __BITFIELD_FIELD(unsigned int op : 2,
818 __BITFIELD_FIELD(unsigned int func : 6,
822 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
823 __BITFIELD_FIELD(unsigned int opcode : 6,
824 __BITFIELD_FIELD(unsigned int op : 5,
825 __BITFIELD_FIELD(unsigned int rt : 5,
826 __BITFIELD_FIELD(unsigned int fs : 5,
827 __BITFIELD_FIELD(unsigned int fd : 5,
828 __BITFIELD_FIELD(unsigned int func : 6,
832 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
833 __BITFIELD_FIELD(unsigned int opcode : 6,
834 __BITFIELD_FIELD(unsigned int rt : 5,
835 __BITFIELD_FIELD(unsigned int fs : 5,
836 __BITFIELD_FIELD(unsigned int fmt : 2,
837 __BITFIELD_FIELD(unsigned int op : 8,
838 __BITFIELD_FIELD(unsigned int func : 6,
842 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
843 __BITFIELD_FIELD(unsigned int opcode : 6,
844 __BITFIELD_FIELD(unsigned int fd : 5,
845 __BITFIELD_FIELD(unsigned int fs : 5,
846 __BITFIELD_FIELD(unsigned int cc : 3,
847 __BITFIELD_FIELD(unsigned int zero : 2,
848 __BITFIELD_FIELD(unsigned int fmt : 2,
849 __BITFIELD_FIELD(unsigned int op : 3,
850 __BITFIELD_FIELD(unsigned int func : 6,
854 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
855 __BITFIELD_FIELD(unsigned int opcode : 6,
856 __BITFIELD_FIELD(unsigned int rt : 5,
857 __BITFIELD_FIELD(unsigned int fs : 5,
858 __BITFIELD_FIELD(unsigned int fmt : 3,
859 __BITFIELD_FIELD(unsigned int op : 7,
860 __BITFIELD_FIELD(unsigned int func : 6,
864 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
865 __BITFIELD_FIELD(unsigned int opcode : 6,
866 __BITFIELD_FIELD(unsigned int rt : 5,
867 __BITFIELD_FIELD(unsigned int fs : 5,
868 __BITFIELD_FIELD(unsigned int cc : 3,
869 __BITFIELD_FIELD(unsigned int fmt : 3,
870 __BITFIELD_FIELD(unsigned int cond : 4,
871 __BITFIELD_FIELD(unsigned int func : 6,
875 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
876 __BITFIELD_FIELD(unsigned int opcode : 6,
877 __BITFIELD_FIELD(unsigned int index : 5,
878 __BITFIELD_FIELD(unsigned int base : 5,
879 __BITFIELD_FIELD(unsigned int fd : 5,
880 __BITFIELD_FIELD(unsigned int op : 5,
881 __BITFIELD_FIELD(unsigned int func : 6,
885 struct fp6_format { /* FPU madd and msub format (MIPS IV) */
886 __BITFIELD_FIELD(unsigned int opcode : 6,
887 __BITFIELD_FIELD(unsigned int fr : 5,
888 __BITFIELD_FIELD(unsigned int ft : 5,
889 __BITFIELD_FIELD(unsigned int fs : 5,
890 __BITFIELD_FIELD(unsigned int fd : 5,
891 __BITFIELD_FIELD(unsigned int func : 6,
895 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
896 __BITFIELD_FIELD(unsigned int opcode : 6,
897 __BITFIELD_FIELD(unsigned int ft : 5,
898 __BITFIELD_FIELD(unsigned int fs : 5,
899 __BITFIELD_FIELD(unsigned int fd : 5,
900 __BITFIELD_FIELD(unsigned int fr : 5,
901 __BITFIELD_FIELD(unsigned int func : 6,
905 struct mm_i_format { /* Immediate format (microMIPS) */
906 __BITFIELD_FIELD(unsigned int opcode : 6,
907 __BITFIELD_FIELD(unsigned int rt : 5,
908 __BITFIELD_FIELD(unsigned int rs : 5,
909 __BITFIELD_FIELD(signed int simmediate : 16,
913 struct mm_m_format { /* Multi-word load/store format (microMIPS) */
914 __BITFIELD_FIELD(unsigned int opcode : 6,
915 __BITFIELD_FIELD(unsigned int rd : 5,
916 __BITFIELD_FIELD(unsigned int base : 5,
917 __BITFIELD_FIELD(unsigned int func : 4,
918 __BITFIELD_FIELD(signed int simmediate : 12,
922 struct mm_x_format { /* Scaled indexed load format (microMIPS) */
923 __BITFIELD_FIELD(unsigned int opcode : 6,
924 __BITFIELD_FIELD(unsigned int index : 5,
925 __BITFIELD_FIELD(unsigned int base : 5,
926 __BITFIELD_FIELD(unsigned int rd : 5,
927 __BITFIELD_FIELD(unsigned int func : 11,
931 struct mm_a_format { /* ADDIUPC format (microMIPS) */
932 __BITFIELD_FIELD(unsigned int opcode : 6,
933 __BITFIELD_FIELD(unsigned int rs : 3,
934 __BITFIELD_FIELD(signed int simmediate : 23,
939 * microMIPS instruction formats (16-bit length)
941 struct mm_b0_format { /* Unconditional branch format (microMIPS) */
942 __BITFIELD_FIELD(unsigned int opcode : 6,
943 __BITFIELD_FIELD(signed int simmediate : 10,
944 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
948 struct mm_b1_format { /* Conditional branch format (microMIPS) */
949 __BITFIELD_FIELD(unsigned int opcode : 6,
950 __BITFIELD_FIELD(unsigned int rs : 3,
951 __BITFIELD_FIELD(signed int simmediate : 7,
952 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
956 struct mm16_m_format { /* Multi-word load/store format */
957 __BITFIELD_FIELD(unsigned int opcode : 6,
958 __BITFIELD_FIELD(unsigned int func : 4,
959 __BITFIELD_FIELD(unsigned int rlist : 2,
960 __BITFIELD_FIELD(unsigned int imm : 4,
961 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
965 struct mm16_rb_format { /* Signed immediate format */
966 __BITFIELD_FIELD(unsigned int opcode : 6,
967 __BITFIELD_FIELD(unsigned int rt : 3,
968 __BITFIELD_FIELD(unsigned int base : 3,
969 __BITFIELD_FIELD(signed int simmediate : 4,
970 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
974 struct mm16_r3_format { /* Load from global pointer format */
975 __BITFIELD_FIELD(unsigned int opcode : 6,
976 __BITFIELD_FIELD(unsigned int rt : 3,
977 __BITFIELD_FIELD(signed int simmediate : 7,
978 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
982 struct mm16_r5_format { /* Load/store from stack pointer format */
983 __BITFIELD_FIELD(unsigned int opcode : 6,
984 __BITFIELD_FIELD(unsigned int rt : 5,
985 __BITFIELD_FIELD(unsigned int imm : 5,
986 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
991 * MIPS16e instruction formats (16-bit length)
994 __BITFIELD_FIELD(unsigned int opcode : 5,
995 __BITFIELD_FIELD(unsigned int rx : 3,
996 __BITFIELD_FIELD(unsigned int nd : 1,
997 __BITFIELD_FIELD(unsigned int l : 1,
998 __BITFIELD_FIELD(unsigned int ra : 1,
999 __BITFIELD_FIELD(unsigned int func : 5,
1004 __BITFIELD_FIELD(unsigned int opcode : 5,
1005 __BITFIELD_FIELD(unsigned int x : 1,
1006 __BITFIELD_FIELD(unsigned int imm20_16 : 5,
1007 __BITFIELD_FIELD(signed int imm25_21 : 5,
1012 __BITFIELD_FIELD(unsigned int opcode : 5,
1013 __BITFIELD_FIELD(unsigned int func : 3,
1014 __BITFIELD_FIELD(unsigned int imm : 8,
1019 __BITFIELD_FIELD(unsigned int opcode : 5,
1020 __BITFIELD_FIELD(unsigned int func : 3,
1021 __BITFIELD_FIELD(unsigned int ry : 3,
1022 __BITFIELD_FIELD(unsigned int imm : 5,
1027 __BITFIELD_FIELD(unsigned int opcode : 5,
1028 __BITFIELD_FIELD(unsigned int rx : 3,
1029 __BITFIELD_FIELD(unsigned int imm : 8,
1034 __BITFIELD_FIELD(unsigned int opcode : 5,
1035 __BITFIELD_FIELD(unsigned int rx : 3,
1036 __BITFIELD_FIELD(unsigned int ry : 3,
1037 __BITFIELD_FIELD(unsigned int imm : 5,
1042 __BITFIELD_FIELD(unsigned int opcode : 5,
1043 __BITFIELD_FIELD(unsigned int func : 3,
1044 __BITFIELD_FIELD(unsigned int imm : 8,
1048 union mips_instruction {
1050 unsigned short halfword[2];
1051 unsigned char byte[4];
1052 struct j_format j_format;
1053 struct i_format i_format;
1054 struct u_format u_format;
1055 struct c_format c_format;
1056 struct r_format r_format;
1057 struct c0r_format c0r_format;
1058 struct mfmc0_format mfmc0_format;
1059 struct co_format co_format;
1060 struct p_format p_format;
1061 struct f_format f_format;
1062 struct ma_format ma_format;
1063 struct msa_mi10_format msa_mi10_format;
1064 struct b_format b_format;
1065 struct ps_format ps_format;
1066 struct v_format v_format;
1067 struct dsp_format dsp_format;
1068 struct spec3_format spec3_format;
1069 struct fb_format fb_format;
1070 struct fp0_format fp0_format;
1071 struct mm_fp0_format mm_fp0_format;
1072 struct fp1_format fp1_format;
1073 struct mm_fp1_format mm_fp1_format;
1074 struct mm_fp2_format mm_fp2_format;
1075 struct mm_fp3_format mm_fp3_format;
1076 struct mm_fp4_format mm_fp4_format;
1077 struct mm_fp5_format mm_fp5_format;
1078 struct fp6_format fp6_format;
1079 struct mm_fp6_format mm_fp6_format;
1080 struct mm_i_format mm_i_format;
1081 struct mm_m_format mm_m_format;
1082 struct mm_x_format mm_x_format;
1083 struct mm_a_format mm_a_format;
1084 struct mm_b0_format mm_b0_format;
1085 struct mm_b1_format mm_b1_format;
1086 struct mm16_m_format mm16_m_format ;
1087 struct mm16_rb_format mm16_rb_format;
1088 struct mm16_r3_format mm16_r3_format;
1089 struct mm16_r5_format mm16_r5_format;
1092 union mips16e_instruction {
1093 unsigned int full : 16;
1095 struct m16e_jal jal;
1096 struct m16e_i64 i64;
1097 struct m16e_ri64 ri64;
1099 struct m16e_rri rri;
1103 #endif /* _UAPI_ASM_INST_H */