2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 #ifndef _ASM_SPINLOCK_H
10 #define _ASM_SPINLOCK_H
12 #include <linux/compiler.h>
14 #include <asm/barrier.h>
15 #include <asm/processor.h>
16 #include <asm/compiler.h>
20 * Your basic SMP spinlocks, allowing only a single CPU anywhere
22 * Simple spin lock operations. There are two variants, one clears IRQ's
23 * on the local processor, one does not.
25 * These are fair FIFO ticket locks
27 * (the type definitions are in asm/spinlock_types.h)
32 * Ticket locks are conceptually two parts, one indicating the current head of
33 * the queue, and the other indicating the current tail. The lock is acquired
34 * by atomically noting the tail and incrementing it by one (thus adding
35 * ourself to the queue and noting our position), then waiting until the head
36 * becomes equal to the the initial value of the tail.
39 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
41 u32 counters = ACCESS_ONCE(lock->lock);
43 return ((counters >> 16) ^ counters) & 0xffff;
46 static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
48 return lock.h.serving_now == lock.h.ticket;
51 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
53 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
55 u16 owner = READ_ONCE(lock->h.serving_now);
58 arch_spinlock_t tmp = READ_ONCE(*lock);
60 if (tmp.h.serving_now == tmp.h.ticket ||
61 tmp.h.serving_now != owner)
66 smp_acquire__after_ctrl_dep();
69 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
71 u32 counters = ACCESS_ONCE(lock->lock);
73 return (((counters >> 16) - counters) & 0xffff) > 1;
75 #define arch_spin_is_contended arch_spin_is_contended
77 static inline void arch_spin_lock(arch_spinlock_t *lock)
83 if (R10000_LLSC_WAR) {
84 __asm__ __volatile__ (
85 " .set push # arch_spin_lock \n"
88 "1: ll %[ticket], %[ticket_ptr] \n"
89 " addu %[my_ticket], %[ticket], %[inc] \n"
90 " sc %[my_ticket], %[ticket_ptr] \n"
91 " beqzl %[my_ticket], 1b \n"
93 " srl %[my_ticket], %[ticket], 16 \n"
94 " andi %[ticket], %[ticket], 0xffff \n"
95 " bne %[ticket], %[my_ticket], 4f \n"
96 " subu %[ticket], %[my_ticket], %[ticket] \n"
99 "4: andi %[ticket], %[ticket], 0xffff \n"
100 " sll %[ticket], 5 \n"
102 "6: bnez %[ticket], 6b \n"
103 " subu %[ticket], 1 \n"
105 " lhu %[ticket], %[serving_now_ptr] \n"
106 " beq %[ticket], %[my_ticket], 2b \n"
107 " subu %[ticket], %[my_ticket], %[ticket] \n"
109 " subu %[ticket], %[ticket], 1 \n"
112 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
113 [serving_now_ptr] "+m" (lock->h.serving_now),
114 [ticket] "=&r" (tmp),
115 [my_ticket] "=&r" (my_ticket)
118 __asm__ __volatile__ (
119 " .set push # arch_spin_lock \n"
122 "1: ll %[ticket], %[ticket_ptr] \n"
123 " addu %[my_ticket], %[ticket], %[inc] \n"
124 " sc %[my_ticket], %[ticket_ptr] \n"
125 " beqz %[my_ticket], 1b \n"
126 " srl %[my_ticket], %[ticket], 16 \n"
127 " andi %[ticket], %[ticket], 0xffff \n"
128 " bne %[ticket], %[my_ticket], 4f \n"
129 " subu %[ticket], %[my_ticket], %[ticket] \n"
132 "4: andi %[ticket], %[ticket], 0xffff \n"
133 " sll %[ticket], 5 \n"
135 "6: bnez %[ticket], 6b \n"
136 " subu %[ticket], 1 \n"
138 " lhu %[ticket], %[serving_now_ptr] \n"
139 " beq %[ticket], %[my_ticket], 2b \n"
140 " subu %[ticket], %[my_ticket], %[ticket] \n"
142 " subu %[ticket], %[ticket], 1 \n"
145 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
146 [serving_now_ptr] "+m" (lock->h.serving_now),
147 [ticket] "=&r" (tmp),
148 [my_ticket] "=&r" (my_ticket)
155 static inline void arch_spin_unlock(arch_spinlock_t *lock)
157 unsigned int serving_now = lock->h.serving_now + 1;
159 lock->h.serving_now = (u16)serving_now;
163 static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
168 if (R10000_LLSC_WAR) {
169 __asm__ __volatile__ (
170 " .set push # arch_spin_trylock \n"
173 "1: ll %[ticket], %[ticket_ptr] \n"
174 " srl %[my_ticket], %[ticket], 16 \n"
175 " andi %[now_serving], %[ticket], 0xffff \n"
176 " bne %[my_ticket], %[now_serving], 3f \n"
177 " addu %[ticket], %[ticket], %[inc] \n"
178 " sc %[ticket], %[ticket_ptr] \n"
179 " beqzl %[ticket], 1b \n"
180 " li %[ticket], 1 \n"
184 " li %[ticket], 0 \n"
187 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
188 [ticket] "=&r" (tmp),
189 [my_ticket] "=&r" (tmp2),
190 [now_serving] "=&r" (tmp3)
193 __asm__ __volatile__ (
194 " .set push # arch_spin_trylock \n"
197 "1: ll %[ticket], %[ticket_ptr] \n"
198 " srl %[my_ticket], %[ticket], 16 \n"
199 " andi %[now_serving], %[ticket], 0xffff \n"
200 " bne %[my_ticket], %[now_serving], 3f \n"
201 " addu %[ticket], %[ticket], %[inc] \n"
202 " sc %[ticket], %[ticket_ptr] \n"
203 " beqz %[ticket], 1b \n"
204 " li %[ticket], 1 \n"
208 " li %[ticket], 0 \n"
211 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
212 [ticket] "=&r" (tmp),
213 [my_ticket] "=&r" (tmp2),
214 [now_serving] "=&r" (tmp3)
224 * Read-write spinlocks, allowing multiple readers but only one writer.
226 * NOTE! it is quite common to have readers in interrupts but no interrupt
227 * writers. For those circumstances we can "mix" irq-safe locks - any writer
228 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
233 * read_can_lock - would read_trylock() succeed?
234 * @lock: the rwlock in question.
236 #define arch_read_can_lock(rw) ((rw)->lock >= 0)
239 * write_can_lock - would write_trylock() succeed?
240 * @lock: the rwlock in question.
242 #define arch_write_can_lock(rw) (!(rw)->lock)
244 static inline void arch_read_lock(arch_rwlock_t *rw)
248 if (R10000_LLSC_WAR) {
249 __asm__ __volatile__(
250 " .set noreorder # arch_read_lock \n"
258 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
259 : GCC_OFF_SMALL_ASM() (rw->lock)
263 __asm__ __volatile__(
264 "1: ll %1, %2 # arch_read_lock \n"
268 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
269 : GCC_OFF_SMALL_ASM() (rw->lock)
271 } while (unlikely(!tmp));
277 static inline void arch_read_unlock(arch_rwlock_t *rw)
281 smp_mb__before_llsc();
283 if (R10000_LLSC_WAR) {
284 __asm__ __volatile__(
285 "1: ll %1, %2 # arch_read_unlock \n"
289 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
290 : GCC_OFF_SMALL_ASM() (rw->lock)
294 __asm__ __volatile__(
295 "1: ll %1, %2 # arch_read_unlock \n"
298 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
299 : GCC_OFF_SMALL_ASM() (rw->lock)
301 } while (unlikely(!tmp));
305 static inline void arch_write_lock(arch_rwlock_t *rw)
309 if (R10000_LLSC_WAR) {
310 __asm__ __volatile__(
311 " .set noreorder # arch_write_lock \n"
319 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
320 : GCC_OFF_SMALL_ASM() (rw->lock)
324 __asm__ __volatile__(
325 "1: ll %1, %2 # arch_write_lock \n"
329 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
330 : GCC_OFF_SMALL_ASM() (rw->lock)
332 } while (unlikely(!tmp));
338 static inline void arch_write_unlock(arch_rwlock_t *rw)
340 smp_mb__before_llsc();
342 __asm__ __volatile__(
343 " # arch_write_unlock \n"
350 static inline int arch_read_trylock(arch_rwlock_t *rw)
355 if (R10000_LLSC_WAR) {
356 __asm__ __volatile__(
357 " .set noreorder # arch_read_trylock \n"
369 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
370 : GCC_OFF_SMALL_ASM() (rw->lock)
373 __asm__ __volatile__(
374 " .set noreorder # arch_read_trylock \n"
386 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
387 : GCC_OFF_SMALL_ASM() (rw->lock)
394 static inline int arch_write_trylock(arch_rwlock_t *rw)
399 if (R10000_LLSC_WAR) {
400 __asm__ __volatile__(
401 " .set noreorder # arch_write_trylock \n"
413 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
414 : GCC_OFF_SMALL_ASM() (rw->lock)
418 __asm__ __volatile__(
419 " ll %1, %3 # arch_write_trylock \n"
426 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp),
428 : GCC_OFF_SMALL_ASM() (rw->lock)
430 } while (unlikely(!tmp));
438 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
439 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
441 #define arch_spin_relax(lock) cpu_relax()
442 #define arch_read_relax(lock) cpu_relax()
443 #define arch_write_relax(lock) cpu_relax()
445 #endif /* _ASM_SPINLOCK_H */