arch/mips/include/asm/octeon/cvmx-uctlx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
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  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
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  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_UCTLX_DEFS_H__
  29 #define __CVMX_UCTLX_DEFS_H__
  30
  31 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
  32 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
  33 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
  34 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
  35 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
  36 #define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
  37 #define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
  38 #define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
  39 #define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
  40 #define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
  41 #define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
  42 #define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
  43 #define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
  44
  45 union cvmx_uctlx_bist_status {
  46         uint64_t u64;
  47         struct cvmx_uctlx_bist_status_s {
  48 #ifdef __BIG_ENDIAN_BITFIELD
  49                 uint64_t reserved_6_63:58;
  50                 uint64_t data_bis:1;
  51                 uint64_t desc_bis:1;
  52                 uint64_t erbm_bis:1;
  53                 uint64_t orbm_bis:1;
  54                 uint64_t wrbm_bis:1;
  55                 uint64_t ppaf_bis:1;
  56 #else
  57                 uint64_t ppaf_bis:1;
  58                 uint64_t wrbm_bis:1;
  59                 uint64_t orbm_bis:1;
  60                 uint64_t erbm_bis:1;
  61                 uint64_t desc_bis:1;
  62                 uint64_t data_bis:1;
  63                 uint64_t reserved_6_63:58;
  64 #endif
  65         } s;
  66 };
  67
  68 union cvmx_uctlx_clk_rst_ctl {
  69         uint64_t u64;
  70         struct cvmx_uctlx_clk_rst_ctl_s {
  71 #ifdef __BIG_ENDIAN_BITFIELD
  72                 uint64_t reserved_25_63:39;
  73                 uint64_t clear_bist:1;
  74                 uint64_t start_bist:1;
  75                 uint64_t ehci_sm:1;
  76                 uint64_t ohci_clkcktrst:1;
  77                 uint64_t ohci_sm:1;
  78                 uint64_t ohci_susp_lgcy:1;
  79                 uint64_t app_start_clk:1;
  80                 uint64_t o_clkdiv_rst:1;
  81                 uint64_t h_clkdiv_byp:1;
  82                 uint64_t h_clkdiv_rst:1;
  83                 uint64_t h_clkdiv_en:1;
  84                 uint64_t o_clkdiv_en:1;
  85                 uint64_t h_div:4;
  86                 uint64_t p_refclk_sel:2;
  87                 uint64_t p_refclk_div:2;
  88                 uint64_t reserved_4_4:1;
  89                 uint64_t p_com_on:1;
  90                 uint64_t p_por:1;
  91                 uint64_t p_prst:1;
  92                 uint64_t hrst:1;
  93 #else
  94                 uint64_t hrst:1;
  95                 uint64_t p_prst:1;
  96                 uint64_t p_por:1;
  97                 uint64_t p_com_on:1;
  98                 uint64_t reserved_4_4:1;
  99                 uint64_t p_refclk_div:2;
 100                 uint64_t p_refclk_sel:2;
 101                 uint64_t h_div:4;
 102                 uint64_t o_clkdiv_en:1;
 103                 uint64_t h_clkdiv_en:1;
 104                 uint64_t h_clkdiv_rst:1;
 105                 uint64_t h_clkdiv_byp:1;
 106                 uint64_t o_clkdiv_rst:1;
 107                 uint64_t app_start_clk:1;
 108                 uint64_t ohci_susp_lgcy:1;
 109                 uint64_t ohci_sm:1;
 110                 uint64_t ohci_clkcktrst:1;
 111                 uint64_t ehci_sm:1;
 112                 uint64_t start_bist:1;
 113                 uint64_t clear_bist:1;
 114                 uint64_t reserved_25_63:39;
 115 #endif
 116         } s;
 117 };
 118
 119 union cvmx_uctlx_ehci_ctl {
 120         uint64_t u64;
 121         struct cvmx_uctlx_ehci_ctl_s {
 122 #ifdef __BIG_ENDIAN_BITFIELD
 123                 uint64_t reserved_20_63:44;
 124                 uint64_t desc_rbm:1;
 125                 uint64_t reg_nb:1;
 126                 uint64_t l2c_dc:1;
 127                 uint64_t l2c_bc:1;
 128                 uint64_t l2c_0pag:1;
 129                 uint64_t l2c_stt:1;
 130                 uint64_t l2c_buff_emod:2;
 131                 uint64_t l2c_desc_emod:2;
 132                 uint64_t inv_reg_a2:1;
 133                 uint64_t ehci_64b_addr_en:1;
 134                 uint64_t l2c_addr_msb:8;
 135 #else
 136                 uint64_t l2c_addr_msb:8;
 137                 uint64_t ehci_64b_addr_en:1;
 138                 uint64_t inv_reg_a2:1;
 139                 uint64_t l2c_desc_emod:2;
 140                 uint64_t l2c_buff_emod:2;
 141                 uint64_t l2c_stt:1;
 142                 uint64_t l2c_0pag:1;
 143                 uint64_t l2c_bc:1;
 144                 uint64_t l2c_dc:1;
 145                 uint64_t reg_nb:1;
 146                 uint64_t desc_rbm:1;
 147                 uint64_t reserved_20_63:44;
 148 #endif
 149         } s;
 150 };
 151
 152 union cvmx_uctlx_ehci_fla {
 153         uint64_t u64;
 154         struct cvmx_uctlx_ehci_fla_s {
 155 #ifdef __BIG_ENDIAN_BITFIELD
 156                 uint64_t reserved_6_63:58;
 157                 uint64_t fla:6;
 158 #else
 159                 uint64_t fla:6;
 160                 uint64_t reserved_6_63:58;
 161 #endif
 162         } s;
 163 };
 164
 165 union cvmx_uctlx_erto_ctl {
 166         uint64_t u64;
 167         struct cvmx_uctlx_erto_ctl_s {
 168 #ifdef __BIG_ENDIAN_BITFIELD
 169                 uint64_t reserved_32_63:32;
 170                 uint64_t to_val:27;
 171                 uint64_t reserved_0_4:5;
 172 #else
 173                 uint64_t reserved_0_4:5;
 174                 uint64_t to_val:27;
 175                 uint64_t reserved_32_63:32;
 176 #endif
 177         } s;
 178 };
 179
 180 union cvmx_uctlx_if_ena {
 181         uint64_t u64;
 182         struct cvmx_uctlx_if_ena_s {
 183 #ifdef __BIG_ENDIAN_BITFIELD
 184                 uint64_t reserved_1_63:63;
 185                 uint64_t en:1;
 186 #else
 187                 uint64_t en:1;
 188                 uint64_t reserved_1_63:63;
 189 #endif
 190         } s;
 191 };
 192
 193 union cvmx_uctlx_int_ena {
 194         uint64_t u64;
 195         struct cvmx_uctlx_int_ena_s {
 196 #ifdef __BIG_ENDIAN_BITFIELD
 197                 uint64_t reserved_8_63:56;
 198                 uint64_t ec_ovf_e:1;
 199                 uint64_t oc_ovf_e:1;
 200                 uint64_t wb_pop_e:1;
 201                 uint64_t wb_psh_f:1;
 202                 uint64_t cf_psh_f:1;
 203                 uint64_t or_psh_f:1;
 204                 uint64_t er_psh_f:1;
 205                 uint64_t pp_psh_f:1;
 206 #else
 207                 uint64_t pp_psh_f:1;
 208                 uint64_t er_psh_f:1;
 209                 uint64_t or_psh_f:1;
 210                 uint64_t cf_psh_f:1;
 211                 uint64_t wb_psh_f:1;
 212                 uint64_t wb_pop_e:1;
 213                 uint64_t oc_ovf_e:1;
 214                 uint64_t ec_ovf_e:1;
 215                 uint64_t reserved_8_63:56;
 216 #endif
 217         } s;
 218 };
 219
 220 union cvmx_uctlx_int_reg {
 221         uint64_t u64;
 222         struct cvmx_uctlx_int_reg_s {
 223 #ifdef __BIG_ENDIAN_BITFIELD
 224                 uint64_t reserved_8_63:56;
 225                 uint64_t ec_ovf_e:1;
 226                 uint64_t oc_ovf_e:1;
 227                 uint64_t wb_pop_e:1;
 228                 uint64_t wb_psh_f:1;
 229                 uint64_t cf_psh_f:1;
 230                 uint64_t or_psh_f:1;
 231                 uint64_t er_psh_f:1;
 232                 uint64_t pp_psh_f:1;
 233 #else
 234                 uint64_t pp_psh_f:1;
 235                 uint64_t er_psh_f:1;
 236                 uint64_t or_psh_f:1;
 237                 uint64_t cf_psh_f:1;
 238                 uint64_t wb_psh_f:1;
 239                 uint64_t wb_pop_e:1;
 240                 uint64_t oc_ovf_e:1;
 241                 uint64_t ec_ovf_e:1;
 242                 uint64_t reserved_8_63:56;
 243 #endif
 244         } s;
 245 };
 246
 247 union cvmx_uctlx_ohci_ctl {
 248         uint64_t u64;
 249         struct cvmx_uctlx_ohci_ctl_s {
 250 #ifdef __BIG_ENDIAN_BITFIELD
 251                 uint64_t reserved_19_63:45;
 252                 uint64_t reg_nb:1;
 253                 uint64_t l2c_dc:1;
 254                 uint64_t l2c_bc:1;
 255                 uint64_t l2c_0pag:1;
 256                 uint64_t l2c_stt:1;
 257                 uint64_t l2c_buff_emod:2;
 258                 uint64_t l2c_desc_emod:2;
 259                 uint64_t inv_reg_a2:1;
 260                 uint64_t reserved_8_8:1;
 261                 uint64_t l2c_addr_msb:8;
 262 #else
 263                 uint64_t l2c_addr_msb:8;
 264                 uint64_t reserved_8_8:1;
 265                 uint64_t inv_reg_a2:1;
 266                 uint64_t l2c_desc_emod:2;
 267                 uint64_t l2c_buff_emod:2;
 268                 uint64_t l2c_stt:1;
 269                 uint64_t l2c_0pag:1;
 270                 uint64_t l2c_bc:1;
 271                 uint64_t l2c_dc:1;
 272                 uint64_t reg_nb:1;
 273                 uint64_t reserved_19_63:45;
 274 #endif
 275         } s;
 276 };
 277
 278 union cvmx_uctlx_orto_ctl {
 279         uint64_t u64;
 280         struct cvmx_uctlx_orto_ctl_s {
 281 #ifdef __BIG_ENDIAN_BITFIELD
 282                 uint64_t reserved_32_63:32;
 283                 uint64_t to_val:24;
 284                 uint64_t reserved_0_7:8;
 285 #else
 286                 uint64_t reserved_0_7:8;
 287                 uint64_t to_val:24;
 288                 uint64_t reserved_32_63:32;
 289 #endif
 290         } s;
 291 };
 292
 293 union cvmx_uctlx_ppaf_wm {
 294         uint64_t u64;
 295         struct cvmx_uctlx_ppaf_wm_s {
 296 #ifdef __BIG_ENDIAN_BITFIELD
 297                 uint64_t reserved_5_63:59;
 298                 uint64_t wm:5;
 299 #else
 300                 uint64_t wm:5;
 301                 uint64_t reserved_5_63:59;
 302 #endif
 303         } s;
 304 };
 305
 306 union cvmx_uctlx_uphy_ctl_status {
 307         uint64_t u64;
 308         struct cvmx_uctlx_uphy_ctl_status_s {
 309 #ifdef __BIG_ENDIAN_BITFIELD
 310                 uint64_t reserved_10_63:54;
 311                 uint64_t bist_done:1;
 312                 uint64_t bist_err:1;
 313                 uint64_t hsbist:1;
 314                 uint64_t fsbist:1;
 315                 uint64_t lsbist:1;
 316                 uint64_t siddq:1;
 317                 uint64_t vtest_en:1;
 318                 uint64_t uphy_bist:1;
 319                 uint64_t bist_en:1;
 320                 uint64_t ate_reset:1;
 321 #else
 322                 uint64_t ate_reset:1;
 323                 uint64_t bist_en:1;
 324                 uint64_t uphy_bist:1;
 325                 uint64_t vtest_en:1;
 326                 uint64_t siddq:1;
 327                 uint64_t lsbist:1;
 328                 uint64_t fsbist:1;
 329                 uint64_t hsbist:1;
 330                 uint64_t bist_err:1;
 331                 uint64_t bist_done:1;
 332                 uint64_t reserved_10_63:54;
 333 #endif
 334         } s;
 335 };
 336
 337 union cvmx_uctlx_uphy_portx_ctl_status {
 338         uint64_t u64;
 339         struct cvmx_uctlx_uphy_portx_ctl_status_s {
 340 #ifdef __BIG_ENDIAN_BITFIELD
 341                 uint64_t reserved_43_63:21;
 342                 uint64_t tdata_out:4;
 343                 uint64_t txbiststuffenh:1;
 344                 uint64_t txbiststuffen:1;
 345                 uint64_t dmpulldown:1;
 346                 uint64_t dppulldown:1;
 347                 uint64_t vbusvldext:1;
 348                 uint64_t portreset:1;
 349                 uint64_t txhsvxtune:2;
 350                 uint64_t txvreftune:4;
 351                 uint64_t txrisetune:1;
 352                 uint64_t txpreemphasistune:1;
 353                 uint64_t txfslstune:4;
 354                 uint64_t sqrxtune:3;
 355                 uint64_t compdistune:3;
 356                 uint64_t loop_en:1;
 357                 uint64_t tclk:1;
 358                 uint64_t tdata_sel:1;
 359                 uint64_t taddr_in:4;
 360                 uint64_t tdata_in:8;
 361 #else
 362                 uint64_t tdata_in:8;
 363                 uint64_t taddr_in:4;
 364                 uint64_t tdata_sel:1;
 365                 uint64_t tclk:1;
 366                 uint64_t loop_en:1;
 367                 uint64_t compdistune:3;
 368                 uint64_t sqrxtune:3;
 369                 uint64_t txfslstune:4;
 370                 uint64_t txpreemphasistune:1;
 371                 uint64_t txrisetune:1;
 372                 uint64_t txvreftune:4;
 373                 uint64_t txhsvxtune:2;
 374                 uint64_t portreset:1;
 375                 uint64_t vbusvldext:1;
 376                 uint64_t dppulldown:1;
 377                 uint64_t dmpulldown:1;
 378                 uint64_t txbiststuffen:1;
 379                 uint64_t txbiststuffenh:1;
 380                 uint64_t tdata_out:4;
 381                 uint64_t reserved_43_63:21;
 382 #endif
 383         } s;
 384 };
 385
 386 #endif