1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_UCTLX_DEFS_H__
29 #define __CVMX_UCTLX_DEFS_H__
31 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
32 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
33 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
34 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
35 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
36 #define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
37 #define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
38 #define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
39 #define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
40 #define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
41 #define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
42 #define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
43 #define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
45 union cvmx_uctlx_bist_status {
47 struct cvmx_uctlx_bist_status_s {
48 #ifdef __BIG_ENDIAN_BITFIELD
49 uint64_t reserved_6_63:58;
63 uint64_t reserved_6_63:58;
68 union cvmx_uctlx_clk_rst_ctl {
70 struct cvmx_uctlx_clk_rst_ctl_s {
71 #ifdef __BIG_ENDIAN_BITFIELD
72 uint64_t reserved_25_63:39;
73 uint64_t clear_bist:1;
74 uint64_t start_bist:1;
76 uint64_t ohci_clkcktrst:1;
78 uint64_t ohci_susp_lgcy:1;
79 uint64_t app_start_clk:1;
80 uint64_t o_clkdiv_rst:1;
81 uint64_t h_clkdiv_byp:1;
82 uint64_t h_clkdiv_rst:1;
83 uint64_t h_clkdiv_en:1;
84 uint64_t o_clkdiv_en:1;
86 uint64_t p_refclk_sel:2;
87 uint64_t p_refclk_div:2;
88 uint64_t reserved_4_4:1;
98 uint64_t reserved_4_4:1;
99 uint64_t p_refclk_div:2;
100 uint64_t p_refclk_sel:2;
102 uint64_t o_clkdiv_en:1;
103 uint64_t h_clkdiv_en:1;
104 uint64_t h_clkdiv_rst:1;
105 uint64_t h_clkdiv_byp:1;
106 uint64_t o_clkdiv_rst:1;
107 uint64_t app_start_clk:1;
108 uint64_t ohci_susp_lgcy:1;
110 uint64_t ohci_clkcktrst:1;
112 uint64_t start_bist:1;
113 uint64_t clear_bist:1;
114 uint64_t reserved_25_63:39;
119 union cvmx_uctlx_ehci_ctl {
121 struct cvmx_uctlx_ehci_ctl_s {
122 #ifdef __BIG_ENDIAN_BITFIELD
123 uint64_t reserved_20_63:44;
130 uint64_t l2c_buff_emod:2;
131 uint64_t l2c_desc_emod:2;
132 uint64_t inv_reg_a2:1;
133 uint64_t ehci_64b_addr_en:1;
134 uint64_t l2c_addr_msb:8;
136 uint64_t l2c_addr_msb:8;
137 uint64_t ehci_64b_addr_en:1;
138 uint64_t inv_reg_a2:1;
139 uint64_t l2c_desc_emod:2;
140 uint64_t l2c_buff_emod:2;
147 uint64_t reserved_20_63:44;
152 union cvmx_uctlx_ehci_fla {
154 struct cvmx_uctlx_ehci_fla_s {
155 #ifdef __BIG_ENDIAN_BITFIELD
156 uint64_t reserved_6_63:58;
160 uint64_t reserved_6_63:58;
165 union cvmx_uctlx_erto_ctl {
167 struct cvmx_uctlx_erto_ctl_s {
168 #ifdef __BIG_ENDIAN_BITFIELD
169 uint64_t reserved_32_63:32;
171 uint64_t reserved_0_4:5;
173 uint64_t reserved_0_4:5;
175 uint64_t reserved_32_63:32;
180 union cvmx_uctlx_if_ena {
182 struct cvmx_uctlx_if_ena_s {
183 #ifdef __BIG_ENDIAN_BITFIELD
184 uint64_t reserved_1_63:63;
188 uint64_t reserved_1_63:63;
193 union cvmx_uctlx_int_ena {
195 struct cvmx_uctlx_int_ena_s {
196 #ifdef __BIG_ENDIAN_BITFIELD
197 uint64_t reserved_8_63:56;
215 uint64_t reserved_8_63:56;
220 union cvmx_uctlx_int_reg {
222 struct cvmx_uctlx_int_reg_s {
223 #ifdef __BIG_ENDIAN_BITFIELD
224 uint64_t reserved_8_63:56;
242 uint64_t reserved_8_63:56;
247 union cvmx_uctlx_ohci_ctl {
249 struct cvmx_uctlx_ohci_ctl_s {
250 #ifdef __BIG_ENDIAN_BITFIELD
251 uint64_t reserved_19_63:45;
257 uint64_t l2c_buff_emod:2;
258 uint64_t l2c_desc_emod:2;
259 uint64_t inv_reg_a2:1;
260 uint64_t reserved_8_8:1;
261 uint64_t l2c_addr_msb:8;
263 uint64_t l2c_addr_msb:8;
264 uint64_t reserved_8_8:1;
265 uint64_t inv_reg_a2:1;
266 uint64_t l2c_desc_emod:2;
267 uint64_t l2c_buff_emod:2;
273 uint64_t reserved_19_63:45;
278 union cvmx_uctlx_orto_ctl {
280 struct cvmx_uctlx_orto_ctl_s {
281 #ifdef __BIG_ENDIAN_BITFIELD
282 uint64_t reserved_32_63:32;
284 uint64_t reserved_0_7:8;
286 uint64_t reserved_0_7:8;
288 uint64_t reserved_32_63:32;
293 union cvmx_uctlx_ppaf_wm {
295 struct cvmx_uctlx_ppaf_wm_s {
296 #ifdef __BIG_ENDIAN_BITFIELD
297 uint64_t reserved_5_63:59;
301 uint64_t reserved_5_63:59;
306 union cvmx_uctlx_uphy_ctl_status {
308 struct cvmx_uctlx_uphy_ctl_status_s {
309 #ifdef __BIG_ENDIAN_BITFIELD
310 uint64_t reserved_10_63:54;
311 uint64_t bist_done:1;
318 uint64_t uphy_bist:1;
320 uint64_t ate_reset:1;
322 uint64_t ate_reset:1;
324 uint64_t uphy_bist:1;
331 uint64_t bist_done:1;
332 uint64_t reserved_10_63:54;
337 union cvmx_uctlx_uphy_portx_ctl_status {
339 struct cvmx_uctlx_uphy_portx_ctl_status_s {
340 #ifdef __BIG_ENDIAN_BITFIELD
341 uint64_t reserved_43_63:21;
342 uint64_t tdata_out:4;
343 uint64_t txbiststuffenh:1;
344 uint64_t txbiststuffen:1;
345 uint64_t dmpulldown:1;
346 uint64_t dppulldown:1;
347 uint64_t vbusvldext:1;
348 uint64_t portreset:1;
349 uint64_t txhsvxtune:2;
350 uint64_t txvreftune:4;
351 uint64_t txrisetune:1;
352 uint64_t txpreemphasistune:1;
353 uint64_t txfslstune:4;
355 uint64_t compdistune:3;
358 uint64_t tdata_sel:1;
364 uint64_t tdata_sel:1;
367 uint64_t compdistune:3;
369 uint64_t txfslstune:4;
370 uint64_t txpreemphasistune:1;
371 uint64_t txrisetune:1;
372 uint64_t txvreftune:4;
373 uint64_t txhsvxtune:2;
374 uint64_t portreset:1;
375 uint64_t vbusvldext:1;
376 uint64_t dppulldown:1;
377 uint64_t dmpulldown:1;
378 uint64_t txbiststuffen:1;
379 uint64_t txbiststuffenh:1;
380 uint64_t tdata_out:4;
381 uint64_t reserved_43_63:21;