1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_SRXX_DEFS_H__
29 #define __CVMX_SRXX_DEFS_H__
31 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
34 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
38 union cvmx_srxx_com_ctl {
40 struct cvmx_srxx_com_ctl_s {
41 #ifdef __BIG_ENDIAN_BITFIELD
42 uint64_t reserved_8_63:56;
45 uint64_t reserved_1_2:2;
49 uint64_t reserved_1_2:2;
52 uint64_t reserved_8_63:56;
55 struct cvmx_srxx_com_ctl_s cn38xx;
56 struct cvmx_srxx_com_ctl_s cn38xxp2;
57 struct cvmx_srxx_com_ctl_s cn58xx;
58 struct cvmx_srxx_com_ctl_s cn58xxp1;
61 union cvmx_srxx_ign_rx_full {
63 struct cvmx_srxx_ign_rx_full_s {
64 #ifdef __BIG_ENDIAN_BITFIELD
65 uint64_t reserved_16_63:48;
69 uint64_t reserved_16_63:48;
72 struct cvmx_srxx_ign_rx_full_s cn38xx;
73 struct cvmx_srxx_ign_rx_full_s cn38xxp2;
74 struct cvmx_srxx_ign_rx_full_s cn58xx;
75 struct cvmx_srxx_ign_rx_full_s cn58xxp1;
78 union cvmx_srxx_spi4_calx {
80 struct cvmx_srxx_spi4_calx_s {
81 #ifdef __BIG_ENDIAN_BITFIELD
82 uint64_t reserved_17_63:47;
94 uint64_t reserved_17_63:47;
97 struct cvmx_srxx_spi4_calx_s cn38xx;
98 struct cvmx_srxx_spi4_calx_s cn38xxp2;
99 struct cvmx_srxx_spi4_calx_s cn58xx;
100 struct cvmx_srxx_spi4_calx_s cn58xxp1;
103 union cvmx_srxx_spi4_stat {
105 struct cvmx_srxx_spi4_stat_s {
106 #ifdef __BIG_ENDIAN_BITFIELD
107 uint64_t reserved_16_63:48;
109 uint64_t reserved_7_7:1;
113 uint64_t reserved_7_7:1;
115 uint64_t reserved_16_63:48;
118 struct cvmx_srxx_spi4_stat_s cn38xx;
119 struct cvmx_srxx_spi4_stat_s cn38xxp2;
120 struct cvmx_srxx_spi4_stat_s cn58xx;
121 struct cvmx_srxx_spi4_stat_s cn58xxp1;
124 union cvmx_srxx_sw_tick_ctl {
126 struct cvmx_srxx_sw_tick_ctl_s {
127 #ifdef __BIG_ENDIAN_BITFIELD
128 uint64_t reserved_14_63:50;
140 uint64_t reserved_14_63:50;
143 struct cvmx_srxx_sw_tick_ctl_s cn38xx;
144 struct cvmx_srxx_sw_tick_ctl_s cn58xx;
145 struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
148 union cvmx_srxx_sw_tick_dat {
150 struct cvmx_srxx_sw_tick_dat_s {
151 #ifdef __BIG_ENDIAN_BITFIELD
157 struct cvmx_srxx_sw_tick_dat_s cn38xx;
158 struct cvmx_srxx_sw_tick_dat_s cn58xx;
159 struct cvmx_srxx_sw_tick_dat_s cn58xxp1;