1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_SRIOX_DEFS_H__
29 #define __CVMX_SRIOX_DEFS_H__
31 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
32 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
33 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
34 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
35 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
36 #define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
37 #define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
38 #define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
39 #define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
40 #define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
41 #define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
42 #define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
43 #define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
44 #define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
45 #define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
46 #define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
47 #define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
48 #define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
49 #define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
50 #define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
51 #define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
52 #define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
53 #define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
54 #define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
55 #define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
56 #define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
57 #define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
58 #define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
59 #define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
60 #define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
61 #define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
62 #define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
63 #define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
64 #define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
65 #define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
66 #define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
67 #define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
68 #define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
69 #define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
70 #define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
71 #define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
72 #define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
73 #define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
74 #define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
75 #define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
76 #define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
77 #define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
79 union cvmx_sriox_acc_ctrl {
81 struct cvmx_sriox_acc_ctrl_s {
82 #ifdef __BIG_ENDIAN_BITFIELD
83 uint64_t reserved_7_63:57;
87 uint64_t reserved_3_3:1;
95 uint64_t reserved_3_3:1;
99 uint64_t reserved_7_63:57;
102 struct cvmx_sriox_acc_ctrl_cn63xx {
103 #ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_3_63:61;
105 uint64_t deny_bar2:1;
106 uint64_t deny_bar1:1;
107 uint64_t deny_bar0:1;
109 uint64_t deny_bar0:1;
110 uint64_t deny_bar1:1;
111 uint64_t deny_bar2:1;
112 uint64_t reserved_3_63:61;
117 union cvmx_sriox_asmbly_id {
119 struct cvmx_sriox_asmbly_id_s {
120 #ifdef __BIG_ENDIAN_BITFIELD
121 uint64_t reserved_32_63:32;
123 uint64_t assy_ven:16;
125 uint64_t assy_ven:16;
127 uint64_t reserved_32_63:32;
132 union cvmx_sriox_asmbly_info {
134 struct cvmx_sriox_asmbly_info_s {
135 #ifdef __BIG_ENDIAN_BITFIELD
136 uint64_t reserved_32_63:32;
137 uint64_t assy_rev:16;
138 uint64_t reserved_0_15:16;
140 uint64_t reserved_0_15:16;
141 uint64_t assy_rev:16;
142 uint64_t reserved_32_63:32;
147 union cvmx_sriox_bell_resp_ctrl {
149 struct cvmx_sriox_bell_resp_ctrl_s {
150 #ifdef __BIG_ENDIAN_BITFIELD
151 uint64_t reserved_6_63:58;
161 uint64_t reserved_6_63:58;
166 union cvmx_sriox_bist_status {
168 struct cvmx_sriox_bist_status_s {
169 #ifdef __BIG_ENDIAN_BITFIELD
170 uint64_t reserved_45_63:19;
210 uint64_t reserved_45_63:19;
213 struct cvmx_sriox_bist_status_cn63xx {
214 #ifdef __BIG_ENDIAN_BITFIELD
215 uint64_t reserved_44_63:20;
253 uint64_t reserved_44_63:20;
256 struct cvmx_sriox_bist_status_cn63xxp1 {
257 #ifdef __BIG_ENDIAN_BITFIELD
258 uint64_t reserved_44_63:20;
268 uint64_t reserved_20_23:4;
284 uint64_t reserved_20_23:4;
294 uint64_t reserved_44_63:20;
299 union cvmx_sriox_imsg_ctrl {
301 struct cvmx_sriox_imsg_ctrl_s {
302 #ifdef __BIG_ENDIAN_BITFIELD
303 uint64_t reserved_32_63:32;
305 uint64_t reserved_30_30:1;
307 uint64_t reserved_22_23:2;
312 uint64_t reserved_15_15:1;
322 uint64_t reserved_15_15:1;
327 uint64_t reserved_22_23:2;
329 uint64_t reserved_30_30:1;
331 uint64_t reserved_32_63:32;
336 union cvmx_sriox_imsg_inst_hdrx {
338 struct cvmx_sriox_imsg_inst_hdrx_s {
339 #ifdef __BIG_ENDIAN_BITFIELD
341 uint64_t reserved_58_62:5;
343 uint64_t reserved_55_55:1;
345 uint64_t reserved_46_47:2;
350 uint64_t reserved_35_41:7;
358 uint64_t reserved_35_41:7;
363 uint64_t reserved_46_47:2;
365 uint64_t reserved_55_55:1;
367 uint64_t reserved_58_62:5;
373 union cvmx_sriox_imsg_qos_grpx {
375 struct cvmx_sriox_imsg_qos_grpx_s {
376 #ifdef __BIG_ENDIAN_BITFIELD
377 uint64_t reserved_63_63:1;
380 uint64_t reserved_55_55:1;
383 uint64_t reserved_47_47:1;
386 uint64_t reserved_39_39:1;
389 uint64_t reserved_31_31:1;
392 uint64_t reserved_23_23:1;
395 uint64_t reserved_15_15:1;
398 uint64_t reserved_7_7:1;
404 uint64_t reserved_7_7:1;
407 uint64_t reserved_15_15:1;
410 uint64_t reserved_23_23:1;
413 uint64_t reserved_31_31:1;
416 uint64_t reserved_39_39:1;
419 uint64_t reserved_47_47:1;
422 uint64_t reserved_55_55:1;
425 uint64_t reserved_63_63:1;
430 union cvmx_sriox_imsg_statusx {
432 struct cvmx_sriox_imsg_statusx_s {
433 #ifdef __BIG_ENDIAN_BITFIELD
439 uint64_t reserved_58_58:1;
451 uint64_t reserved_26_26:1;
465 uint64_t reserved_26_26:1;
477 uint64_t reserved_58_58:1;
487 union cvmx_sriox_imsg_vport_thr {
489 struct cvmx_sriox_imsg_vport_thr_s {
490 #ifdef __BIG_ENDIAN_BITFIELD
491 uint64_t reserved_54_63:10;
493 uint64_t reserved_46_47:2;
495 uint64_t reserved_38_39:2;
498 uint64_t reserved_20_30:11;
500 uint64_t reserved_14_15:2;
502 uint64_t reserved_6_7:2;
506 uint64_t reserved_6_7:2;
508 uint64_t reserved_14_15:2;
510 uint64_t reserved_20_30:11;
513 uint64_t reserved_38_39:2;
515 uint64_t reserved_46_47:2;
517 uint64_t reserved_54_63:10;
522 union cvmx_sriox_imsg_vport_thr2 {
524 struct cvmx_sriox_imsg_vport_thr2_s {
525 #ifdef __BIG_ENDIAN_BITFIELD
526 uint64_t reserved_46_63:18;
528 uint64_t reserved_38_39:2;
530 uint64_t reserved_0_31:32;
532 uint64_t reserved_0_31:32;
534 uint64_t reserved_38_39:2;
536 uint64_t reserved_46_63:18;
541 union cvmx_sriox_int2_enable {
543 struct cvmx_sriox_int2_enable_s {
544 #ifdef __BIG_ENDIAN_BITFIELD
545 uint64_t reserved_1_63:63;
549 uint64_t reserved_1_63:63;
554 union cvmx_sriox_int2_reg {
556 struct cvmx_sriox_int2_reg_s {
557 #ifdef __BIG_ENDIAN_BITFIELD
558 uint64_t reserved_32_63:32;
560 uint64_t reserved_1_30:30;
564 uint64_t reserved_1_30:30;
566 uint64_t reserved_32_63:32;
571 union cvmx_sriox_int_enable {
573 struct cvmx_sriox_int_enable_s {
574 #ifdef __BIG_ENDIAN_BITFIELD
575 uint64_t reserved_27_63:37;
631 uint64_t reserved_27_63:37;
634 struct cvmx_sriox_int_enable_cn63xxp1 {
635 #ifdef __BIG_ENDIAN_BITFIELD
636 uint64_t reserved_22_63:42;
682 uint64_t reserved_22_63:42;
687 union cvmx_sriox_int_info0 {
689 struct cvmx_sriox_int_info0_s {
690 #ifdef __BIG_ENDIAN_BITFIELD
694 uint64_t reserved_42_47:6;
697 uint64_t reserved_16_28:13;
703 uint64_t reserved_16_28:13;
706 uint64_t reserved_42_47:6;
714 union cvmx_sriox_int_info1 {
716 struct cvmx_sriox_int_info1_s {
717 #ifdef __BIG_ENDIAN_BITFIELD
725 union cvmx_sriox_int_info2 {
727 struct cvmx_sriox_int_info2_s {
728 #ifdef __BIG_ENDIAN_BITFIELD
756 union cvmx_sriox_int_info3 {
758 struct cvmx_sriox_int_info3_s {
759 #ifdef __BIG_ENDIAN_BITFIELD
764 uint64_t reserved_0_7:8;
766 uint64_t reserved_0_7:8;
775 union cvmx_sriox_int_reg {
777 struct cvmx_sriox_int_reg_s {
778 #ifdef __BIG_ENDIAN_BITFIELD
779 uint64_t reserved_32_63:32;
781 uint64_t reserved_27_30:4;
837 uint64_t reserved_27_30:4;
839 uint64_t reserved_32_63:32;
842 struct cvmx_sriox_int_reg_cn63xxp1 {
843 #ifdef __BIG_ENDIAN_BITFIELD
844 uint64_t reserved_22_63:42;
890 uint64_t reserved_22_63:42;
895 union cvmx_sriox_ip_feature {
897 struct cvmx_sriox_ip_feature_s {
898 #ifdef __BIG_ENDIAN_BITFIELD
900 uint64_t reserved_15_31:17;
904 uint64_t reserved_11_11:1;
914 uint64_t reserved_11_11:1;
918 uint64_t reserved_15_31:17;
922 struct cvmx_sriox_ip_feature_cn63xx {
923 #ifdef __BIG_ENDIAN_BITFIELD
925 uint64_t reserved_14_31:18;
928 uint64_t reserved_11_11:1;
938 uint64_t reserved_11_11:1;
941 uint64_t reserved_14_31:18;
947 union cvmx_sriox_mac_buffers {
949 struct cvmx_sriox_mac_buffers_s {
950 #ifdef __BIG_ENDIAN_BITFIELD
951 uint64_t reserved_56_63:8;
953 uint64_t reserved_44_47:4;
956 uint64_t reserved_24_31:8;
958 uint64_t reserved_12_15:4;
964 uint64_t reserved_12_15:4;
966 uint64_t reserved_24_31:8;
969 uint64_t reserved_44_47:4;
971 uint64_t reserved_56_63:8;
976 union cvmx_sriox_maint_op {
978 struct cvmx_sriox_maint_op_s {
979 #ifdef __BIG_ENDIAN_BITFIELD
981 uint64_t reserved_27_31:5;
991 uint64_t reserved_27_31:5;
997 union cvmx_sriox_maint_rd_data {
999 struct cvmx_sriox_maint_rd_data_s {
1000 #ifdef __BIG_ENDIAN_BITFIELD
1001 uint64_t reserved_33_63:31;
1003 uint64_t rd_data:32;
1005 uint64_t rd_data:32;
1007 uint64_t reserved_33_63:31;
1012 union cvmx_sriox_mce_tx_ctl {
1014 struct cvmx_sriox_mce_tx_ctl_s {
1015 #ifdef __BIG_ENDIAN_BITFIELD
1016 uint64_t reserved_1_63:63;
1020 uint64_t reserved_1_63:63;
1025 union cvmx_sriox_mem_op_ctrl {
1027 struct cvmx_sriox_mem_op_ctrl_s {
1028 #ifdef __BIG_ENDIAN_BITFIELD
1029 uint64_t reserved_10_63:54;
1032 uint64_t reserved_6_7:2;
1042 uint64_t reserved_6_7:2;
1045 uint64_t reserved_10_63:54;
1050 union cvmx_sriox_omsg_ctrlx {
1052 struct cvmx_sriox_omsg_ctrlx_s {
1053 #ifdef __BIG_ENDIAN_BITFIELD
1054 uint64_t testmode:1;
1055 uint64_t reserved_37_62:26;
1056 uint64_t silo_max:5;
1057 uint64_t rtry_thr:16;
1059 uint64_t reserved_11_14:4;
1071 uint64_t reserved_11_14:4;
1073 uint64_t rtry_thr:16;
1074 uint64_t silo_max:5;
1075 uint64_t reserved_37_62:26;
1076 uint64_t testmode:1;
1079 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
1080 #ifdef __BIG_ENDIAN_BITFIELD
1081 uint64_t testmode:1;
1082 uint64_t reserved_32_62:31;
1083 uint64_t rtry_thr:16;
1085 uint64_t reserved_11_14:4;
1097 uint64_t reserved_11_14:4;
1099 uint64_t rtry_thr:16;
1100 uint64_t reserved_32_62:31;
1101 uint64_t testmode:1;
1106 union cvmx_sriox_omsg_done_countsx {
1108 struct cvmx_sriox_omsg_done_countsx_s {
1109 #ifdef __BIG_ENDIAN_BITFIELD
1110 uint64_t reserved_32_63:32;
1116 uint64_t reserved_32_63:32;
1121 union cvmx_sriox_omsg_fmp_mrx {
1123 struct cvmx_sriox_omsg_fmp_mrx_s {
1124 #ifdef __BIG_ENDIAN_BITFIELD
1125 uint64_t reserved_15_63:49;
1127 uint64_t ctlr_fmp:1;
1128 uint64_t ctlr_nmp:1;
1134 uint64_t mbox_fmp:1;
1135 uint64_t mbox_nmp:1;
1136 uint64_t mbox_psd:1;
1146 uint64_t mbox_psd:1;
1147 uint64_t mbox_nmp:1;
1148 uint64_t mbox_fmp:1;
1154 uint64_t ctlr_nmp:1;
1155 uint64_t ctlr_fmp:1;
1157 uint64_t reserved_15_63:49;
1162 union cvmx_sriox_omsg_nmp_mrx {
1164 struct cvmx_sriox_omsg_nmp_mrx_s {
1165 #ifdef __BIG_ENDIAN_BITFIELD
1166 uint64_t reserved_15_63:49;
1168 uint64_t ctlr_fmp:1;
1169 uint64_t ctlr_nmp:1;
1173 uint64_t reserved_8_8:1;
1175 uint64_t mbox_fmp:1;
1176 uint64_t mbox_nmp:1;
1177 uint64_t reserved_4_4:1;
1181 uint64_t reserved_0_0:1;
1183 uint64_t reserved_0_0:1;
1187 uint64_t reserved_4_4:1;
1188 uint64_t mbox_nmp:1;
1189 uint64_t mbox_fmp:1;
1191 uint64_t reserved_8_8:1;
1195 uint64_t ctlr_nmp:1;
1196 uint64_t ctlr_fmp:1;
1198 uint64_t reserved_15_63:49;
1203 union cvmx_sriox_omsg_portx {
1205 struct cvmx_sriox_omsg_portx_s {
1206 #ifdef __BIG_ENDIAN_BITFIELD
1207 uint64_t reserved_32_63:32;
1209 uint64_t reserved_3_30:28;
1213 uint64_t reserved_3_30:28;
1215 uint64_t reserved_32_63:32;
1218 struct cvmx_sriox_omsg_portx_cn63xx {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220 uint64_t reserved_32_63:32;
1222 uint64_t reserved_2_30:29;
1226 uint64_t reserved_2_30:29;
1228 uint64_t reserved_32_63:32;
1233 union cvmx_sriox_omsg_silo_thr {
1235 struct cvmx_sriox_omsg_silo_thr_s {
1236 #ifdef __BIG_ENDIAN_BITFIELD
1237 uint64_t reserved_5_63:59;
1238 uint64_t tot_silo:5;
1240 uint64_t tot_silo:5;
1241 uint64_t reserved_5_63:59;
1246 union cvmx_sriox_omsg_sp_mrx {
1248 struct cvmx_sriox_omsg_sp_mrx_s {
1249 #ifdef __BIG_ENDIAN_BITFIELD
1250 uint64_t reserved_16_63:48;
1251 uint64_t xmbox_sp:1;
1253 uint64_t ctlr_fmp:1;
1254 uint64_t ctlr_nmp:1;
1260 uint64_t mbox_fmp:1;
1261 uint64_t mbox_nmp:1;
1262 uint64_t mbox_psd:1;
1272 uint64_t mbox_psd:1;
1273 uint64_t mbox_nmp:1;
1274 uint64_t mbox_fmp:1;
1280 uint64_t ctlr_nmp:1;
1281 uint64_t ctlr_fmp:1;
1283 uint64_t xmbox_sp:1;
1284 uint64_t reserved_16_63:48;
1289 union cvmx_sriox_priox_in_use {
1291 struct cvmx_sriox_priox_in_use_s {
1292 #ifdef __BIG_ENDIAN_BITFIELD
1293 uint64_t reserved_32_63:32;
1294 uint64_t end_cnt:16;
1295 uint64_t start_cnt:16;
1297 uint64_t start_cnt:16;
1298 uint64_t end_cnt:16;
1299 uint64_t reserved_32_63:32;
1304 union cvmx_sriox_rx_bell {
1306 struct cvmx_sriox_rx_bell_s {
1307 #ifdef __BIG_ENDIAN_BITFIELD
1308 uint64_t reserved_48_63:16;
1312 uint64_t reserved_5_7:3;
1315 uint64_t reserved_2_2:1;
1316 uint64_t priority:2;
1318 uint64_t priority:2;
1319 uint64_t reserved_2_2:1;
1322 uint64_t reserved_5_7:3;
1326 uint64_t reserved_48_63:16;
1331 union cvmx_sriox_rx_bell_seq {
1333 struct cvmx_sriox_rx_bell_seq_s {
1334 #ifdef __BIG_ENDIAN_BITFIELD
1335 uint64_t reserved_40_63:24;
1341 uint64_t reserved_40_63:24;
1346 union cvmx_sriox_rx_status {
1348 struct cvmx_sriox_rx_status_s {
1349 #ifdef __BIG_ENDIAN_BITFIELD
1353 uint64_t reserved_28_39:12;
1356 uint64_t reserved_13_15:3;
1362 uint64_t reserved_13_15:3;
1365 uint64_t reserved_28_39:12;
1373 union cvmx_sriox_s2m_typex {
1375 struct cvmx_sriox_s2m_typex_s {
1376 #ifdef __BIG_ENDIAN_BITFIELD
1377 uint64_t reserved_19_63:45;
1379 uint64_t reserved_15_15:1;
1381 uint64_t wr_prior:2;
1382 uint64_t rd_prior:2;
1383 uint64_t reserved_6_7:2;
1386 uint64_t reserved_2_3:2;
1387 uint64_t iaow_sel:2;
1389 uint64_t iaow_sel:2;
1390 uint64_t reserved_2_3:2;
1393 uint64_t reserved_6_7:2;
1394 uint64_t rd_prior:2;
1395 uint64_t wr_prior:2;
1397 uint64_t reserved_15_15:1;
1399 uint64_t reserved_19_63:45;
1404 union cvmx_sriox_seq {
1406 struct cvmx_sriox_seq_s {
1407 #ifdef __BIG_ENDIAN_BITFIELD
1408 uint64_t reserved_32_63:32;
1412 uint64_t reserved_32_63:32;
1417 union cvmx_sriox_status_reg {
1419 struct cvmx_sriox_status_reg_s {
1420 #ifdef __BIG_ENDIAN_BITFIELD
1421 uint64_t reserved_2_63:62;
1427 uint64_t reserved_2_63:62;
1432 union cvmx_sriox_tag_ctrl {
1434 struct cvmx_sriox_tag_ctrl_s {
1435 #ifdef __BIG_ENDIAN_BITFIELD
1436 uint64_t reserved_17_63:47;
1438 uint64_t reserved_13_15:3;
1440 uint64_t reserved_5_7:3;
1444 uint64_t reserved_5_7:3;
1446 uint64_t reserved_13_15:3;
1448 uint64_t reserved_17_63:47;
1453 union cvmx_sriox_tlp_credits {
1455 struct cvmx_sriox_tlp_credits_s {
1456 #ifdef __BIG_ENDIAN_BITFIELD
1457 uint64_t reserved_28_63:36;
1460 uint64_t reserved_13_15:3;
1466 uint64_t reserved_13_15:3;
1469 uint64_t reserved_28_63:36;
1474 union cvmx_sriox_tx_bell {
1476 struct cvmx_sriox_tx_bell_s {
1477 #ifdef __BIG_ENDIAN_BITFIELD
1478 uint64_t reserved_48_63:16;
1480 uint64_t dest_id:16;
1481 uint64_t reserved_9_15:7;
1483 uint64_t reserved_5_7:3;
1486 uint64_t reserved_2_2:1;
1487 uint64_t priority:2;
1489 uint64_t priority:2;
1490 uint64_t reserved_2_2:1;
1493 uint64_t reserved_5_7:3;
1495 uint64_t reserved_9_15:7;
1496 uint64_t dest_id:16;
1498 uint64_t reserved_48_63:16;
1503 union cvmx_sriox_tx_bell_info {
1505 struct cvmx_sriox_tx_bell_info_s {
1506 #ifdef __BIG_ENDIAN_BITFIELD
1507 uint64_t reserved_48_63:16;
1509 uint64_t dest_id:16;
1510 uint64_t reserved_8_15:8;
1516 uint64_t reserved_2_2:1;
1517 uint64_t priority:2;
1519 uint64_t priority:2;
1520 uint64_t reserved_2_2:1;
1526 uint64_t reserved_8_15:8;
1527 uint64_t dest_id:16;
1529 uint64_t reserved_48_63:16;
1534 union cvmx_sriox_tx_ctrl {
1536 struct cvmx_sriox_tx_ctrl_s {
1537 #ifdef __BIG_ENDIAN_BITFIELD
1538 uint64_t reserved_53_63:11;
1540 uint64_t reserved_45_47:3;
1542 uint64_t reserved_37_39:3;
1544 uint64_t reserved_20_31:12;
1546 uint64_t reserved_12_15:4;
1548 uint64_t reserved_4_7:4;
1552 uint64_t reserved_4_7:4;
1554 uint64_t reserved_12_15:4;
1556 uint64_t reserved_20_31:12;
1558 uint64_t reserved_37_39:3;
1560 uint64_t reserved_45_47:3;
1562 uint64_t reserved_53_63:11;
1567 union cvmx_sriox_tx_emphasis {
1569 struct cvmx_sriox_tx_emphasis_s {
1570 #ifdef __BIG_ENDIAN_BITFIELD
1571 uint64_t reserved_4_63:60;
1575 uint64_t reserved_4_63:60;
1580 union cvmx_sriox_tx_status {
1582 struct cvmx_sriox_tx_status_s {
1583 #ifdef __BIG_ENDIAN_BITFIELD
1584 uint64_t reserved_32_63:32;
1594 uint64_t reserved_32_63:32;
1599 union cvmx_sriox_wr_done_counts {
1601 struct cvmx_sriox_wr_done_counts_s {
1602 #ifdef __BIG_ENDIAN_BITFIELD
1603 uint64_t reserved_32_63:32;
1609 uint64_t reserved_32_63:32;