1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (C) 2003-2018 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_SPXX_DEFS_H__
29 #define __CVMX_SPXX_DEFS_H__
31 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
41 #define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
45 #define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
46 #define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
48 void __cvmx_interrupt_spxx_int_msk_enable(int index);
50 union cvmx_spxx_bckprs_cnt {
52 struct cvmx_spxx_bckprs_cnt_s {
53 #ifdef __BIG_ENDIAN_BITFIELD
54 uint64_t reserved_32_63:32;
58 uint64_t reserved_32_63:32;
63 union cvmx_spxx_bist_stat {
65 struct cvmx_spxx_bist_stat_s {
66 #ifdef __BIG_ENDIAN_BITFIELD
67 uint64_t reserved_3_63:61;
75 uint64_t reserved_3_63:61;
80 union cvmx_spxx_clk_ctl {
82 struct cvmx_spxx_clk_ctl_s {
83 #ifdef __BIG_ENDIAN_BITFIELD
84 uint64_t reserved_17_63:47;
86 uint64_t reserved_12_15:4;
104 uint64_t reserved_12_15:4;
106 uint64_t reserved_17_63:47;
111 union cvmx_spxx_clk_stat {
113 struct cvmx_spxx_clk_stat_s {
114 #ifdef __BIG_ENDIAN_BITFIELD
115 uint64_t reserved_11_63:53;
117 uint64_t reserved_9_9:1;
123 uint64_t reserved_0_3:4;
125 uint64_t reserved_0_3:4;
131 uint64_t reserved_9_9:1;
133 uint64_t reserved_11_63:53;
138 union cvmx_spxx_dbg_deskew_ctl {
140 struct cvmx_spxx_dbg_deskew_ctl_s {
141 #ifdef __BIG_ENDIAN_BITFIELD
142 uint64_t reserved_30_63:34;
145 uint64_t reserved_26_27:2;
148 uint64_t reserved_22_23:2;
168 uint64_t reserved_22_23:2;
171 uint64_t reserved_26_27:2;
174 uint64_t reserved_30_63:34;
179 union cvmx_spxx_dbg_deskew_state {
181 struct cvmx_spxx_dbg_deskew_state_s {
182 #ifdef __BIG_ENDIAN_BITFIELD
183 uint64_t reserved_9_63:55;
193 uint64_t reserved_9_63:55;
198 union cvmx_spxx_drv_ctl {
200 struct cvmx_spxx_drv_ctl_s {
201 #ifdef __BIG_ENDIAN_BITFIELD
202 uint64_t reserved_0_63:64;
204 uint64_t reserved_0_63:64;
207 struct cvmx_spxx_drv_ctl_cn38xx {
208 #ifdef __BIG_ENDIAN_BITFIELD
209 uint64_t reserved_16_63:48;
217 uint64_t reserved_16_63:48;
220 struct cvmx_spxx_drv_ctl_cn58xx {
221 #ifdef __BIG_ENDIAN_BITFIELD
222 uint64_t reserved_24_63:40;
225 uint64_t reserved_10_15:6;
229 uint64_t reserved_10_15:6;
232 uint64_t reserved_24_63:40;
237 union cvmx_spxx_err_ctl {
239 struct cvmx_spxx_err_ctl_s {
240 #ifdef __BIG_ENDIAN_BITFIELD
241 uint64_t reserved_9_63:55;
245 uint64_t reserved_4_5:2;
249 uint64_t reserved_4_5:2;
253 uint64_t reserved_9_63:55;
258 union cvmx_spxx_int_dat {
260 struct cvmx_spxx_int_dat_s {
261 #ifdef __BIG_ENDIAN_BITFIELD
262 uint64_t reserved_32_63:32;
264 uint64_t reserved_14_30:17;
272 uint64_t reserved_14_30:17;
274 uint64_t reserved_32_63:32;
279 union cvmx_spxx_int_msk {
281 struct cvmx_spxx_int_msk_s {
282 #ifdef __BIG_ENDIAN_BITFIELD
283 uint64_t reserved_12_63:52;
292 uint64_t reserved_2_3:2;
298 uint64_t reserved_2_3:2;
307 uint64_t reserved_12_63:52;
312 union cvmx_spxx_int_reg {
314 struct cvmx_spxx_int_reg_s {
315 #ifdef __BIG_ENDIAN_BITFIELD
316 uint64_t reserved_32_63:32;
318 uint64_t reserved_12_30:19;
327 uint64_t reserved_2_3:2;
333 uint64_t reserved_2_3:2;
342 uint64_t reserved_12_30:19;
344 uint64_t reserved_32_63:32;
349 union cvmx_spxx_int_sync {
351 struct cvmx_spxx_int_sync_s {
352 #ifdef __BIG_ENDIAN_BITFIELD
353 uint64_t reserved_12_63:52;
362 uint64_t reserved_2_3:2;
368 uint64_t reserved_2_3:2;
377 uint64_t reserved_12_63:52;
382 union cvmx_spxx_tpa_acc {
384 struct cvmx_spxx_tpa_acc_s {
385 #ifdef __BIG_ENDIAN_BITFIELD
386 uint64_t reserved_32_63:32;
390 uint64_t reserved_32_63:32;
395 union cvmx_spxx_tpa_max {
397 struct cvmx_spxx_tpa_max_s {
398 #ifdef __BIG_ENDIAN_BITFIELD
399 uint64_t reserved_32_63:32;
403 uint64_t reserved_32_63:32;
408 union cvmx_spxx_tpa_sel {
410 struct cvmx_spxx_tpa_sel_s {
411 #ifdef __BIG_ENDIAN_BITFIELD
412 uint64_t reserved_4_63:60;
416 uint64_t reserved_4_63:60;
421 union cvmx_spxx_trn4_ctl {
423 struct cvmx_spxx_trn4_ctl_s {
424 #ifdef __BIG_ENDIAN_BITFIELD
425 uint64_t reserved_13_63:51;
441 uint64_t reserved_13_63:51;