1 /***********************license start***************
4 * Contact: support@cavium.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2014 Cavium Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Inc. for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_RST_DEFS_H__
29 #define __CVMX_RST_DEFS_H__
31 #define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
32 #define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
33 #define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
34 #define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
35 #define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
36 #define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
37 #define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
38 #define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
39 #define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
40 #define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
41 #define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
42 #define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
46 struct cvmx_rst_boot_s {
47 #ifdef __BIG_ENDIAN_BITFIELD
52 uint64_t ckill_ppdis:1;
53 uint64_t jt_tstmode:1;
55 uint64_t reserved_37_56:20;
58 uint64_t reserved_21_23:3;
70 uint64_t reserved_21_23:3;
73 uint64_t reserved_37_56:20;
75 uint64_t jt_tstmode:1;
76 uint64_t ckill_ppdis:1;
83 struct cvmx_rst_boot_s cn70xx;
84 struct cvmx_rst_boot_s cn70xxp1;
85 struct cvmx_rst_boot_s cn78xx;
90 struct cvmx_rst_cfg_s {
91 #ifdef __BIG_ENDIAN_BITFIELD
92 uint64_t bist_delay:58;
93 uint64_t reserved_3_5:3;
94 uint64_t cntl_clr_bist:1;
95 uint64_t warm_clr_bist:1;
96 uint64_t soft_clr_bist:1;
98 uint64_t soft_clr_bist:1;
99 uint64_t warm_clr_bist:1;
100 uint64_t cntl_clr_bist:1;
101 uint64_t reserved_3_5:3;
102 uint64_t bist_delay:58;
105 struct cvmx_rst_cfg_s cn70xx;
106 struct cvmx_rst_cfg_s cn70xxp1;
107 struct cvmx_rst_cfg_s cn78xx;
110 union cvmx_rst_ckill {
112 struct cvmx_rst_ckill_s {
113 #ifdef __BIG_ENDIAN_BITFIELD
114 uint64_t reserved_47_63:17;
118 uint64_t reserved_47_63:17;
121 struct cvmx_rst_ckill_s cn70xx;
122 struct cvmx_rst_ckill_s cn70xxp1;
123 struct cvmx_rst_ckill_s cn78xx;
126 union cvmx_rst_ctlx {
128 struct cvmx_rst_ctlx_s {
129 #ifdef __BIG_ENDIAN_BITFIELD
130 uint64_t reserved_10_63:54;
131 uint64_t prst_link:1;
134 uint64_t host_mode:1;
135 uint64_t reserved_4_5:2;
145 uint64_t reserved_4_5:2;
146 uint64_t host_mode:1;
149 uint64_t prst_link:1;
150 uint64_t reserved_10_63:54;
153 struct cvmx_rst_ctlx_s cn70xx;
154 struct cvmx_rst_ctlx_s cn70xxp1;
155 struct cvmx_rst_ctlx_s cn78xx;
158 union cvmx_rst_delay {
160 struct cvmx_rst_delay_s {
161 #ifdef __BIG_ENDIAN_BITFIELD
162 uint64_t reserved_32_63:32;
163 uint64_t warm_rst_dly:16;
164 uint64_t soft_rst_dly:16;
166 uint64_t soft_rst_dly:16;
167 uint64_t warm_rst_dly:16;
168 uint64_t reserved_32_63:32;
171 struct cvmx_rst_delay_s cn70xx;
172 struct cvmx_rst_delay_s cn70xxp1;
173 struct cvmx_rst_delay_s cn78xx;
178 struct cvmx_rst_eco_s {
179 #ifdef __BIG_ENDIAN_BITFIELD
180 uint64_t reserved_32_63:32;
184 uint64_t reserved_32_63:32;
187 struct cvmx_rst_eco_s cn78xx;
192 struct cvmx_rst_int_s {
193 #ifdef __BIG_ENDIAN_BITFIELD
194 uint64_t reserved_12_63:52;
196 uint64_t reserved_4_7:4;
200 uint64_t reserved_4_7:4;
202 uint64_t reserved_12_63:52;
205 struct cvmx_rst_int_cn70xx {
206 #ifdef __BIG_ENDIAN_BITFIELD
207 uint64_t reserved_11_63:53;
209 uint64_t reserved_3_7:5;
213 uint64_t reserved_3_7:5;
215 uint64_t reserved_11_63:53;
218 struct cvmx_rst_int_cn70xx cn70xxp1;
219 struct cvmx_rst_int_s cn78xx;
224 struct cvmx_rst_ocx_s {
225 #ifdef __BIG_ENDIAN_BITFIELD
226 uint64_t reserved_3_63:61;
230 uint64_t reserved_3_63:61;
233 struct cvmx_rst_ocx_s cn78xx;
236 union cvmx_rst_power_dbg {
238 struct cvmx_rst_power_dbg_s {
239 #ifdef __BIG_ENDIAN_BITFIELD
240 uint64_t reserved_3_63:61;
244 uint64_t reserved_3_63:61;
247 struct cvmx_rst_power_dbg_s cn78xx;
250 union cvmx_rst_pp_power {
252 struct cvmx_rst_pp_power_s {
253 #ifdef __BIG_ENDIAN_BITFIELD
254 uint64_t reserved_48_63:16;
258 uint64_t reserved_48_63:16;
261 struct cvmx_rst_pp_power_cn70xx {
262 #ifdef __BIG_ENDIAN_BITFIELD
263 uint64_t reserved_4_63:60;
267 uint64_t reserved_4_63:60;
270 struct cvmx_rst_pp_power_cn70xx cn70xxp1;
271 struct cvmx_rst_pp_power_s cn78xx;
274 union cvmx_rst_soft_prstx {
276 struct cvmx_rst_soft_prstx_s {
277 #ifdef __BIG_ENDIAN_BITFIELD
278 uint64_t reserved_1_63:63;
279 uint64_t soft_prst:1;
281 uint64_t soft_prst:1;
282 uint64_t reserved_1_63:63;
285 struct cvmx_rst_soft_prstx_s cn70xx;
286 struct cvmx_rst_soft_prstx_s cn70xxp1;
287 struct cvmx_rst_soft_prstx_s cn78xx;
290 union cvmx_rst_soft_rst {
292 struct cvmx_rst_soft_rst_s {
293 #ifdef __BIG_ENDIAN_BITFIELD
294 uint64_t reserved_1_63:63;
298 uint64_t reserved_1_63:63;
301 struct cvmx_rst_soft_rst_s cn70xx;
302 struct cvmx_rst_soft_rst_s cn70xxp1;
303 struct cvmx_rst_soft_rst_s cn78xx;