1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_PEMX_DEFS_H__
29 #define __CVMX_PEMX_DEFS_H__
31 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
32 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
33 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
34 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
35 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
36 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
37 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
38 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
39 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
40 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
41 #define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
42 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
43 #define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
44 #define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
45 #define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
46 #define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
47 #define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
48 #define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
49 #define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
50 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
51 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
52 #define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
54 union cvmx_pemx_bar1_indexx {
56 struct cvmx_pemx_bar1_indexx_s {
57 #ifdef __BIG_ENDIAN_BITFIELD
58 uint64_t reserved_20_63:44;
68 uint64_t reserved_20_63:44;
73 union cvmx_pemx_bar2_mask {
75 struct cvmx_pemx_bar2_mask_s {
76 #ifdef __BIG_ENDIAN_BITFIELD
77 uint64_t reserved_38_63:26;
79 uint64_t reserved_0_2:3;
81 uint64_t reserved_0_2:3;
83 uint64_t reserved_38_63:26;
88 union cvmx_pemx_bar_ctl {
90 struct cvmx_pemx_bar_ctl_s {
91 #ifdef __BIG_ENDIAN_BITFIELD
92 uint64_t reserved_7_63:57;
102 uint64_t reserved_7_63:57;
107 union cvmx_pemx_bist_status {
109 struct cvmx_pemx_bist_status_s {
110 #ifdef __BIG_ENDIAN_BITFIELD
111 uint64_t reserved_8_63:56;
129 uint64_t reserved_8_63:56;
134 union cvmx_pemx_bist_status2 {
136 struct cvmx_pemx_bist_status2_s {
137 #ifdef __BIG_ENDIAN_BITFIELD
138 uint64_t reserved_10_63:54;
160 uint64_t reserved_10_63:54;
165 union cvmx_pemx_cfg_rd {
167 struct cvmx_pemx_cfg_rd_s {
168 #ifdef __BIG_ENDIAN_BITFIELD
178 union cvmx_pemx_cfg_wr {
180 struct cvmx_pemx_cfg_wr_s {
181 #ifdef __BIG_ENDIAN_BITFIELD
191 union cvmx_pemx_cpl_lut_valid {
193 struct cvmx_pemx_cpl_lut_valid_s {
194 #ifdef __BIG_ENDIAN_BITFIELD
195 uint64_t reserved_32_63:32;
199 uint64_t reserved_32_63:32;
204 union cvmx_pemx_ctl_status {
206 struct cvmx_pemx_ctl_status_s {
207 #ifdef __BIG_ENDIAN_BITFIELD
208 uint64_t reserved_48_63:16;
212 uint64_t reserved_32_33:2;
213 uint64_t cfg_rtry:16;
214 uint64_t reserved_12_15:4;
218 uint64_t reserved_7_8:2;
234 uint64_t reserved_7_8:2;
238 uint64_t reserved_12_15:4;
239 uint64_t cfg_rtry:16;
240 uint64_t reserved_32_33:2;
244 uint64_t reserved_48_63:16;
249 union cvmx_pemx_dbg_info {
251 struct cvmx_pemx_dbg_info_s {
252 #ifdef __BIG_ENDIAN_BITFIELD
253 uint64_t reserved_31_63:33;
317 uint64_t reserved_31_63:33;
322 union cvmx_pemx_dbg_info_en {
324 struct cvmx_pemx_dbg_info_en_s {
325 #ifdef __BIG_ENDIAN_BITFIELD
326 uint64_t reserved_31_63:33;
390 uint64_t reserved_31_63:33;
395 union cvmx_pemx_diag_status {
397 struct cvmx_pemx_diag_status_s {
398 #ifdef __BIG_ENDIAN_BITFIELD
399 uint64_t reserved_4_63:60;
409 uint64_t reserved_4_63:60;
414 union cvmx_pemx_inb_read_credits {
416 struct cvmx_pemx_inb_read_credits_s {
417 #ifdef __BIG_ENDIAN_BITFIELD
418 uint64_t reserved_6_63:58;
422 uint64_t reserved_6_63:58;
427 union cvmx_pemx_int_enb {
429 struct cvmx_pemx_int_enb_s {
430 #ifdef __BIG_ENDIAN_BITFIELD
431 uint64_t reserved_14_63:50;
461 uint64_t reserved_14_63:50;
466 union cvmx_pemx_int_enb_int {
468 struct cvmx_pemx_int_enb_int_s {
469 #ifdef __BIG_ENDIAN_BITFIELD
470 uint64_t reserved_14_63:50;
500 uint64_t reserved_14_63:50;
505 union cvmx_pemx_int_sum {
507 struct cvmx_pemx_int_sum_s {
508 #ifdef __BIG_ENDIAN_BITFIELD
509 uint64_t reserved_14_63:50;
539 uint64_t reserved_14_63:50;
544 union cvmx_pemx_p2n_bar0_start {
546 struct cvmx_pemx_p2n_bar0_start_s {
547 #ifdef __BIG_ENDIAN_BITFIELD
549 uint64_t reserved_0_13:14;
551 uint64_t reserved_0_13:14;
557 union cvmx_pemx_p2n_bar1_start {
559 struct cvmx_pemx_p2n_bar1_start_s {
560 #ifdef __BIG_ENDIAN_BITFIELD
562 uint64_t reserved_0_25:26;
564 uint64_t reserved_0_25:26;
570 union cvmx_pemx_p2n_bar2_start {
572 struct cvmx_pemx_p2n_bar2_start_s {
573 #ifdef __BIG_ENDIAN_BITFIELD
575 uint64_t reserved_0_40:41;
577 uint64_t reserved_0_40:41;
583 union cvmx_pemx_p2p_barx_end {
585 struct cvmx_pemx_p2p_barx_end_s {
586 #ifdef __BIG_ENDIAN_BITFIELD
588 uint64_t reserved_0_11:12;
590 uint64_t reserved_0_11:12;
596 union cvmx_pemx_p2p_barx_start {
598 struct cvmx_pemx_p2p_barx_start_s {
599 #ifdef __BIG_ENDIAN_BITFIELD
601 uint64_t reserved_0_11:12;
603 uint64_t reserved_0_11:12;
609 union cvmx_pemx_tlp_credits {
611 struct cvmx_pemx_tlp_credits_s {
612 #ifdef __BIG_ENDIAN_BITFIELD
613 uint64_t reserved_56_63:8;
629 uint64_t reserved_56_63:8;
632 struct cvmx_pemx_tlp_credits_cn61xx {
633 #ifdef __BIG_ENDIAN_BITFIELD
634 uint64_t reserved_56_63:8;
636 uint64_t reserved_24_47:24;
644 uint64_t reserved_24_47:24;
646 uint64_t reserved_56_63:8;