1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (C) 2003-2018 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_PCSX_DEFS_H__
29 #define __CVMX_PCSX_DEFS_H__
31 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
35 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
36 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
37 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
38 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
39 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
40 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
42 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
43 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
44 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
46 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
49 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
51 switch (cvmx_get_octeon_family()) {
52 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
53 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
54 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
55 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
56 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
57 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
58 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
59 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
60 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
61 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
64 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
67 static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
69 switch (cvmx_get_octeon_family()) {
70 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
71 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
72 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
73 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
75 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
76 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
77 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
78 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
79 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
80 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
82 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
85 static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
87 switch (cvmx_get_octeon_family()) {
88 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
89 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
90 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
91 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
92 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
93 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
94 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
95 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
96 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
97 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
98 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
100 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
103 static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
105 switch (cvmx_get_octeon_family()) {
106 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
107 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
108 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
109 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
110 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
111 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
112 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
113 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
114 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
115 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
116 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
118 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
121 static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
123 switch (cvmx_get_octeon_family()) {
124 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
125 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
126 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
127 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
128 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
129 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
130 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
131 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
132 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
133 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
134 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
136 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
139 static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
141 switch (cvmx_get_octeon_family()) {
142 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
143 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
144 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
145 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
146 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
147 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
148 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
149 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
150 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
151 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
152 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
154 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
157 static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
159 switch (cvmx_get_octeon_family()) {
160 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
161 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
162 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
163 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
164 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
165 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
166 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
167 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
168 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
169 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
170 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
172 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
175 static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
177 switch (cvmx_get_octeon_family()) {
178 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
179 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
180 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
181 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
182 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
183 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
184 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
185 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
186 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
187 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
188 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
190 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
193 static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
195 switch (cvmx_get_octeon_family()) {
196 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
197 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
198 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
199 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
200 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
201 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
202 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
203 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
204 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
205 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
206 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
208 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
211 static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
213 switch (cvmx_get_octeon_family()) {
214 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
215 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
216 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
217 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
218 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
219 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
220 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
221 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
222 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
223 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
224 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
226 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
229 static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
231 switch (cvmx_get_octeon_family()) {
232 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
233 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
234 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
235 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
236 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
237 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
238 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
239 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
240 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
241 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
242 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
244 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
247 static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
249 switch (cvmx_get_octeon_family()) {
250 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
251 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
252 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
253 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
254 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
255 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
256 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
257 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
258 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
259 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
260 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
262 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
265 static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
267 switch (cvmx_get_octeon_family()) {
268 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
269 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
270 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
271 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
272 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
273 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
274 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
275 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
276 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
277 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
278 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
280 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
283 static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
285 switch (cvmx_get_octeon_family()) {
286 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
287 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
288 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
289 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
290 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
291 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
292 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
293 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
294 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
295 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
296 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
298 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
301 static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
303 switch (cvmx_get_octeon_family()) {
304 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
305 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
306 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
307 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
308 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
309 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
310 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
311 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
312 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
313 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
314 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
316 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
319 static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
321 switch (cvmx_get_octeon_family()) {
322 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
323 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
324 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
325 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
326 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
327 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
328 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
329 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
330 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
331 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
332 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
334 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
337 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
339 union cvmx_pcsx_anx_adv_reg {
341 struct cvmx_pcsx_anx_adv_reg_s {
342 #ifdef __BIG_ENDIAN_BITFIELD
343 uint64_t reserved_16_63:48;
345 uint64_t reserved_14_14:1;
347 uint64_t reserved_9_11:3;
351 uint64_t reserved_0_4:5;
353 uint64_t reserved_0_4:5;
357 uint64_t reserved_9_11:3;
359 uint64_t reserved_14_14:1;
361 uint64_t reserved_16_63:48;
366 union cvmx_pcsx_anx_ext_st_reg {
368 struct cvmx_pcsx_anx_ext_st_reg_s {
369 #ifdef __BIG_ENDIAN_BITFIELD
370 uint64_t reserved_16_63:48;
375 uint64_t reserved_0_11:12;
377 uint64_t reserved_0_11:12;
382 uint64_t reserved_16_63:48;
387 union cvmx_pcsx_anx_lp_abil_reg {
389 struct cvmx_pcsx_anx_lp_abil_reg_s {
390 #ifdef __BIG_ENDIAN_BITFIELD
391 uint64_t reserved_16_63:48;
395 uint64_t reserved_9_11:3;
399 uint64_t reserved_0_4:5;
401 uint64_t reserved_0_4:5;
405 uint64_t reserved_9_11:3;
409 uint64_t reserved_16_63:48;
414 union cvmx_pcsx_anx_results_reg {
416 struct cvmx_pcsx_anx_results_reg_s {
417 #ifdef __BIG_ENDIAN_BITFIELD
418 uint64_t reserved_7_63:57;
430 uint64_t reserved_7_63:57;
435 union cvmx_pcsx_intx_en_reg {
437 struct cvmx_pcsx_intx_en_reg_s {
438 #ifdef __BIG_ENDIAN_BITFIELD
439 uint64_t reserved_13_63:51;
440 uint64_t dbg_sync_en:1;
442 uint64_t sync_bad_en:1;
443 uint64_t an_bad_en:1;
444 uint64_t rxlock_en:1;
448 uint64_t txfifo_en:1;
449 uint64_t txfifu_en:1;
450 uint64_t an_err_en:1;
452 uint64_t lnkspd_en:1;
454 uint64_t lnkspd_en:1;
456 uint64_t an_err_en:1;
457 uint64_t txfifu_en:1;
458 uint64_t txfifo_en:1;
462 uint64_t rxlock_en:1;
463 uint64_t an_bad_en:1;
464 uint64_t sync_bad_en:1;
466 uint64_t dbg_sync_en:1;
467 uint64_t reserved_13_63:51;
470 struct cvmx_pcsx_intx_en_reg_cn52xx {
471 #ifdef __BIG_ENDIAN_BITFIELD
472 uint64_t reserved_12_63:52;
474 uint64_t sync_bad_en:1;
475 uint64_t an_bad_en:1;
476 uint64_t rxlock_en:1;
480 uint64_t txfifo_en:1;
481 uint64_t txfifu_en:1;
482 uint64_t an_err_en:1;
484 uint64_t lnkspd_en:1;
486 uint64_t lnkspd_en:1;
488 uint64_t an_err_en:1;
489 uint64_t txfifu_en:1;
490 uint64_t txfifo_en:1;
494 uint64_t rxlock_en:1;
495 uint64_t an_bad_en:1;
496 uint64_t sync_bad_en:1;
498 uint64_t reserved_12_63:52;
503 union cvmx_pcsx_intx_reg {
505 struct cvmx_pcsx_intx_reg_s {
506 #ifdef __BIG_ENDIAN_BITFIELD
507 uint64_t reserved_13_63:51;
535 uint64_t reserved_13_63:51;
538 struct cvmx_pcsx_intx_reg_cn52xx {
539 #ifdef __BIG_ENDIAN_BITFIELD
540 uint64_t reserved_12_63:52;
566 uint64_t reserved_12_63:52;
571 union cvmx_pcsx_linkx_timer_count_reg {
573 struct cvmx_pcsx_linkx_timer_count_reg_s {
574 #ifdef __BIG_ENDIAN_BITFIELD
575 uint64_t reserved_16_63:48;
579 uint64_t reserved_16_63:48;
584 union cvmx_pcsx_log_anlx_reg {
586 struct cvmx_pcsx_log_anlx_reg_s {
587 #ifdef __BIG_ENDIAN_BITFIELD
588 uint64_t reserved_4_63:60;
589 uint64_t lafifovfl:1;
595 uint64_t lafifovfl:1;
596 uint64_t reserved_4_63:60;
601 union cvmx_pcsx_miscx_ctl_reg {
603 struct cvmx_pcsx_miscx_ctl_reg_s {
604 #ifdef __BIG_ENDIAN_BITFIELD
605 uint64_t reserved_13_63:51;
621 uint64_t reserved_13_63:51;
626 union cvmx_pcsx_mrx_control_reg {
628 struct cvmx_pcsx_mrx_control_reg_s {
629 #ifdef __BIG_ENDIAN_BITFIELD
630 uint64_t reserved_16_63:48;
636 uint64_t reserved_10_10:1;
642 uint64_t reserved_0_4:5;
644 uint64_t reserved_0_4:5;
650 uint64_t reserved_10_10:1;
656 uint64_t reserved_16_63:48;
661 union cvmx_pcsx_mrx_status_reg {
663 struct cvmx_pcsx_mrx_status_reg_s {
664 #ifdef __BIG_ENDIAN_BITFIELD
665 uint64_t reserved_16_63:48;
674 uint64_t reserved_7_7:1;
680 uint64_t reserved_1_1:1;
684 uint64_t reserved_1_1:1;
690 uint64_t reserved_7_7:1;
699 uint64_t reserved_16_63:48;
704 union cvmx_pcsx_rxx_states_reg {
706 struct cvmx_pcsx_rxx_states_reg_s {
707 #ifdef __BIG_ENDIAN_BITFIELD
708 uint64_t reserved_16_63:48;
722 uint64_t reserved_16_63:48;
727 union cvmx_pcsx_rxx_sync_reg {
729 struct cvmx_pcsx_rxx_sync_reg_s {
730 #ifdef __BIG_ENDIAN_BITFIELD
731 uint64_t reserved_2_63:62;
737 uint64_t reserved_2_63:62;
742 union cvmx_pcsx_sgmx_an_adv_reg {
744 struct cvmx_pcsx_sgmx_an_adv_reg_s {
745 #ifdef __BIG_ENDIAN_BITFIELD
746 uint64_t reserved_16_63:48;
749 uint64_t reserved_13_13:1;
752 uint64_t reserved_1_9:9;
756 uint64_t reserved_1_9:9;
759 uint64_t reserved_13_13:1;
762 uint64_t reserved_16_63:48;
767 union cvmx_pcsx_sgmx_lp_adv_reg {
769 struct cvmx_pcsx_sgmx_lp_adv_reg_s {
770 #ifdef __BIG_ENDIAN_BITFIELD
771 uint64_t reserved_16_63:48;
773 uint64_t reserved_13_14:2;
776 uint64_t reserved_1_9:9;
780 uint64_t reserved_1_9:9;
783 uint64_t reserved_13_14:2;
785 uint64_t reserved_16_63:48;
790 union cvmx_pcsx_txx_states_reg {
792 struct cvmx_pcsx_txx_states_reg_s {
793 #ifdef __BIG_ENDIAN_BITFIELD
794 uint64_t reserved_7_63:57;
802 uint64_t reserved_7_63:57;
807 union cvmx_pcsx_tx_rxx_polarity_reg {
809 struct cvmx_pcsx_tx_rxx_polarity_reg_s {
810 #ifdef __BIG_ENDIAN_BITFIELD
811 uint64_t reserved_4_63:60;
821 uint64_t reserved_4_63:60;