1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_PCI_DEFS_H__
29 #define __CVMX_PCI_DEFS_H__
31 #define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
32 #define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
33 #define CVMX_PCI_CFG00 (0x0000000000000000ull)
34 #define CVMX_PCI_CFG01 (0x0000000000000004ull)
35 #define CVMX_PCI_CFG02 (0x0000000000000008ull)
36 #define CVMX_PCI_CFG03 (0x000000000000000Cull)
37 #define CVMX_PCI_CFG04 (0x0000000000000010ull)
38 #define CVMX_PCI_CFG05 (0x0000000000000014ull)
39 #define CVMX_PCI_CFG06 (0x0000000000000018ull)
40 #define CVMX_PCI_CFG07 (0x000000000000001Cull)
41 #define CVMX_PCI_CFG08 (0x0000000000000020ull)
42 #define CVMX_PCI_CFG09 (0x0000000000000024ull)
43 #define CVMX_PCI_CFG10 (0x0000000000000028ull)
44 #define CVMX_PCI_CFG11 (0x000000000000002Cull)
45 #define CVMX_PCI_CFG12 (0x0000000000000030ull)
46 #define CVMX_PCI_CFG13 (0x0000000000000034ull)
47 #define CVMX_PCI_CFG15 (0x000000000000003Cull)
48 #define CVMX_PCI_CFG16 (0x0000000000000040ull)
49 #define CVMX_PCI_CFG17 (0x0000000000000044ull)
50 #define CVMX_PCI_CFG18 (0x0000000000000048ull)
51 #define CVMX_PCI_CFG19 (0x000000000000004Cull)
52 #define CVMX_PCI_CFG20 (0x0000000000000050ull)
53 #define CVMX_PCI_CFG21 (0x0000000000000054ull)
54 #define CVMX_PCI_CFG22 (0x0000000000000058ull)
55 #define CVMX_PCI_CFG56 (0x00000000000000E0ull)
56 #define CVMX_PCI_CFG57 (0x00000000000000E4ull)
57 #define CVMX_PCI_CFG58 (0x00000000000000E8ull)
58 #define CVMX_PCI_CFG59 (0x00000000000000ECull)
59 #define CVMX_PCI_CFG60 (0x00000000000000F0ull)
60 #define CVMX_PCI_CFG61 (0x00000000000000F4ull)
61 #define CVMX_PCI_CFG62 (0x00000000000000F8ull)
62 #define CVMX_PCI_CFG63 (0x00000000000000FCull)
63 #define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
64 #define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
65 #define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
66 #define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
67 #define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
68 #define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
69 #define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
70 #define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
71 #define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
72 #define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
73 #define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
74 #define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
75 #define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
76 #define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
77 #define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
78 #define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
79 #define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
80 #define CVMX_PCI_INT_ENB (0x0000000000000038ull)
81 #define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
82 #define CVMX_PCI_INT_SUM (0x0000000000000030ull)
83 #define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
84 #define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
85 #define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
86 #define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
87 #define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
88 #define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
89 #define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
90 #define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
91 #define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
92 #define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
93 #define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
94 #define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
95 #define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
96 #define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
97 #define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
98 #define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
99 #define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
100 #define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
101 #define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
102 #define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
103 #define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
104 #define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
105 #define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
106 #define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
107 #define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
108 #define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
109 #define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
110 #define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
111 #define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
112 #define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
113 #define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
114 #define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
115 #define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
117 union cvmx_pci_bar1_indexx {
119 struct cvmx_pci_bar1_indexx_s {
120 #ifdef __BIG_ENDIAN_BITFIELD
121 uint32_t reserved_18_31:14;
122 uint32_t addr_idx:14;
130 uint32_t addr_idx:14;
131 uint32_t reserved_18_31:14;
136 union cvmx_pci_bist_reg {
138 struct cvmx_pci_bist_reg_s {
139 #ifdef __BIG_ENDIAN_BITFIELD
140 uint64_t reserved_10_63:54;
162 uint64_t reserved_10_63:54;
167 union cvmx_pci_cfg00 {
169 struct cvmx_pci_cfg00_s {
170 #ifdef __BIG_ENDIAN_BITFIELD
180 union cvmx_pci_cfg01 {
182 struct cvmx_pci_cfg01_s {
183 #ifdef __BIG_ENDIAN_BITFIELD
192 uint32_t reserved_22_22:1;
196 uint32_t reserved_11_18:8;
220 uint32_t reserved_11_18:8;
224 uint32_t reserved_22_22:1;
237 union cvmx_pci_cfg02 {
239 struct cvmx_pci_cfg02_s {
240 #ifdef __BIG_ENDIAN_BITFIELD
250 union cvmx_pci_cfg03 {
252 struct cvmx_pci_cfg03_s {
253 #ifdef __BIG_ENDIAN_BITFIELD
256 uint32_t reserved_28_29:2;
266 uint32_t reserved_28_29:2;
273 union cvmx_pci_cfg04 {
275 struct cvmx_pci_cfg04_s {
276 #ifdef __BIG_ENDIAN_BITFIELD
292 union cvmx_pci_cfg05 {
294 struct cvmx_pci_cfg05_s {
295 #ifdef __BIG_ENDIAN_BITFIELD
303 union cvmx_pci_cfg06 {
305 struct cvmx_pci_cfg06_s {
306 #ifdef __BIG_ENDIAN_BITFIELD
322 union cvmx_pci_cfg07 {
324 struct cvmx_pci_cfg07_s {
325 #ifdef __BIG_ENDIAN_BITFIELD
333 union cvmx_pci_cfg08 {
335 struct cvmx_pci_cfg08_s {
336 #ifdef __BIG_ENDIAN_BITFIELD
350 union cvmx_pci_cfg09 {
352 struct cvmx_pci_cfg09_s {
353 #ifdef __BIG_ENDIAN_BITFIELD
363 union cvmx_pci_cfg10 {
365 struct cvmx_pci_cfg10_s {
366 #ifdef __BIG_ENDIAN_BITFIELD
374 union cvmx_pci_cfg11 {
376 struct cvmx_pci_cfg11_s {
377 #ifdef __BIG_ENDIAN_BITFIELD
387 union cvmx_pci_cfg12 {
389 struct cvmx_pci_cfg12_s {
390 #ifdef __BIG_ENDIAN_BITFIELD
393 uint32_t reserved_1_10:10;
397 uint32_t reserved_1_10:10;
404 union cvmx_pci_cfg13 {
406 struct cvmx_pci_cfg13_s {
407 #ifdef __BIG_ENDIAN_BITFIELD
408 uint32_t reserved_8_31:24;
412 uint32_t reserved_8_31:24;
417 union cvmx_pci_cfg15 {
419 struct cvmx_pci_cfg15_s {
420 #ifdef __BIG_ENDIAN_BITFIELD
434 union cvmx_pci_cfg16 {
436 struct cvmx_pci_cfg16_s {
437 #ifdef __BIG_ENDIAN_BITFIELD
451 uint32_t reserved_2_2:1;
457 uint32_t reserved_2_2:1;
475 union cvmx_pci_cfg17 {
477 struct cvmx_pci_cfg17_s {
478 #ifdef __BIG_ENDIAN_BITFIELD
486 union cvmx_pci_cfg18 {
488 struct cvmx_pci_cfg18_s {
489 #ifdef __BIG_ENDIAN_BITFIELD
497 union cvmx_pci_cfg19 {
499 struct cvmx_pci_cfg19_s {
500 #ifdef __BIG_ENDIAN_BITFIELD
513 uint32_t reserved_9_10:2;
516 uint32_t reserved_6_6:1;
522 uint32_t reserved_6_6:1;
525 uint32_t reserved_9_10:2;
542 union cvmx_pci_cfg20 {
544 struct cvmx_pci_cfg20_s {
545 #ifdef __BIG_ENDIAN_BITFIELD
553 union cvmx_pci_cfg21 {
555 struct cvmx_pci_cfg21_s {
556 #ifdef __BIG_ENDIAN_BITFIELD
564 union cvmx_pci_cfg22 {
566 struct cvmx_pci_cfg22_s {
567 #ifdef __BIG_ENDIAN_BITFIELD
569 uint32_t reserved_19_24:6;
581 uint32_t reserved_19_24:6;
587 union cvmx_pci_cfg56 {
589 struct cvmx_pci_cfg56_s {
590 #ifdef __BIG_ENDIAN_BITFIELD
591 uint32_t reserved_23_31:9;
605 uint32_t reserved_23_31:9;
610 union cvmx_pci_cfg57 {
612 struct cvmx_pci_cfg57_s {
613 #ifdef __BIG_ENDIAN_BITFIELD
614 uint32_t reserved_30_31:2;
640 uint32_t reserved_30_31:2;
645 union cvmx_pci_cfg58 {
647 struct cvmx_pci_cfg58_s {
648 #ifdef __BIG_ENDIAN_BITFIELD
654 uint32_t reserved_20_20:1;
664 uint32_t reserved_20_20:1;
674 union cvmx_pci_cfg59 {
676 struct cvmx_pci_cfg59_s {
677 #ifdef __BIG_ENDIAN_BITFIELD
681 uint32_t reserved_16_21:6;
686 uint32_t reserved_2_7:6;
690 uint32_t reserved_2_7:6;
695 uint32_t reserved_16_21:6;
703 union cvmx_pci_cfg60 {
705 struct cvmx_pci_cfg60_s {
706 #ifdef __BIG_ENDIAN_BITFIELD
707 uint32_t reserved_24_31:8;
721 uint32_t reserved_24_31:8;
726 union cvmx_pci_cfg61 {
728 struct cvmx_pci_cfg61_s {
729 #ifdef __BIG_ENDIAN_BITFIELD
731 uint32_t reserved_0_1:2;
733 uint32_t reserved_0_1:2;
739 union cvmx_pci_cfg62 {
741 struct cvmx_pci_cfg62_s {
742 #ifdef __BIG_ENDIAN_BITFIELD
750 union cvmx_pci_cfg63 {
752 struct cvmx_pci_cfg63_s {
753 #ifdef __BIG_ENDIAN_BITFIELD
754 uint32_t reserved_16_31:16;
758 uint32_t reserved_16_31:16;
763 union cvmx_pci_cnt_reg {
765 struct cvmx_pci_cnt_reg_s {
766 #ifdef __BIG_ENDIAN_BITFIELD
767 uint64_t reserved_38_63:26;
779 uint64_t reserved_38_63:26;
784 union cvmx_pci_ctl_status_2 {
786 struct cvmx_pci_ctl_status_2_s {
787 #ifdef __BIG_ENDIAN_BITFIELD
788 uint32_t reserved_29_31:3;
800 uint32_t reserved_14_14:1;
820 uint32_t reserved_14_14:1;
832 uint32_t reserved_29_31:3;
835 struct cvmx_pci_ctl_status_2_cn31xx {
836 #ifdef __BIG_ENDIAN_BITFIELD
837 uint32_t reserved_20_31:12;
843 uint32_t reserved_14_14:1;
863 uint32_t reserved_14_14:1;
869 uint32_t reserved_20_31:12;
874 union cvmx_pci_dbellx {
876 struct cvmx_pci_dbellx_s {
877 #ifdef __BIG_ENDIAN_BITFIELD
878 uint32_t reserved_16_31:16;
882 uint32_t reserved_16_31:16;
887 union cvmx_pci_dma_cntx {
889 struct cvmx_pci_dma_cntx_s {
890 #ifdef __BIG_ENDIAN_BITFIELD
898 union cvmx_pci_dma_int_levx {
900 struct cvmx_pci_dma_int_levx_s {
901 #ifdef __BIG_ENDIAN_BITFIELD
909 union cvmx_pci_dma_timex {
911 struct cvmx_pci_dma_timex_s {
912 #ifdef __BIG_ENDIAN_BITFIELD
913 uint32_t dma_time:32;
915 uint32_t dma_time:32;
920 union cvmx_pci_instr_countx {
922 struct cvmx_pci_instr_countx_s {
923 #ifdef __BIG_ENDIAN_BITFIELD
931 union cvmx_pci_int_enb {
933 struct cvmx_pci_int_enb_s {
934 #ifdef __BIG_ENDIAN_BITFIELD
935 uint64_t reserved_34_63:30;
961 uint64_t imsi_mabt:1;
962 uint64_t imsi_tabt:1;
978 uint64_t imsi_tabt:1;
979 uint64_t imsi_mabt:1;
1005 uint64_t reserved_34_63:30;
1008 struct cvmx_pci_int_enb_cn30xx {
1009 #ifdef __BIG_ENDIAN_BITFIELD
1010 uint64_t reserved_34_63:30;
1020 uint64_t reserved_22_24:3;
1022 uint64_t reserved_18_20:3;
1024 uint64_t irsl_int:1;
1030 uint64_t itsr_abt:1;
1031 uint64_t imsc_msg:1;
1032 uint64_t imsi_mabt:1;
1033 uint64_t imsi_tabt:1;
1034 uint64_t imsi_per:1;
1038 uint64_t imr_wtto:1;
1039 uint64_t imr_wabt:1;
1040 uint64_t itr_wabt:1;
1042 uint64_t itr_wabt:1;
1043 uint64_t imr_wabt:1;
1044 uint64_t imr_wtto:1;
1048 uint64_t imsi_per:1;
1049 uint64_t imsi_tabt:1;
1050 uint64_t imsi_mabt:1;
1051 uint64_t imsc_msg:1;
1052 uint64_t itsr_abt:1;
1058 uint64_t irsl_int:1;
1060 uint64_t reserved_18_20:3;
1062 uint64_t reserved_22_24:3;
1072 uint64_t reserved_34_63:30;
1075 struct cvmx_pci_int_enb_cn31xx {
1076 #ifdef __BIG_ENDIAN_BITFIELD
1077 uint64_t reserved_34_63:30;
1087 uint64_t reserved_23_24:2;
1090 uint64_t reserved_19_20:2;
1093 uint64_t irsl_int:1;
1099 uint64_t itsr_abt:1;
1100 uint64_t imsc_msg:1;
1101 uint64_t imsi_mabt:1;
1102 uint64_t imsi_tabt:1;
1103 uint64_t imsi_per:1;
1107 uint64_t imr_wtto:1;
1108 uint64_t imr_wabt:1;
1109 uint64_t itr_wabt:1;
1111 uint64_t itr_wabt:1;
1112 uint64_t imr_wabt:1;
1113 uint64_t imr_wtto:1;
1117 uint64_t imsi_per:1;
1118 uint64_t imsi_tabt:1;
1119 uint64_t imsi_mabt:1;
1120 uint64_t imsc_msg:1;
1121 uint64_t itsr_abt:1;
1127 uint64_t irsl_int:1;
1130 uint64_t reserved_19_20:2;
1133 uint64_t reserved_23_24:2;
1143 uint64_t reserved_34_63:30;
1148 union cvmx_pci_int_enb2 {
1150 struct cvmx_pci_int_enb2_s {
1151 #ifdef __BIG_ENDIAN_BITFIELD
1152 uint64_t reserved_34_63:30;
1170 uint64_t rrsl_int:1;
1176 uint64_t rtsr_abt:1;
1177 uint64_t rmsc_msg:1;
1178 uint64_t rmsi_mabt:1;
1179 uint64_t rmsi_tabt:1;
1180 uint64_t rmsi_per:1;
1184 uint64_t rmr_wtto:1;
1185 uint64_t rmr_wabt:1;
1186 uint64_t rtr_wabt:1;
1188 uint64_t rtr_wabt:1;
1189 uint64_t rmr_wabt:1;
1190 uint64_t rmr_wtto:1;
1194 uint64_t rmsi_per:1;
1195 uint64_t rmsi_tabt:1;
1196 uint64_t rmsi_mabt:1;
1197 uint64_t rmsc_msg:1;
1198 uint64_t rtsr_abt:1;
1204 uint64_t rrsl_int:1;
1222 uint64_t reserved_34_63:30;
1225 struct cvmx_pci_int_enb2_cn30xx {
1226 #ifdef __BIG_ENDIAN_BITFIELD
1227 uint64_t reserved_34_63:30;
1237 uint64_t reserved_22_24:3;
1239 uint64_t reserved_18_20:3;
1241 uint64_t rrsl_int:1;
1247 uint64_t rtsr_abt:1;
1248 uint64_t rmsc_msg:1;
1249 uint64_t rmsi_mabt:1;
1250 uint64_t rmsi_tabt:1;
1251 uint64_t rmsi_per:1;
1255 uint64_t rmr_wtto:1;
1256 uint64_t rmr_wabt:1;
1257 uint64_t rtr_wabt:1;
1259 uint64_t rtr_wabt:1;
1260 uint64_t rmr_wabt:1;
1261 uint64_t rmr_wtto:1;
1265 uint64_t rmsi_per:1;
1266 uint64_t rmsi_tabt:1;
1267 uint64_t rmsi_mabt:1;
1268 uint64_t rmsc_msg:1;
1269 uint64_t rtsr_abt:1;
1275 uint64_t rrsl_int:1;
1277 uint64_t reserved_18_20:3;
1279 uint64_t reserved_22_24:3;
1289 uint64_t reserved_34_63:30;
1292 struct cvmx_pci_int_enb2_cn31xx {
1293 #ifdef __BIG_ENDIAN_BITFIELD
1294 uint64_t reserved_34_63:30;
1304 uint64_t reserved_23_24:2;
1307 uint64_t reserved_19_20:2;
1310 uint64_t rrsl_int:1;
1316 uint64_t rtsr_abt:1;
1317 uint64_t rmsc_msg:1;
1318 uint64_t rmsi_mabt:1;
1319 uint64_t rmsi_tabt:1;
1320 uint64_t rmsi_per:1;
1324 uint64_t rmr_wtto:1;
1325 uint64_t rmr_wabt:1;
1326 uint64_t rtr_wabt:1;
1328 uint64_t rtr_wabt:1;
1329 uint64_t rmr_wabt:1;
1330 uint64_t rmr_wtto:1;
1334 uint64_t rmsi_per:1;
1335 uint64_t rmsi_tabt:1;
1336 uint64_t rmsi_mabt:1;
1337 uint64_t rmsc_msg:1;
1338 uint64_t rtsr_abt:1;
1344 uint64_t rrsl_int:1;
1347 uint64_t reserved_19_20:2;
1350 uint64_t reserved_23_24:2;
1360 uint64_t reserved_34_63:30;
1365 union cvmx_pci_int_sum {
1367 struct cvmx_pci_int_sum_s {
1368 #ifdef __BIG_ENDIAN_BITFIELD
1369 uint64_t reserved_34_63:30;
1395 uint64_t msi_mabt:1;
1396 uint64_t msi_tabt:1;
1412 uint64_t msi_tabt:1;
1413 uint64_t msi_mabt:1;
1439 uint64_t reserved_34_63:30;
1442 struct cvmx_pci_int_sum_cn30xx {
1443 #ifdef __BIG_ENDIAN_BITFIELD
1444 uint64_t reserved_34_63:30;
1454 uint64_t reserved_22_24:3;
1456 uint64_t reserved_18_20:3;
1466 uint64_t msi_mabt:1;
1467 uint64_t msi_tabt:1;
1483 uint64_t msi_tabt:1;
1484 uint64_t msi_mabt:1;
1494 uint64_t reserved_18_20:3;
1496 uint64_t reserved_22_24:3;
1506 uint64_t reserved_34_63:30;
1509 struct cvmx_pci_int_sum_cn31xx {
1510 #ifdef __BIG_ENDIAN_BITFIELD
1511 uint64_t reserved_34_63:30;
1521 uint64_t reserved_23_24:2;
1524 uint64_t reserved_19_20:2;
1535 uint64_t msi_mabt:1;
1536 uint64_t msi_tabt:1;
1552 uint64_t msi_tabt:1;
1553 uint64_t msi_mabt:1;
1564 uint64_t reserved_19_20:2;
1567 uint64_t reserved_23_24:2;
1577 uint64_t reserved_34_63:30;
1582 union cvmx_pci_int_sum2 {
1584 struct cvmx_pci_int_sum2_s {
1585 #ifdef __BIG_ENDIAN_BITFIELD
1586 uint64_t reserved_34_63:30;
1612 uint64_t msi_mabt:1;
1613 uint64_t msi_tabt:1;
1629 uint64_t msi_tabt:1;
1630 uint64_t msi_mabt:1;
1656 uint64_t reserved_34_63:30;
1659 struct cvmx_pci_int_sum2_cn30xx {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661 uint64_t reserved_34_63:30;
1671 uint64_t reserved_22_24:3;
1673 uint64_t reserved_18_20:3;
1683 uint64_t msi_mabt:1;
1684 uint64_t msi_tabt:1;
1700 uint64_t msi_tabt:1;
1701 uint64_t msi_mabt:1;
1711 uint64_t reserved_18_20:3;
1713 uint64_t reserved_22_24:3;
1723 uint64_t reserved_34_63:30;
1726 struct cvmx_pci_int_sum2_cn31xx {
1727 #ifdef __BIG_ENDIAN_BITFIELD
1728 uint64_t reserved_34_63:30;
1738 uint64_t reserved_23_24:2;
1741 uint64_t reserved_19_20:2;
1752 uint64_t msi_mabt:1;
1753 uint64_t msi_tabt:1;
1769 uint64_t msi_tabt:1;
1770 uint64_t msi_mabt:1;
1781 uint64_t reserved_19_20:2;
1784 uint64_t reserved_23_24:2;
1794 uint64_t reserved_34_63:30;
1799 union cvmx_pci_msi_rcv {
1801 struct cvmx_pci_msi_rcv_s {
1802 #ifdef __BIG_ENDIAN_BITFIELD
1803 uint32_t reserved_6_31:26;
1807 uint32_t reserved_6_31:26;
1812 union cvmx_pci_pkt_creditsx {
1814 struct cvmx_pci_pkt_creditsx_s {
1815 #ifdef __BIG_ENDIAN_BITFIELD
1816 uint32_t pkt_cnt:16;
1817 uint32_t ptr_cnt:16;
1819 uint32_t ptr_cnt:16;
1820 uint32_t pkt_cnt:16;
1825 union cvmx_pci_pkts_sentx {
1827 struct cvmx_pci_pkts_sentx_s {
1828 #ifdef __BIG_ENDIAN_BITFIELD
1829 uint32_t pkt_cnt:32;
1831 uint32_t pkt_cnt:32;
1836 union cvmx_pci_pkts_sent_int_levx {
1838 struct cvmx_pci_pkts_sent_int_levx_s {
1839 #ifdef __BIG_ENDIAN_BITFIELD
1840 uint32_t pkt_cnt:32;
1842 uint32_t pkt_cnt:32;
1847 union cvmx_pci_pkts_sent_timex {
1849 struct cvmx_pci_pkts_sent_timex_s {
1850 #ifdef __BIG_ENDIAN_BITFIELD
1851 uint32_t pkt_time:32;
1853 uint32_t pkt_time:32;
1858 union cvmx_pci_read_cmd_6 {
1860 struct cvmx_pci_read_cmd_6_s {
1861 #ifdef __BIG_ENDIAN_BITFIELD
1862 uint32_t reserved_9_31:23;
1863 uint32_t min_data:6;
1864 uint32_t prefetch:3;
1866 uint32_t prefetch:3;
1867 uint32_t min_data:6;
1868 uint32_t reserved_9_31:23;
1873 union cvmx_pci_read_cmd_c {
1875 struct cvmx_pci_read_cmd_c_s {
1876 #ifdef __BIG_ENDIAN_BITFIELD
1877 uint32_t reserved_9_31:23;
1878 uint32_t min_data:6;
1879 uint32_t prefetch:3;
1881 uint32_t prefetch:3;
1882 uint32_t min_data:6;
1883 uint32_t reserved_9_31:23;
1888 union cvmx_pci_read_cmd_e {
1890 struct cvmx_pci_read_cmd_e_s {
1891 #ifdef __BIG_ENDIAN_BITFIELD
1892 uint32_t reserved_9_31:23;
1893 uint32_t min_data:6;
1894 uint32_t prefetch:3;
1896 uint32_t prefetch:3;
1897 uint32_t min_data:6;
1898 uint32_t reserved_9_31:23;
1903 union cvmx_pci_read_timeout {
1905 struct cvmx_pci_read_timeout_s {
1906 #ifdef __BIG_ENDIAN_BITFIELD
1907 uint64_t reserved_32_63:32;
1913 uint64_t reserved_32_63:32;
1918 union cvmx_pci_scm_reg {
1920 struct cvmx_pci_scm_reg_s {
1921 #ifdef __BIG_ENDIAN_BITFIELD
1922 uint64_t reserved_32_63:32;
1926 uint64_t reserved_32_63:32;
1931 union cvmx_pci_tsr_reg {
1933 struct cvmx_pci_tsr_reg_s {
1934 #ifdef __BIG_ENDIAN_BITFIELD
1935 uint64_t reserved_36_63:28;
1939 uint64_t reserved_36_63:28;
1944 union cvmx_pci_win_rd_addr {
1946 struct cvmx_pci_win_rd_addr_s {
1947 #ifdef __BIG_ENDIAN_BITFIELD
1948 uint64_t reserved_49_63:15;
1950 uint64_t reserved_0_47:48;
1952 uint64_t reserved_0_47:48;
1954 uint64_t reserved_49_63:15;
1957 struct cvmx_pci_win_rd_addr_cn30xx {
1958 #ifdef __BIG_ENDIAN_BITFIELD
1959 uint64_t reserved_49_63:15;
1961 uint64_t rd_addr:46;
1962 uint64_t reserved_0_1:2;
1964 uint64_t reserved_0_1:2;
1965 uint64_t rd_addr:46;
1967 uint64_t reserved_49_63:15;
1970 struct cvmx_pci_win_rd_addr_cn38xx {
1971 #ifdef __BIG_ENDIAN_BITFIELD
1972 uint64_t reserved_49_63:15;
1974 uint64_t rd_addr:45;
1975 uint64_t reserved_0_2:3;
1977 uint64_t reserved_0_2:3;
1978 uint64_t rd_addr:45;
1980 uint64_t reserved_49_63:15;
1985 union cvmx_pci_win_rd_data {
1987 struct cvmx_pci_win_rd_data_s {
1988 #ifdef __BIG_ENDIAN_BITFIELD
1989 uint64_t rd_data:64;
1991 uint64_t rd_data:64;
1996 union cvmx_pci_win_wr_addr {
1998 struct cvmx_pci_win_wr_addr_s {
1999 #ifdef __BIG_ENDIAN_BITFIELD
2000 uint64_t reserved_49_63:15;
2002 uint64_t wr_addr:45;
2003 uint64_t reserved_0_2:3;
2005 uint64_t reserved_0_2:3;
2006 uint64_t wr_addr:45;
2008 uint64_t reserved_49_63:15;
2013 union cvmx_pci_win_wr_data {
2015 struct cvmx_pci_win_wr_data_s {
2016 #ifdef __BIG_ENDIAN_BITFIELD
2017 uint64_t wr_data:64;
2019 uint64_t wr_data:64;
2024 union cvmx_pci_win_wr_mask {
2026 struct cvmx_pci_win_wr_mask_s {
2027 #ifdef __BIG_ENDIAN_BITFIELD
2028 uint64_t reserved_8_63:56;
2032 uint64_t reserved_8_63:56;