1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_NPI_DEFS_H__
29 #define __CVMX_NPI_DEFS_H__
31 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
32 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
33 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
34 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
35 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
36 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
37 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
38 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
39 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
40 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
41 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
42 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
43 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
44 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
45 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
46 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
47 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
48 #define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
49 #define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
50 #define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
51 #define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
52 #define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
53 #define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
54 #define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
55 #define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
56 #define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
57 #define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
58 #define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
59 #define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
60 #define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
61 #define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
62 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
63 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
64 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
65 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
66 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
67 #define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
68 #define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
69 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
70 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
71 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
72 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
73 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
74 #define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
75 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
76 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
77 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
78 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
79 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
80 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
81 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
82 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
83 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
84 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
85 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
86 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
87 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
88 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
89 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
90 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
91 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
92 #define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
93 #define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
94 #define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
95 #define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
96 #define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
97 #define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
98 #define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
99 #define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
100 #define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
101 #define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
102 #define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
103 #define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
104 #define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
105 #define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
106 #define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
107 #define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
108 #define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
109 #define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
110 #define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
111 #define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
112 #define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
113 #define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
114 #define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
115 #define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
116 #define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
117 #define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
118 #define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
119 #define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
120 #define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
121 #define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
122 #define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
123 #define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
124 #define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
125 #define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
126 #define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
127 #define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
128 #define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
129 #define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
130 #define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
131 #define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
132 #define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
133 #define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
134 #define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
135 #define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
136 #define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
137 #define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
138 #define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
139 #define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
140 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
141 #define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
142 #define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
143 #define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
144 #define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
145 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
147 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
148 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
149 #define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
150 #define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
152 union cvmx_npi_base_addr_inputx {
154 struct cvmx_npi_base_addr_inputx_s {
155 #ifdef __BIG_ENDIAN_BITFIELD
157 uint64_t reserved_0_2:3;
159 uint64_t reserved_0_2:3;
163 struct cvmx_npi_base_addr_inputx_s cn30xx;
164 struct cvmx_npi_base_addr_inputx_s cn31xx;
165 struct cvmx_npi_base_addr_inputx_s cn38xx;
166 struct cvmx_npi_base_addr_inputx_s cn38xxp2;
167 struct cvmx_npi_base_addr_inputx_s cn50xx;
168 struct cvmx_npi_base_addr_inputx_s cn58xx;
169 struct cvmx_npi_base_addr_inputx_s cn58xxp1;
172 union cvmx_npi_base_addr_outputx {
174 struct cvmx_npi_base_addr_outputx_s {
175 #ifdef __BIG_ENDIAN_BITFIELD
177 uint64_t reserved_0_2:3;
179 uint64_t reserved_0_2:3;
183 struct cvmx_npi_base_addr_outputx_s cn30xx;
184 struct cvmx_npi_base_addr_outputx_s cn31xx;
185 struct cvmx_npi_base_addr_outputx_s cn38xx;
186 struct cvmx_npi_base_addr_outputx_s cn38xxp2;
187 struct cvmx_npi_base_addr_outputx_s cn50xx;
188 struct cvmx_npi_base_addr_outputx_s cn58xx;
189 struct cvmx_npi_base_addr_outputx_s cn58xxp1;
192 union cvmx_npi_bist_status {
194 struct cvmx_npi_bist_status_s {
195 #ifdef __BIG_ENDIAN_BITFIELD
196 uint64_t reserved_20_63:44;
238 uint64_t reserved_20_63:44;
241 struct cvmx_npi_bist_status_cn30xx {
242 #ifdef __BIG_ENDIAN_BITFIELD
243 uint64_t reserved_20_63:44;
256 uint64_t reserved_5_7:3;
268 uint64_t reserved_5_7:3;
281 uint64_t reserved_20_63:44;
284 struct cvmx_npi_bist_status_s cn31xx;
285 struct cvmx_npi_bist_status_s cn38xx;
286 struct cvmx_npi_bist_status_s cn38xxp2;
287 struct cvmx_npi_bist_status_cn50xx {
288 #ifdef __BIG_ENDIAN_BITFIELD
289 uint64_t reserved_20_63:44;
303 uint64_t reserved_5_6:2;
315 uint64_t reserved_5_6:2;
329 uint64_t reserved_20_63:44;
332 struct cvmx_npi_bist_status_s cn58xx;
333 struct cvmx_npi_bist_status_s cn58xxp1;
336 union cvmx_npi_buff_size_outputx {
338 struct cvmx_npi_buff_size_outputx_s {
339 #ifdef __BIG_ENDIAN_BITFIELD
340 uint64_t reserved_23_63:41;
346 uint64_t reserved_23_63:41;
349 struct cvmx_npi_buff_size_outputx_s cn30xx;
350 struct cvmx_npi_buff_size_outputx_s cn31xx;
351 struct cvmx_npi_buff_size_outputx_s cn38xx;
352 struct cvmx_npi_buff_size_outputx_s cn38xxp2;
353 struct cvmx_npi_buff_size_outputx_s cn50xx;
354 struct cvmx_npi_buff_size_outputx_s cn58xx;
355 struct cvmx_npi_buff_size_outputx_s cn58xxp1;
358 union cvmx_npi_comp_ctl {
360 struct cvmx_npi_comp_ctl_s {
361 #ifdef __BIG_ENDIAN_BITFIELD
362 uint64_t reserved_10_63:54;
368 uint64_t reserved_10_63:54;
371 struct cvmx_npi_comp_ctl_s cn50xx;
372 struct cvmx_npi_comp_ctl_s cn58xx;
373 struct cvmx_npi_comp_ctl_s cn58xxp1;
376 union cvmx_npi_ctl_status {
378 struct cvmx_npi_ctl_status_s {
379 #ifdef __BIG_ENDIAN_BITFIELD
380 uint64_t reserved_63_63:1;
397 uint64_t reserved_37_39:3;
399 uint64_t reserved_10_31:22;
403 uint64_t reserved_10_31:22;
405 uint64_t reserved_37_39:3;
422 uint64_t reserved_63_63:1;
425 struct cvmx_npi_ctl_status_cn30xx {
426 #ifdef __BIG_ENDIAN_BITFIELD
427 uint64_t reserved_63_63:1;
430 uint64_t reserved_51_53:3;
432 uint64_t reserved_47_49:3;
434 uint64_t reserved_43_45:3;
438 uint64_t reserved_37_39:3;
440 uint64_t reserved_10_31:22;
444 uint64_t reserved_10_31:22;
446 uint64_t reserved_37_39:3;
450 uint64_t reserved_43_45:3;
452 uint64_t reserved_47_49:3;
454 uint64_t reserved_51_53:3;
457 uint64_t reserved_63_63:1;
460 struct cvmx_npi_ctl_status_cn31xx {
461 #ifdef __BIG_ENDIAN_BITFIELD
462 uint64_t reserved_63_63:1;
465 uint64_t reserved_52_53:2;
468 uint64_t reserved_48_49:2;
471 uint64_t reserved_44_45:2;
476 uint64_t reserved_37_39:3;
478 uint64_t reserved_10_31:22;
482 uint64_t reserved_10_31:22;
484 uint64_t reserved_37_39:3;
489 uint64_t reserved_44_45:2;
492 uint64_t reserved_48_49:2;
495 uint64_t reserved_52_53:2;
498 uint64_t reserved_63_63:1;
501 struct cvmx_npi_ctl_status_s cn38xx;
502 struct cvmx_npi_ctl_status_s cn38xxp2;
503 struct cvmx_npi_ctl_status_cn31xx cn50xx;
504 struct cvmx_npi_ctl_status_s cn58xx;
505 struct cvmx_npi_ctl_status_s cn58xxp1;
508 union cvmx_npi_dbg_select {
510 struct cvmx_npi_dbg_select_s {
511 #ifdef __BIG_ENDIAN_BITFIELD
512 uint64_t reserved_16_63:48;
516 uint64_t reserved_16_63:48;
519 struct cvmx_npi_dbg_select_s cn30xx;
520 struct cvmx_npi_dbg_select_s cn31xx;
521 struct cvmx_npi_dbg_select_s cn38xx;
522 struct cvmx_npi_dbg_select_s cn38xxp2;
523 struct cvmx_npi_dbg_select_s cn50xx;
524 struct cvmx_npi_dbg_select_s cn58xx;
525 struct cvmx_npi_dbg_select_s cn58xxp1;
528 union cvmx_npi_dma_control {
530 struct cvmx_npi_dma_control_s {
531 #ifdef __BIG_ENDIAN_BITFIELD
532 uint64_t reserved_36_63:28;
558 uint64_t reserved_36_63:28;
561 struct cvmx_npi_dma_control_s cn30xx;
562 struct cvmx_npi_dma_control_s cn31xx;
563 struct cvmx_npi_dma_control_s cn38xx;
564 struct cvmx_npi_dma_control_s cn38xxp2;
565 struct cvmx_npi_dma_control_s cn50xx;
566 struct cvmx_npi_dma_control_s cn58xx;
567 struct cvmx_npi_dma_control_s cn58xxp1;
570 union cvmx_npi_dma_highp_counts {
572 struct cvmx_npi_dma_highp_counts_s {
573 #ifdef __BIG_ENDIAN_BITFIELD
574 uint64_t reserved_39_63:25;
580 uint64_t reserved_39_63:25;
583 struct cvmx_npi_dma_highp_counts_s cn30xx;
584 struct cvmx_npi_dma_highp_counts_s cn31xx;
585 struct cvmx_npi_dma_highp_counts_s cn38xx;
586 struct cvmx_npi_dma_highp_counts_s cn38xxp2;
587 struct cvmx_npi_dma_highp_counts_s cn50xx;
588 struct cvmx_npi_dma_highp_counts_s cn58xx;
589 struct cvmx_npi_dma_highp_counts_s cn58xxp1;
592 union cvmx_npi_dma_highp_naddr {
594 struct cvmx_npi_dma_highp_naddr_s {
595 #ifdef __BIG_ENDIAN_BITFIELD
596 uint64_t reserved_40_63:24;
602 uint64_t reserved_40_63:24;
605 struct cvmx_npi_dma_highp_naddr_s cn30xx;
606 struct cvmx_npi_dma_highp_naddr_s cn31xx;
607 struct cvmx_npi_dma_highp_naddr_s cn38xx;
608 struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
609 struct cvmx_npi_dma_highp_naddr_s cn50xx;
610 struct cvmx_npi_dma_highp_naddr_s cn58xx;
611 struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
614 union cvmx_npi_dma_lowp_counts {
616 struct cvmx_npi_dma_lowp_counts_s {
617 #ifdef __BIG_ENDIAN_BITFIELD
618 uint64_t reserved_39_63:25;
624 uint64_t reserved_39_63:25;
627 struct cvmx_npi_dma_lowp_counts_s cn30xx;
628 struct cvmx_npi_dma_lowp_counts_s cn31xx;
629 struct cvmx_npi_dma_lowp_counts_s cn38xx;
630 struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
631 struct cvmx_npi_dma_lowp_counts_s cn50xx;
632 struct cvmx_npi_dma_lowp_counts_s cn58xx;
633 struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
636 union cvmx_npi_dma_lowp_naddr {
638 struct cvmx_npi_dma_lowp_naddr_s {
639 #ifdef __BIG_ENDIAN_BITFIELD
640 uint64_t reserved_40_63:24;
646 uint64_t reserved_40_63:24;
649 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
650 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
651 struct cvmx_npi_dma_lowp_naddr_s cn38xx;
652 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
653 struct cvmx_npi_dma_lowp_naddr_s cn50xx;
654 struct cvmx_npi_dma_lowp_naddr_s cn58xx;
655 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
658 union cvmx_npi_highp_dbell {
660 struct cvmx_npi_highp_dbell_s {
661 #ifdef __BIG_ENDIAN_BITFIELD
662 uint64_t reserved_16_63:48;
666 uint64_t reserved_16_63:48;
669 struct cvmx_npi_highp_dbell_s cn30xx;
670 struct cvmx_npi_highp_dbell_s cn31xx;
671 struct cvmx_npi_highp_dbell_s cn38xx;
672 struct cvmx_npi_highp_dbell_s cn38xxp2;
673 struct cvmx_npi_highp_dbell_s cn50xx;
674 struct cvmx_npi_highp_dbell_s cn58xx;
675 struct cvmx_npi_highp_dbell_s cn58xxp1;
678 union cvmx_npi_highp_ibuff_saddr {
680 struct cvmx_npi_highp_ibuff_saddr_s {
681 #ifdef __BIG_ENDIAN_BITFIELD
682 uint64_t reserved_36_63:28;
686 uint64_t reserved_36_63:28;
689 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
690 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
691 struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
692 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
693 struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
694 struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
695 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
698 union cvmx_npi_input_control {
700 struct cvmx_npi_input_control_s {
701 #ifdef __BIG_ENDIAN_BITFIELD
702 uint64_t reserved_23_63:41;
722 uint64_t reserved_23_63:41;
725 struct cvmx_npi_input_control_cn30xx {
726 #ifdef __BIG_ENDIAN_BITFIELD
727 uint64_t reserved_22_63:42;
745 uint64_t reserved_22_63:42;
748 struct cvmx_npi_input_control_cn30xx cn31xx;
749 struct cvmx_npi_input_control_s cn38xx;
750 struct cvmx_npi_input_control_cn30xx cn38xxp2;
751 struct cvmx_npi_input_control_s cn50xx;
752 struct cvmx_npi_input_control_s cn58xx;
753 struct cvmx_npi_input_control_s cn58xxp1;
756 union cvmx_npi_int_enb {
758 struct cvmx_npi_int_enb_s {
759 #ifdef __BIG_ENDIAN_BITFIELD
760 uint64_t reserved_62_63:2;
886 uint64_t reserved_62_63:2;
889 struct cvmx_npi_int_enb_cn30xx {
890 #ifdef __BIG_ENDIAN_BITFIELD
891 uint64_t reserved_62_63:2;
915 uint64_t reserved_36_38:3;
917 uint64_t reserved_32_34:3;
919 uint64_t reserved_28_30:3;
921 uint64_t reserved_24_26:3;
923 uint64_t reserved_20_22:3;
925 uint64_t reserved_16_18:3;
927 uint64_t reserved_12_14:3;
929 uint64_t reserved_8_10:3;
931 uint64_t reserved_4_6:3;
941 uint64_t reserved_4_6:3;
943 uint64_t reserved_8_10:3;
945 uint64_t reserved_12_14:3;
947 uint64_t reserved_16_18:3;
949 uint64_t reserved_20_22:3;
951 uint64_t reserved_24_26:3;
953 uint64_t reserved_28_30:3;
955 uint64_t reserved_32_34:3;
957 uint64_t reserved_36_38:3;
981 uint64_t reserved_62_63:2;
984 struct cvmx_npi_int_enb_cn31xx {
985 #ifdef __BIG_ENDIAN_BITFIELD
986 uint64_t reserved_62_63:2;
1010 uint64_t reserved_37_38:2;
1011 uint64_t i1_pperr:1;
1012 uint64_t i0_pperr:1;
1013 uint64_t reserved_33_34:2;
1014 uint64_t p1_ptout:1;
1015 uint64_t p0_ptout:1;
1016 uint64_t reserved_29_30:2;
1017 uint64_t p1_pperr:1;
1018 uint64_t p0_pperr:1;
1019 uint64_t reserved_25_26:2;
1020 uint64_t g1_rtout:1;
1021 uint64_t g0_rtout:1;
1022 uint64_t reserved_21_22:2;
1025 uint64_t reserved_17_18:2;
1026 uint64_t p1_rtout:1;
1027 uint64_t p0_rtout:1;
1028 uint64_t reserved_13_14:2;
1029 uint64_t i1_overf:1;
1030 uint64_t i0_overf:1;
1031 uint64_t reserved_9_10:2;
1032 uint64_t i1_rtout:1;
1033 uint64_t i0_rtout:1;
1034 uint64_t reserved_5_6:2;
1035 uint64_t po1_2sml:1;
1036 uint64_t po0_2sml:1;
1044 uint64_t po0_2sml:1;
1045 uint64_t po1_2sml:1;
1046 uint64_t reserved_5_6:2;
1047 uint64_t i0_rtout:1;
1048 uint64_t i1_rtout:1;
1049 uint64_t reserved_9_10:2;
1050 uint64_t i0_overf:1;
1051 uint64_t i1_overf:1;
1052 uint64_t reserved_13_14:2;
1053 uint64_t p0_rtout:1;
1054 uint64_t p1_rtout:1;
1055 uint64_t reserved_17_18:2;
1058 uint64_t reserved_21_22:2;
1059 uint64_t g0_rtout:1;
1060 uint64_t g1_rtout:1;
1061 uint64_t reserved_25_26:2;
1062 uint64_t p0_pperr:1;
1063 uint64_t p1_pperr:1;
1064 uint64_t reserved_29_30:2;
1065 uint64_t p0_ptout:1;
1066 uint64_t p1_ptout:1;
1067 uint64_t reserved_33_34:2;
1068 uint64_t i0_pperr:1;
1069 uint64_t i1_pperr:1;
1070 uint64_t reserved_37_38:2;
1094 uint64_t reserved_62_63:2;
1097 struct cvmx_npi_int_enb_s cn38xx;
1098 struct cvmx_npi_int_enb_cn38xxp2 {
1099 #ifdef __BIG_ENDIAN_BITFIELD
1100 uint64_t reserved_42_63:22;
1104 uint64_t i3_pperr:1;
1105 uint64_t i2_pperr:1;
1106 uint64_t i1_pperr:1;
1107 uint64_t i0_pperr:1;
1108 uint64_t p3_ptout:1;
1109 uint64_t p2_ptout:1;
1110 uint64_t p1_ptout:1;
1111 uint64_t p0_ptout:1;
1112 uint64_t p3_pperr:1;
1113 uint64_t p2_pperr:1;
1114 uint64_t p1_pperr:1;
1115 uint64_t p0_pperr:1;
1116 uint64_t g3_rtout:1;
1117 uint64_t g2_rtout:1;
1118 uint64_t g1_rtout:1;
1119 uint64_t g0_rtout:1;
1124 uint64_t p3_rtout:1;
1125 uint64_t p2_rtout:1;
1126 uint64_t p1_rtout:1;
1127 uint64_t p0_rtout:1;
1128 uint64_t i3_overf:1;
1129 uint64_t i2_overf:1;
1130 uint64_t i1_overf:1;
1131 uint64_t i0_overf:1;
1132 uint64_t i3_rtout:1;
1133 uint64_t i2_rtout:1;
1134 uint64_t i1_rtout:1;
1135 uint64_t i0_rtout:1;
1136 uint64_t po3_2sml:1;
1137 uint64_t po2_2sml:1;
1138 uint64_t po1_2sml:1;
1139 uint64_t po0_2sml:1;
1147 uint64_t po0_2sml:1;
1148 uint64_t po1_2sml:1;
1149 uint64_t po2_2sml:1;
1150 uint64_t po3_2sml:1;
1151 uint64_t i0_rtout:1;
1152 uint64_t i1_rtout:1;
1153 uint64_t i2_rtout:1;
1154 uint64_t i3_rtout:1;
1155 uint64_t i0_overf:1;
1156 uint64_t i1_overf:1;
1157 uint64_t i2_overf:1;
1158 uint64_t i3_overf:1;
1159 uint64_t p0_rtout:1;
1160 uint64_t p1_rtout:1;
1161 uint64_t p2_rtout:1;
1162 uint64_t p3_rtout:1;
1167 uint64_t g0_rtout:1;
1168 uint64_t g1_rtout:1;
1169 uint64_t g2_rtout:1;
1170 uint64_t g3_rtout:1;
1171 uint64_t p0_pperr:1;
1172 uint64_t p1_pperr:1;
1173 uint64_t p2_pperr:1;
1174 uint64_t p3_pperr:1;
1175 uint64_t p0_ptout:1;
1176 uint64_t p1_ptout:1;
1177 uint64_t p2_ptout:1;
1178 uint64_t p3_ptout:1;
1179 uint64_t i0_pperr:1;
1180 uint64_t i1_pperr:1;
1181 uint64_t i2_pperr:1;
1182 uint64_t i3_pperr:1;
1186 uint64_t reserved_42_63:22;
1189 struct cvmx_npi_int_enb_cn31xx cn50xx;
1190 struct cvmx_npi_int_enb_s cn58xx;
1191 struct cvmx_npi_int_enb_s cn58xxp1;
1194 union cvmx_npi_int_sum {
1196 struct cvmx_npi_int_sum_s {
1197 #ifdef __BIG_ENDIAN_BITFIELD
1198 uint64_t reserved_62_63:2;
1222 uint64_t i3_pperr:1;
1223 uint64_t i2_pperr:1;
1224 uint64_t i1_pperr:1;
1225 uint64_t i0_pperr:1;
1226 uint64_t p3_ptout:1;
1227 uint64_t p2_ptout:1;
1228 uint64_t p1_ptout:1;
1229 uint64_t p0_ptout:1;
1230 uint64_t p3_pperr:1;
1231 uint64_t p2_pperr:1;
1232 uint64_t p1_pperr:1;
1233 uint64_t p0_pperr:1;
1234 uint64_t g3_rtout:1;
1235 uint64_t g2_rtout:1;
1236 uint64_t g1_rtout:1;
1237 uint64_t g0_rtout:1;
1242 uint64_t p3_rtout:1;
1243 uint64_t p2_rtout:1;
1244 uint64_t p1_rtout:1;
1245 uint64_t p0_rtout:1;
1246 uint64_t i3_overf:1;
1247 uint64_t i2_overf:1;
1248 uint64_t i1_overf:1;
1249 uint64_t i0_overf:1;
1250 uint64_t i3_rtout:1;
1251 uint64_t i2_rtout:1;
1252 uint64_t i1_rtout:1;
1253 uint64_t i0_rtout:1;
1254 uint64_t po3_2sml:1;
1255 uint64_t po2_2sml:1;
1256 uint64_t po1_2sml:1;
1257 uint64_t po0_2sml:1;
1265 uint64_t po0_2sml:1;
1266 uint64_t po1_2sml:1;
1267 uint64_t po2_2sml:1;
1268 uint64_t po3_2sml:1;
1269 uint64_t i0_rtout:1;
1270 uint64_t i1_rtout:1;
1271 uint64_t i2_rtout:1;
1272 uint64_t i3_rtout:1;
1273 uint64_t i0_overf:1;
1274 uint64_t i1_overf:1;
1275 uint64_t i2_overf:1;
1276 uint64_t i3_overf:1;
1277 uint64_t p0_rtout:1;
1278 uint64_t p1_rtout:1;
1279 uint64_t p2_rtout:1;
1280 uint64_t p3_rtout:1;
1285 uint64_t g0_rtout:1;
1286 uint64_t g1_rtout:1;
1287 uint64_t g2_rtout:1;
1288 uint64_t g3_rtout:1;
1289 uint64_t p0_pperr:1;
1290 uint64_t p1_pperr:1;
1291 uint64_t p2_pperr:1;
1292 uint64_t p3_pperr:1;
1293 uint64_t p0_ptout:1;
1294 uint64_t p1_ptout:1;
1295 uint64_t p2_ptout:1;
1296 uint64_t p3_ptout:1;
1297 uint64_t i0_pperr:1;
1298 uint64_t i1_pperr:1;
1299 uint64_t i2_pperr:1;
1300 uint64_t i3_pperr:1;
1324 uint64_t reserved_62_63:2;
1327 struct cvmx_npi_int_sum_cn30xx {
1328 #ifdef __BIG_ENDIAN_BITFIELD
1329 uint64_t reserved_62_63:2;
1353 uint64_t reserved_36_38:3;
1354 uint64_t i0_pperr:1;
1355 uint64_t reserved_32_34:3;
1356 uint64_t p0_ptout:1;
1357 uint64_t reserved_28_30:3;
1358 uint64_t p0_pperr:1;
1359 uint64_t reserved_24_26:3;
1360 uint64_t g0_rtout:1;
1361 uint64_t reserved_20_22:3;
1363 uint64_t reserved_16_18:3;
1364 uint64_t p0_rtout:1;
1365 uint64_t reserved_12_14:3;
1366 uint64_t i0_overf:1;
1367 uint64_t reserved_8_10:3;
1368 uint64_t i0_rtout:1;
1369 uint64_t reserved_4_6:3;
1370 uint64_t po0_2sml:1;
1378 uint64_t po0_2sml:1;
1379 uint64_t reserved_4_6:3;
1380 uint64_t i0_rtout:1;
1381 uint64_t reserved_8_10:3;
1382 uint64_t i0_overf:1;
1383 uint64_t reserved_12_14:3;
1384 uint64_t p0_rtout:1;
1385 uint64_t reserved_16_18:3;
1387 uint64_t reserved_20_22:3;
1388 uint64_t g0_rtout:1;
1389 uint64_t reserved_24_26:3;
1390 uint64_t p0_pperr:1;
1391 uint64_t reserved_28_30:3;
1392 uint64_t p0_ptout:1;
1393 uint64_t reserved_32_34:3;
1394 uint64_t i0_pperr:1;
1395 uint64_t reserved_36_38:3;
1419 uint64_t reserved_62_63:2;
1422 struct cvmx_npi_int_sum_cn31xx {
1423 #ifdef __BIG_ENDIAN_BITFIELD
1424 uint64_t reserved_62_63:2;
1448 uint64_t reserved_37_38:2;
1449 uint64_t i1_pperr:1;
1450 uint64_t i0_pperr:1;
1451 uint64_t reserved_33_34:2;
1452 uint64_t p1_ptout:1;
1453 uint64_t p0_ptout:1;
1454 uint64_t reserved_29_30:2;
1455 uint64_t p1_pperr:1;
1456 uint64_t p0_pperr:1;
1457 uint64_t reserved_25_26:2;
1458 uint64_t g1_rtout:1;
1459 uint64_t g0_rtout:1;
1460 uint64_t reserved_21_22:2;
1463 uint64_t reserved_17_18:2;
1464 uint64_t p1_rtout:1;
1465 uint64_t p0_rtout:1;
1466 uint64_t reserved_13_14:2;
1467 uint64_t i1_overf:1;
1468 uint64_t i0_overf:1;
1469 uint64_t reserved_9_10:2;
1470 uint64_t i1_rtout:1;
1471 uint64_t i0_rtout:1;
1472 uint64_t reserved_5_6:2;
1473 uint64_t po1_2sml:1;
1474 uint64_t po0_2sml:1;
1482 uint64_t po0_2sml:1;
1483 uint64_t po1_2sml:1;
1484 uint64_t reserved_5_6:2;
1485 uint64_t i0_rtout:1;
1486 uint64_t i1_rtout:1;
1487 uint64_t reserved_9_10:2;
1488 uint64_t i0_overf:1;
1489 uint64_t i1_overf:1;
1490 uint64_t reserved_13_14:2;
1491 uint64_t p0_rtout:1;
1492 uint64_t p1_rtout:1;
1493 uint64_t reserved_17_18:2;
1496 uint64_t reserved_21_22:2;
1497 uint64_t g0_rtout:1;
1498 uint64_t g1_rtout:1;
1499 uint64_t reserved_25_26:2;
1500 uint64_t p0_pperr:1;
1501 uint64_t p1_pperr:1;
1502 uint64_t reserved_29_30:2;
1503 uint64_t p0_ptout:1;
1504 uint64_t p1_ptout:1;
1505 uint64_t reserved_33_34:2;
1506 uint64_t i0_pperr:1;
1507 uint64_t i1_pperr:1;
1508 uint64_t reserved_37_38:2;
1532 uint64_t reserved_62_63:2;
1535 struct cvmx_npi_int_sum_s cn38xx;
1536 struct cvmx_npi_int_sum_cn38xxp2 {
1537 #ifdef __BIG_ENDIAN_BITFIELD
1538 uint64_t reserved_42_63:22;
1542 uint64_t i3_pperr:1;
1543 uint64_t i2_pperr:1;
1544 uint64_t i1_pperr:1;
1545 uint64_t i0_pperr:1;
1546 uint64_t p3_ptout:1;
1547 uint64_t p2_ptout:1;
1548 uint64_t p1_ptout:1;
1549 uint64_t p0_ptout:1;
1550 uint64_t p3_pperr:1;
1551 uint64_t p2_pperr:1;
1552 uint64_t p1_pperr:1;
1553 uint64_t p0_pperr:1;
1554 uint64_t g3_rtout:1;
1555 uint64_t g2_rtout:1;
1556 uint64_t g1_rtout:1;
1557 uint64_t g0_rtout:1;
1562 uint64_t p3_rtout:1;
1563 uint64_t p2_rtout:1;
1564 uint64_t p1_rtout:1;
1565 uint64_t p0_rtout:1;
1566 uint64_t i3_overf:1;
1567 uint64_t i2_overf:1;
1568 uint64_t i1_overf:1;
1569 uint64_t i0_overf:1;
1570 uint64_t i3_rtout:1;
1571 uint64_t i2_rtout:1;
1572 uint64_t i1_rtout:1;
1573 uint64_t i0_rtout:1;
1574 uint64_t po3_2sml:1;
1575 uint64_t po2_2sml:1;
1576 uint64_t po1_2sml:1;
1577 uint64_t po0_2sml:1;
1585 uint64_t po0_2sml:1;
1586 uint64_t po1_2sml:1;
1587 uint64_t po2_2sml:1;
1588 uint64_t po3_2sml:1;
1589 uint64_t i0_rtout:1;
1590 uint64_t i1_rtout:1;
1591 uint64_t i2_rtout:1;
1592 uint64_t i3_rtout:1;
1593 uint64_t i0_overf:1;
1594 uint64_t i1_overf:1;
1595 uint64_t i2_overf:1;
1596 uint64_t i3_overf:1;
1597 uint64_t p0_rtout:1;
1598 uint64_t p1_rtout:1;
1599 uint64_t p2_rtout:1;
1600 uint64_t p3_rtout:1;
1605 uint64_t g0_rtout:1;
1606 uint64_t g1_rtout:1;
1607 uint64_t g2_rtout:1;
1608 uint64_t g3_rtout:1;
1609 uint64_t p0_pperr:1;
1610 uint64_t p1_pperr:1;
1611 uint64_t p2_pperr:1;
1612 uint64_t p3_pperr:1;
1613 uint64_t p0_ptout:1;
1614 uint64_t p1_ptout:1;
1615 uint64_t p2_ptout:1;
1616 uint64_t p3_ptout:1;
1617 uint64_t i0_pperr:1;
1618 uint64_t i1_pperr:1;
1619 uint64_t i2_pperr:1;
1620 uint64_t i3_pperr:1;
1624 uint64_t reserved_42_63:22;
1627 struct cvmx_npi_int_sum_cn31xx cn50xx;
1628 struct cvmx_npi_int_sum_s cn58xx;
1629 struct cvmx_npi_int_sum_s cn58xxp1;
1632 union cvmx_npi_lowp_dbell {
1634 struct cvmx_npi_lowp_dbell_s {
1635 #ifdef __BIG_ENDIAN_BITFIELD
1636 uint64_t reserved_16_63:48;
1640 uint64_t reserved_16_63:48;
1643 struct cvmx_npi_lowp_dbell_s cn30xx;
1644 struct cvmx_npi_lowp_dbell_s cn31xx;
1645 struct cvmx_npi_lowp_dbell_s cn38xx;
1646 struct cvmx_npi_lowp_dbell_s cn38xxp2;
1647 struct cvmx_npi_lowp_dbell_s cn50xx;
1648 struct cvmx_npi_lowp_dbell_s cn58xx;
1649 struct cvmx_npi_lowp_dbell_s cn58xxp1;
1652 union cvmx_npi_lowp_ibuff_saddr {
1654 struct cvmx_npi_lowp_ibuff_saddr_s {
1655 #ifdef __BIG_ENDIAN_BITFIELD
1656 uint64_t reserved_36_63:28;
1660 uint64_t reserved_36_63:28;
1663 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
1664 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
1665 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
1666 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
1667 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
1668 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
1669 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
1672 union cvmx_npi_mem_access_subidx {
1674 struct cvmx_npi_mem_access_subidx_s {
1675 #ifdef __BIG_ENDIAN_BITFIELD
1676 uint64_t reserved_38_63:26;
1696 uint64_t reserved_38_63:26;
1699 struct cvmx_npi_mem_access_subidx_s cn30xx;
1700 struct cvmx_npi_mem_access_subidx_cn31xx {
1701 #ifdef __BIG_ENDIAN_BITFIELD
1702 uint64_t reserved_36_63:28;
1718 uint64_t reserved_36_63:28;
1721 struct cvmx_npi_mem_access_subidx_s cn38xx;
1722 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1723 struct cvmx_npi_mem_access_subidx_s cn50xx;
1724 struct cvmx_npi_mem_access_subidx_s cn58xx;
1725 struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1728 union cvmx_npi_msi_rcv {
1730 struct cvmx_npi_msi_rcv_s {
1731 #ifdef __BIG_ENDIAN_BITFIELD
1732 uint64_t int_vec:64;
1734 uint64_t int_vec:64;
1737 struct cvmx_npi_msi_rcv_s cn30xx;
1738 struct cvmx_npi_msi_rcv_s cn31xx;
1739 struct cvmx_npi_msi_rcv_s cn38xx;
1740 struct cvmx_npi_msi_rcv_s cn38xxp2;
1741 struct cvmx_npi_msi_rcv_s cn50xx;
1742 struct cvmx_npi_msi_rcv_s cn58xx;
1743 struct cvmx_npi_msi_rcv_s cn58xxp1;
1746 union cvmx_npi_num_desc_outputx {
1748 struct cvmx_npi_num_desc_outputx_s {
1749 #ifdef __BIG_ENDIAN_BITFIELD
1750 uint64_t reserved_32_63:32;
1754 uint64_t reserved_32_63:32;
1757 struct cvmx_npi_num_desc_outputx_s cn30xx;
1758 struct cvmx_npi_num_desc_outputx_s cn31xx;
1759 struct cvmx_npi_num_desc_outputx_s cn38xx;
1760 struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1761 struct cvmx_npi_num_desc_outputx_s cn50xx;
1762 struct cvmx_npi_num_desc_outputx_s cn58xx;
1763 struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1766 union cvmx_npi_output_control {
1768 struct cvmx_npi_output_control_s {
1769 #ifdef __BIG_ENDIAN_BITFIELD
1770 uint64_t reserved_49_63:15;
1772 uint64_t p3_bmode:1;
1773 uint64_t p2_bmode:1;
1774 uint64_t p1_bmode:1;
1775 uint64_t p0_bmode:1;
1792 uint64_t reserved_20_23:4;
1826 uint64_t reserved_20_23:4;
1843 uint64_t p0_bmode:1;
1844 uint64_t p1_bmode:1;
1845 uint64_t p2_bmode:1;
1846 uint64_t p3_bmode:1;
1848 uint64_t reserved_49_63:15;
1851 struct cvmx_npi_output_control_cn30xx {
1852 #ifdef __BIG_ENDIAN_BITFIELD
1853 uint64_t reserved_45_63:19;
1854 uint64_t p0_bmode:1;
1855 uint64_t reserved_32_43:12;
1859 uint64_t reserved_25_27:3;
1861 uint64_t reserved_17_23:7;
1863 uint64_t reserved_4_15:12;
1871 uint64_t reserved_4_15:12;
1873 uint64_t reserved_17_23:7;
1875 uint64_t reserved_25_27:3;
1879 uint64_t reserved_32_43:12;
1880 uint64_t p0_bmode:1;
1881 uint64_t reserved_45_63:19;
1884 struct cvmx_npi_output_control_cn31xx {
1885 #ifdef __BIG_ENDIAN_BITFIELD
1886 uint64_t reserved_46_63:18;
1887 uint64_t p1_bmode:1;
1888 uint64_t p0_bmode:1;
1889 uint64_t reserved_36_43:8;
1896 uint64_t reserved_26_27:2;
1899 uint64_t reserved_18_23:6;
1902 uint64_t reserved_8_15:8;
1916 uint64_t reserved_8_15:8;
1919 uint64_t reserved_18_23:6;
1922 uint64_t reserved_26_27:2;
1929 uint64_t reserved_36_43:8;
1930 uint64_t p0_bmode:1;
1931 uint64_t p1_bmode:1;
1932 uint64_t reserved_46_63:18;
1935 struct cvmx_npi_output_control_s cn38xx;
1936 struct cvmx_npi_output_control_cn38xxp2 {
1937 #ifdef __BIG_ENDIAN_BITFIELD
1938 uint64_t reserved_48_63:16;
1939 uint64_t p3_bmode:1;
1940 uint64_t p2_bmode:1;
1941 uint64_t p1_bmode:1;
1942 uint64_t p0_bmode:1;
1959 uint64_t reserved_20_23:4;
1993 uint64_t reserved_20_23:4;
2010 uint64_t p0_bmode:1;
2011 uint64_t p1_bmode:1;
2012 uint64_t p2_bmode:1;
2013 uint64_t p3_bmode:1;
2014 uint64_t reserved_48_63:16;
2017 struct cvmx_npi_output_control_cn50xx {
2018 #ifdef __BIG_ENDIAN_BITFIELD
2019 uint64_t reserved_49_63:15;
2021 uint64_t reserved_46_47:2;
2022 uint64_t p1_bmode:1;
2023 uint64_t p0_bmode:1;
2024 uint64_t reserved_36_43:8;
2031 uint64_t reserved_26_27:2;
2034 uint64_t reserved_18_23:6;
2037 uint64_t reserved_8_15:8;
2051 uint64_t reserved_8_15:8;
2054 uint64_t reserved_18_23:6;
2057 uint64_t reserved_26_27:2;
2064 uint64_t reserved_36_43:8;
2065 uint64_t p0_bmode:1;
2066 uint64_t p1_bmode:1;
2067 uint64_t reserved_46_47:2;
2069 uint64_t reserved_49_63:15;
2072 struct cvmx_npi_output_control_s cn58xx;
2073 struct cvmx_npi_output_control_s cn58xxp1;
2076 union cvmx_npi_px_dbpair_addr {
2078 struct cvmx_npi_px_dbpair_addr_s {
2079 #ifdef __BIG_ENDIAN_BITFIELD
2080 uint64_t reserved_63_63:1;
2086 uint64_t reserved_63_63:1;
2089 struct cvmx_npi_px_dbpair_addr_s cn30xx;
2090 struct cvmx_npi_px_dbpair_addr_s cn31xx;
2091 struct cvmx_npi_px_dbpair_addr_s cn38xx;
2092 struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
2093 struct cvmx_npi_px_dbpair_addr_s cn50xx;
2094 struct cvmx_npi_px_dbpair_addr_s cn58xx;
2095 struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
2098 union cvmx_npi_px_instr_addr {
2100 struct cvmx_npi_px_instr_addr_s {
2101 #ifdef __BIG_ENDIAN_BITFIELD
2109 struct cvmx_npi_px_instr_addr_s cn30xx;
2110 struct cvmx_npi_px_instr_addr_s cn31xx;
2111 struct cvmx_npi_px_instr_addr_s cn38xx;
2112 struct cvmx_npi_px_instr_addr_s cn38xxp2;
2113 struct cvmx_npi_px_instr_addr_s cn50xx;
2114 struct cvmx_npi_px_instr_addr_s cn58xx;
2115 struct cvmx_npi_px_instr_addr_s cn58xxp1;
2118 union cvmx_npi_px_instr_cnts {
2120 struct cvmx_npi_px_instr_cnts_s {
2121 #ifdef __BIG_ENDIAN_BITFIELD
2122 uint64_t reserved_38_63:26;
2128 uint64_t reserved_38_63:26;
2131 struct cvmx_npi_px_instr_cnts_s cn30xx;
2132 struct cvmx_npi_px_instr_cnts_s cn31xx;
2133 struct cvmx_npi_px_instr_cnts_s cn38xx;
2134 struct cvmx_npi_px_instr_cnts_s cn38xxp2;
2135 struct cvmx_npi_px_instr_cnts_s cn50xx;
2136 struct cvmx_npi_px_instr_cnts_s cn58xx;
2137 struct cvmx_npi_px_instr_cnts_s cn58xxp1;
2140 union cvmx_npi_px_pair_cnts {
2142 struct cvmx_npi_px_pair_cnts_s {
2143 #ifdef __BIG_ENDIAN_BITFIELD
2144 uint64_t reserved_37_63:27;
2150 uint64_t reserved_37_63:27;
2153 struct cvmx_npi_px_pair_cnts_s cn30xx;
2154 struct cvmx_npi_px_pair_cnts_s cn31xx;
2155 struct cvmx_npi_px_pair_cnts_s cn38xx;
2156 struct cvmx_npi_px_pair_cnts_s cn38xxp2;
2157 struct cvmx_npi_px_pair_cnts_s cn50xx;
2158 struct cvmx_npi_px_pair_cnts_s cn58xx;
2159 struct cvmx_npi_px_pair_cnts_s cn58xxp1;
2162 union cvmx_npi_pci_burst_size {
2164 struct cvmx_npi_pci_burst_size_s {
2165 #ifdef __BIG_ENDIAN_BITFIELD
2166 uint64_t reserved_14_63:50;
2172 uint64_t reserved_14_63:50;
2175 struct cvmx_npi_pci_burst_size_s cn30xx;
2176 struct cvmx_npi_pci_burst_size_s cn31xx;
2177 struct cvmx_npi_pci_burst_size_s cn38xx;
2178 struct cvmx_npi_pci_burst_size_s cn38xxp2;
2179 struct cvmx_npi_pci_burst_size_s cn50xx;
2180 struct cvmx_npi_pci_burst_size_s cn58xx;
2181 struct cvmx_npi_pci_burst_size_s cn58xxp1;
2184 union cvmx_npi_pci_int_arb_cfg {
2186 struct cvmx_npi_pci_int_arb_cfg_s {
2187 #ifdef __BIG_ENDIAN_BITFIELD
2188 uint64_t reserved_13_63:51;
2189 uint64_t hostmode:1;
2191 uint64_t reserved_5_7:3;
2193 uint64_t park_mod:1;
2194 uint64_t park_dev:3;
2196 uint64_t park_dev:3;
2197 uint64_t park_mod:1;
2199 uint64_t reserved_5_7:3;
2201 uint64_t hostmode:1;
2202 uint64_t reserved_13_63:51;
2205 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
2206 #ifdef __BIG_ENDIAN_BITFIELD
2207 uint64_t reserved_5_63:59;
2209 uint64_t park_mod:1;
2210 uint64_t park_dev:3;
2212 uint64_t park_dev:3;
2213 uint64_t park_mod:1;
2215 uint64_t reserved_5_63:59;
2218 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
2219 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
2220 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
2221 struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
2222 struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
2223 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
2226 union cvmx_npi_pci_read_cmd {
2228 struct cvmx_npi_pci_read_cmd_s {
2229 #ifdef __BIG_ENDIAN_BITFIELD
2230 uint64_t reserved_11_63:53;
2231 uint64_t cmd_size:11;
2233 uint64_t cmd_size:11;
2234 uint64_t reserved_11_63:53;
2237 struct cvmx_npi_pci_read_cmd_s cn30xx;
2238 struct cvmx_npi_pci_read_cmd_s cn31xx;
2239 struct cvmx_npi_pci_read_cmd_s cn38xx;
2240 struct cvmx_npi_pci_read_cmd_s cn38xxp2;
2241 struct cvmx_npi_pci_read_cmd_s cn50xx;
2242 struct cvmx_npi_pci_read_cmd_s cn58xx;
2243 struct cvmx_npi_pci_read_cmd_s cn58xxp1;
2246 union cvmx_npi_port32_instr_hdr {
2248 struct cvmx_npi_port32_instr_hdr_s {
2249 #ifdef __BIG_ENDIAN_BITFIELD
2250 uint64_t reserved_44_63:20;
2253 uint64_t rparmode:2;
2255 uint64_t rskp_len:7;
2257 uint64_t use_ihdr:1;
2259 uint64_t par_mode:2;
2267 uint64_t par_mode:2;
2269 uint64_t use_ihdr:1;
2271 uint64_t rskp_len:7;
2273 uint64_t rparmode:2;
2276 uint64_t reserved_44_63:20;
2279 struct cvmx_npi_port32_instr_hdr_s cn30xx;
2280 struct cvmx_npi_port32_instr_hdr_s cn31xx;
2281 struct cvmx_npi_port32_instr_hdr_s cn38xx;
2282 struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
2283 struct cvmx_npi_port32_instr_hdr_s cn50xx;
2284 struct cvmx_npi_port32_instr_hdr_s cn58xx;
2285 struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
2288 union cvmx_npi_port33_instr_hdr {
2290 struct cvmx_npi_port33_instr_hdr_s {
2291 #ifdef __BIG_ENDIAN_BITFIELD
2292 uint64_t reserved_44_63:20;
2295 uint64_t rparmode:2;
2297 uint64_t rskp_len:7;
2299 uint64_t use_ihdr:1;
2301 uint64_t par_mode:2;
2309 uint64_t par_mode:2;
2311 uint64_t use_ihdr:1;
2313 uint64_t rskp_len:7;
2315 uint64_t rparmode:2;
2318 uint64_t reserved_44_63:20;
2321 struct cvmx_npi_port33_instr_hdr_s cn31xx;
2322 struct cvmx_npi_port33_instr_hdr_s cn38xx;
2323 struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
2324 struct cvmx_npi_port33_instr_hdr_s cn50xx;
2325 struct cvmx_npi_port33_instr_hdr_s cn58xx;
2326 struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
2329 union cvmx_npi_port34_instr_hdr {
2331 struct cvmx_npi_port34_instr_hdr_s {
2332 #ifdef __BIG_ENDIAN_BITFIELD
2333 uint64_t reserved_44_63:20;
2336 uint64_t rparmode:2;
2338 uint64_t rskp_len:7;
2340 uint64_t use_ihdr:1;
2342 uint64_t par_mode:2;
2350 uint64_t par_mode:2;
2352 uint64_t use_ihdr:1;
2354 uint64_t rskp_len:7;
2356 uint64_t rparmode:2;
2359 uint64_t reserved_44_63:20;
2362 struct cvmx_npi_port34_instr_hdr_s cn38xx;
2363 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
2364 struct cvmx_npi_port34_instr_hdr_s cn58xx;
2365 struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
2368 union cvmx_npi_port35_instr_hdr {
2370 struct cvmx_npi_port35_instr_hdr_s {
2371 #ifdef __BIG_ENDIAN_BITFIELD
2372 uint64_t reserved_44_63:20;
2375 uint64_t rparmode:2;
2377 uint64_t rskp_len:7;
2379 uint64_t use_ihdr:1;
2381 uint64_t par_mode:2;
2389 uint64_t par_mode:2;
2391 uint64_t use_ihdr:1;
2393 uint64_t rskp_len:7;
2395 uint64_t rparmode:2;
2398 uint64_t reserved_44_63:20;
2401 struct cvmx_npi_port35_instr_hdr_s cn38xx;
2402 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
2403 struct cvmx_npi_port35_instr_hdr_s cn58xx;
2404 struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
2407 union cvmx_npi_port_bp_control {
2409 struct cvmx_npi_port_bp_control_s {
2410 #ifdef __BIG_ENDIAN_BITFIELD
2411 uint64_t reserved_8_63:56;
2417 uint64_t reserved_8_63:56;
2420 struct cvmx_npi_port_bp_control_s cn30xx;
2421 struct cvmx_npi_port_bp_control_s cn31xx;
2422 struct cvmx_npi_port_bp_control_s cn38xx;
2423 struct cvmx_npi_port_bp_control_s cn38xxp2;
2424 struct cvmx_npi_port_bp_control_s cn50xx;
2425 struct cvmx_npi_port_bp_control_s cn58xx;
2426 struct cvmx_npi_port_bp_control_s cn58xxp1;
2429 union cvmx_npi_rsl_int_blocks {
2431 struct cvmx_npi_rsl_int_blocks_s {
2432 #ifdef __BIG_ENDIAN_BITFIELD
2433 uint64_t reserved_32_63:32;
2436 uint64_t reserved_28_29:2;
2450 uint64_t reserved_13_14:2;
2478 uint64_t reserved_13_14:2;
2492 uint64_t reserved_28_29:2;
2495 uint64_t reserved_32_63:32;
2498 struct cvmx_npi_rsl_int_blocks_cn30xx {
2499 #ifdef __BIG_ENDIAN_BITFIELD
2500 uint64_t reserved_32_63:32;
2566 uint64_t reserved_32_63:32;
2569 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
2570 struct cvmx_npi_rsl_int_blocks_cn38xx {
2571 #ifdef __BIG_ENDIAN_BITFIELD
2572 uint64_t reserved_32_63:32;
2638 uint64_t reserved_32_63:32;
2641 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
2642 struct cvmx_npi_rsl_int_blocks_cn50xx {
2643 #ifdef __BIG_ENDIAN_BITFIELD
2644 uint64_t reserved_31_63:33;
2648 uint64_t reserved_24_27:4;
2651 uint64_t reserved_21_21:1;
2657 uint64_t reserved_15_15:1;
2664 uint64_t reserved_8_8:1;
2682 uint64_t reserved_8_8:1;
2689 uint64_t reserved_15_15:1;
2695 uint64_t reserved_21_21:1;
2698 uint64_t reserved_24_27:4;
2702 uint64_t reserved_31_63:33;
2705 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
2706 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
2709 union cvmx_npi_size_inputx {
2711 struct cvmx_npi_size_inputx_s {
2712 #ifdef __BIG_ENDIAN_BITFIELD
2713 uint64_t reserved_32_63:32;
2717 uint64_t reserved_32_63:32;
2720 struct cvmx_npi_size_inputx_s cn30xx;
2721 struct cvmx_npi_size_inputx_s cn31xx;
2722 struct cvmx_npi_size_inputx_s cn38xx;
2723 struct cvmx_npi_size_inputx_s cn38xxp2;
2724 struct cvmx_npi_size_inputx_s cn50xx;
2725 struct cvmx_npi_size_inputx_s cn58xx;
2726 struct cvmx_npi_size_inputx_s cn58xxp1;
2729 union cvmx_npi_win_read_to {
2731 struct cvmx_npi_win_read_to_s {
2732 #ifdef __BIG_ENDIAN_BITFIELD
2733 uint64_t reserved_32_63:32;
2737 uint64_t reserved_32_63:32;
2740 struct cvmx_npi_win_read_to_s cn30xx;
2741 struct cvmx_npi_win_read_to_s cn31xx;
2742 struct cvmx_npi_win_read_to_s cn38xx;
2743 struct cvmx_npi_win_read_to_s cn38xxp2;
2744 struct cvmx_npi_win_read_to_s cn50xx;
2745 struct cvmx_npi_win_read_to_s cn58xx;
2746 struct cvmx_npi_win_read_to_s cn58xxp1;