1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_NPEI_DEFS_H__
29 #define __CVMX_NPEI_DEFS_H__
31 #define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
32 #define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
33 #define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
34 #define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
35 #define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
36 #define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
37 #define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
38 #define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
39 #define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
40 #define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
41 #define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
42 #define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
43 #define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
44 #define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
45 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
46 #define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
47 #define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
48 #define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
49 #define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
50 #define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
51 #define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
52 #define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
53 #define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
54 #define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
55 #define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
56 #define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
57 #define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
58 #define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
59 #define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
60 #define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
61 #define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
62 #define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
63 #define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
64 #define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
65 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
69 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
72 #define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
73 #define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
74 #define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
75 #define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
76 #define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
77 #define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
78 #define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
79 #define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
80 #define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
81 #define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
82 #define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
83 #define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
84 #define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
85 #define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
86 #define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
87 #define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
88 #define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
89 #define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
90 #define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
91 #define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
92 #define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
93 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
94 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
95 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
96 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
97 #define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
98 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
99 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
100 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
101 #define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
102 #define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
103 #define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
104 #define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
105 #define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
106 #define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
107 #define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
108 #define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
109 #define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
110 #define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
111 #define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
112 #define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
113 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
114 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
115 #define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
116 #define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
117 #define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
118 #define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
119 #define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
120 #define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
121 #define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
122 #define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
123 #define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
124 #define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
125 #define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
126 #define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
127 #define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
128 #define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
129 #define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
130 #define CVMX_NPEI_STATE1 (0x0000000000000620ull)
131 #define CVMX_NPEI_STATE2 (0x0000000000000630ull)
132 #define CVMX_NPEI_STATE3 (0x0000000000000640ull)
133 #define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
134 #define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
135 #define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
136 #define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
137 #define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
138 #define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
140 union cvmx_npei_bar1_indexx {
142 struct cvmx_npei_bar1_indexx_s {
143 #ifdef __BIG_ENDIAN_BITFIELD
144 uint32_t reserved_18_31:14;
145 uint32_t addr_idx:14;
153 uint32_t addr_idx:14;
154 uint32_t reserved_18_31:14;
157 struct cvmx_npei_bar1_indexx_s cn52xx;
158 struct cvmx_npei_bar1_indexx_s cn52xxp1;
159 struct cvmx_npei_bar1_indexx_s cn56xx;
160 struct cvmx_npei_bar1_indexx_s cn56xxp1;
163 union cvmx_npei_bist_status {
165 struct cvmx_npei_bist_status_s {
166 #ifdef __BIG_ENDIAN_BITFIELD
168 uint64_t reserved_60_62:3;
176 uint64_t reserved_50_52:3;
179 uint64_t reserved_36_47:12;
184 uint64_t reserved_31_31:1;
213 uint64_t reserved_2_2:1;
219 uint64_t reserved_2_2:1;
248 uint64_t reserved_31_31:1;
253 uint64_t reserved_36_47:12;
256 uint64_t reserved_50_52:3;
264 uint64_t reserved_60_62:3;
268 struct cvmx_npei_bist_status_cn52xx {
269 #ifdef __BIG_ENDIAN_BITFIELD
271 uint64_t reserved_60_62:3;
282 uint64_t reserved_48_49:2;
291 uint64_t reserved_36_39:4;
365 uint64_t reserved_36_39:4;
374 uint64_t reserved_48_49:2;
385 uint64_t reserved_60_62:3;
389 struct cvmx_npei_bist_status_cn52xxp1 {
390 #ifdef __BIG_ENDIAN_BITFIELD
391 uint64_t reserved_46_63:18;
485 uint64_t reserved_46_63:18;
488 struct cvmx_npei_bist_status_cn52xx cn56xx;
489 struct cvmx_npei_bist_status_cn56xxp1 {
490 #ifdef __BIG_ENDIAN_BITFIELD
491 uint64_t reserved_58_63:6;
609 uint64_t reserved_58_63:6;
614 union cvmx_npei_bist_status2 {
616 struct cvmx_npei_bist_status2_s {
617 #ifdef __BIG_ENDIAN_BITFIELD
618 uint64_t reserved_14_63:50;
648 uint64_t reserved_14_63:50;
651 struct cvmx_npei_bist_status2_s cn52xx;
652 struct cvmx_npei_bist_status2_s cn56xx;
655 union cvmx_npei_ctl_port0 {
657 struct cvmx_npei_ctl_port0_s {
658 #ifdef __BIG_ENDIAN_BITFIELD
659 uint64_t reserved_21_63:43;
660 uint64_t waitl_com:1;
670 uint64_t reserved_6_6:1;
682 uint64_t reserved_6_6:1;
692 uint64_t waitl_com:1;
693 uint64_t reserved_21_63:43;
696 struct cvmx_npei_ctl_port0_s cn52xx;
697 struct cvmx_npei_ctl_port0_s cn52xxp1;
698 struct cvmx_npei_ctl_port0_s cn56xx;
699 struct cvmx_npei_ctl_port0_s cn56xxp1;
702 union cvmx_npei_ctl_port1 {
704 struct cvmx_npei_ctl_port1_s {
705 #ifdef __BIG_ENDIAN_BITFIELD
706 uint64_t reserved_21_63:43;
707 uint64_t waitl_com:1;
717 uint64_t reserved_6_6:1;
729 uint64_t reserved_6_6:1;
739 uint64_t waitl_com:1;
740 uint64_t reserved_21_63:43;
743 struct cvmx_npei_ctl_port1_s cn52xx;
744 struct cvmx_npei_ctl_port1_s cn52xxp1;
745 struct cvmx_npei_ctl_port1_s cn56xx;
746 struct cvmx_npei_ctl_port1_s cn56xxp1;
749 union cvmx_npei_ctl_status {
751 struct cvmx_npei_ctl_status_s {
752 #ifdef __BIG_ENDIAN_BITFIELD
753 uint64_t reserved_44_63:20;
756 uint64_t cfg_rtry:16;
761 uint64_t host_mode:1;
765 uint64_t host_mode:1;
770 uint64_t cfg_rtry:16;
773 uint64_t reserved_44_63:20;
776 struct cvmx_npei_ctl_status_s cn52xx;
777 struct cvmx_npei_ctl_status_cn52xxp1 {
778 #ifdef __BIG_ENDIAN_BITFIELD
779 uint64_t reserved_44_63:20;
782 uint64_t cfg_rtry:16;
783 uint64_t reserved_15_15:1;
786 uint64_t reserved_9_12:4;
787 uint64_t host_mode:1;
791 uint64_t host_mode:1;
792 uint64_t reserved_9_12:4;
795 uint64_t reserved_15_15:1;
796 uint64_t cfg_rtry:16;
799 uint64_t reserved_44_63:20;
802 struct cvmx_npei_ctl_status_s cn56xx;
803 struct cvmx_npei_ctl_status_cn56xxp1 {
804 #ifdef __BIG_ENDIAN_BITFIELD
805 uint64_t reserved_15_63:49;
809 uint64_t host_mode:1;
813 uint64_t host_mode:1;
817 uint64_t reserved_15_63:49;
822 union cvmx_npei_ctl_status2 {
824 struct cvmx_npei_ctl_status2_s {
825 #ifdef __BIG_ENDIAN_BITFIELD
826 uint64_t reserved_16_63:48;
848 uint64_t reserved_16_63:48;
851 struct cvmx_npei_ctl_status2_s cn52xx;
852 struct cvmx_npei_ctl_status2_s cn52xxp1;
853 struct cvmx_npei_ctl_status2_s cn56xx;
854 struct cvmx_npei_ctl_status2_s cn56xxp1;
857 union cvmx_npei_data_out_cnt {
859 struct cvmx_npei_data_out_cnt_s {
860 #ifdef __BIG_ENDIAN_BITFIELD
861 uint64_t reserved_44_63:20;
871 uint64_t reserved_44_63:20;
874 struct cvmx_npei_data_out_cnt_s cn52xx;
875 struct cvmx_npei_data_out_cnt_s cn52xxp1;
876 struct cvmx_npei_data_out_cnt_s cn56xx;
877 struct cvmx_npei_data_out_cnt_s cn56xxp1;
880 union cvmx_npei_dbg_data {
882 struct cvmx_npei_dbg_data_s {
883 #ifdef __BIG_ENDIAN_BITFIELD
884 uint64_t reserved_28_63:36;
885 uint64_t qlm0_rev_lanes:1;
886 uint64_t reserved_25_26:2;
896 uint64_t reserved_25_26:2;
897 uint64_t qlm0_rev_lanes:1;
898 uint64_t reserved_28_63:36;
901 struct cvmx_npei_dbg_data_cn52xx {
902 #ifdef __BIG_ENDIAN_BITFIELD
903 uint64_t reserved_29_63:35;
904 uint64_t qlm0_link_width:1;
905 uint64_t qlm0_rev_lanes:1;
906 uint64_t qlm1_mode:2;
916 uint64_t qlm1_mode:2;
917 uint64_t qlm0_rev_lanes:1;
918 uint64_t qlm0_link_width:1;
919 uint64_t reserved_29_63:35;
922 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
923 struct cvmx_npei_dbg_data_cn56xx {
924 #ifdef __BIG_ENDIAN_BITFIELD
925 uint64_t reserved_29_63:35;
926 uint64_t qlm2_rev_lanes:1;
927 uint64_t qlm0_rev_lanes:1;
939 uint64_t qlm0_rev_lanes:1;
940 uint64_t qlm2_rev_lanes:1;
941 uint64_t reserved_29_63:35;
944 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
947 union cvmx_npei_dbg_select {
949 struct cvmx_npei_dbg_select_s {
950 #ifdef __BIG_ENDIAN_BITFIELD
951 uint64_t reserved_16_63:48;
955 uint64_t reserved_16_63:48;
958 struct cvmx_npei_dbg_select_s cn52xx;
959 struct cvmx_npei_dbg_select_s cn52xxp1;
960 struct cvmx_npei_dbg_select_s cn56xx;
961 struct cvmx_npei_dbg_select_s cn56xxp1;
964 union cvmx_npei_dmax_counts {
966 struct cvmx_npei_dmax_counts_s {
967 #ifdef __BIG_ENDIAN_BITFIELD
968 uint64_t reserved_39_63:25;
974 uint64_t reserved_39_63:25;
977 struct cvmx_npei_dmax_counts_s cn52xx;
978 struct cvmx_npei_dmax_counts_s cn52xxp1;
979 struct cvmx_npei_dmax_counts_s cn56xx;
980 struct cvmx_npei_dmax_counts_s cn56xxp1;
983 union cvmx_npei_dmax_dbell {
985 struct cvmx_npei_dmax_dbell_s {
986 #ifdef __BIG_ENDIAN_BITFIELD
987 uint32_t reserved_16_31:16;
991 uint32_t reserved_16_31:16;
994 struct cvmx_npei_dmax_dbell_s cn52xx;
995 struct cvmx_npei_dmax_dbell_s cn52xxp1;
996 struct cvmx_npei_dmax_dbell_s cn56xx;
997 struct cvmx_npei_dmax_dbell_s cn56xxp1;
1000 union cvmx_npei_dmax_ibuff_saddr {
1002 struct cvmx_npei_dmax_ibuff_saddr_s {
1003 #ifdef __BIG_ENDIAN_BITFIELD
1004 uint64_t reserved_37_63:27;
1007 uint64_t reserved_0_6:7;
1009 uint64_t reserved_0_6:7;
1012 uint64_t reserved_37_63:27;
1015 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
1016 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
1017 #ifdef __BIG_ENDIAN_BITFIELD
1018 uint64_t reserved_36_63:28;
1020 uint64_t reserved_0_6:7;
1022 uint64_t reserved_0_6:7;
1024 uint64_t reserved_36_63:28;
1027 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
1028 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
1031 union cvmx_npei_dmax_naddr {
1033 struct cvmx_npei_dmax_naddr_s {
1034 #ifdef __BIG_ENDIAN_BITFIELD
1035 uint64_t reserved_36_63:28;
1039 uint64_t reserved_36_63:28;
1042 struct cvmx_npei_dmax_naddr_s cn52xx;
1043 struct cvmx_npei_dmax_naddr_s cn52xxp1;
1044 struct cvmx_npei_dmax_naddr_s cn56xx;
1045 struct cvmx_npei_dmax_naddr_s cn56xxp1;
1048 union cvmx_npei_dma0_int_level {
1050 struct cvmx_npei_dma0_int_level_s {
1051 #ifdef __BIG_ENDIAN_BITFIELD
1059 struct cvmx_npei_dma0_int_level_s cn52xx;
1060 struct cvmx_npei_dma0_int_level_s cn52xxp1;
1061 struct cvmx_npei_dma0_int_level_s cn56xx;
1062 struct cvmx_npei_dma0_int_level_s cn56xxp1;
1065 union cvmx_npei_dma1_int_level {
1067 struct cvmx_npei_dma1_int_level_s {
1068 #ifdef __BIG_ENDIAN_BITFIELD
1076 struct cvmx_npei_dma1_int_level_s cn52xx;
1077 struct cvmx_npei_dma1_int_level_s cn52xxp1;
1078 struct cvmx_npei_dma1_int_level_s cn56xx;
1079 struct cvmx_npei_dma1_int_level_s cn56xxp1;
1082 union cvmx_npei_dma_cnts {
1084 struct cvmx_npei_dma_cnts_s {
1085 #ifdef __BIG_ENDIAN_BITFIELD
1093 struct cvmx_npei_dma_cnts_s cn52xx;
1094 struct cvmx_npei_dma_cnts_s cn52xxp1;
1095 struct cvmx_npei_dma_cnts_s cn56xx;
1096 struct cvmx_npei_dma_cnts_s cn56xxp1;
1099 union cvmx_npei_dma_control {
1101 struct cvmx_npei_dma_control_s {
1102 #ifdef __BIG_ENDIAN_BITFIELD
1103 uint64_t reserved_40_63:24;
1105 uint64_t dma4_enb:1;
1106 uint64_t dma3_enb:1;
1107 uint64_t dma2_enb:1;
1108 uint64_t dma1_enb:1;
1109 uint64_t dma0_enb:1;
1111 uint64_t dwb_denb:1;
1112 uint64_t dwb_ichk:9;
1128 uint64_t dwb_ichk:9;
1129 uint64_t dwb_denb:1;
1131 uint64_t dma0_enb:1;
1132 uint64_t dma1_enb:1;
1133 uint64_t dma2_enb:1;
1134 uint64_t dma3_enb:1;
1135 uint64_t dma4_enb:1;
1137 uint64_t reserved_40_63:24;
1140 struct cvmx_npei_dma_control_s cn52xx;
1141 struct cvmx_npei_dma_control_cn52xxp1 {
1142 #ifdef __BIG_ENDIAN_BITFIELD
1143 uint64_t reserved_38_63:26;
1144 uint64_t dma3_enb:1;
1145 uint64_t dma2_enb:1;
1146 uint64_t dma1_enb:1;
1147 uint64_t dma0_enb:1;
1149 uint64_t dwb_denb:1;
1150 uint64_t dwb_ichk:9;
1166 uint64_t dwb_ichk:9;
1167 uint64_t dwb_denb:1;
1169 uint64_t dma0_enb:1;
1170 uint64_t dma1_enb:1;
1171 uint64_t dma2_enb:1;
1172 uint64_t dma3_enb:1;
1173 uint64_t reserved_38_63:26;
1176 struct cvmx_npei_dma_control_s cn56xx;
1177 struct cvmx_npei_dma_control_cn56xxp1 {
1178 #ifdef __BIG_ENDIAN_BITFIELD
1179 uint64_t reserved_39_63:25;
1180 uint64_t dma4_enb:1;
1181 uint64_t dma3_enb:1;
1182 uint64_t dma2_enb:1;
1183 uint64_t dma1_enb:1;
1184 uint64_t dma0_enb:1;
1186 uint64_t dwb_denb:1;
1187 uint64_t dwb_ichk:9;
1203 uint64_t dwb_ichk:9;
1204 uint64_t dwb_denb:1;
1206 uint64_t dma0_enb:1;
1207 uint64_t dma1_enb:1;
1208 uint64_t dma2_enb:1;
1209 uint64_t dma3_enb:1;
1210 uint64_t dma4_enb:1;
1211 uint64_t reserved_39_63:25;
1216 union cvmx_npei_dma_pcie_req_num {
1218 struct cvmx_npei_dma_pcie_req_num_s {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1221 uint64_t reserved_53_62:10;
1223 uint64_t reserved_45_47:3;
1224 uint64_t dma4_cnt:5;
1225 uint64_t reserved_37_39:3;
1226 uint64_t dma3_cnt:5;
1227 uint64_t reserved_29_31:3;
1228 uint64_t dma2_cnt:5;
1229 uint64_t reserved_21_23:3;
1230 uint64_t dma1_cnt:5;
1231 uint64_t reserved_13_15:3;
1232 uint64_t dma0_cnt:5;
1233 uint64_t reserved_5_7:3;
1237 uint64_t reserved_5_7:3;
1238 uint64_t dma0_cnt:5;
1239 uint64_t reserved_13_15:3;
1240 uint64_t dma1_cnt:5;
1241 uint64_t reserved_21_23:3;
1242 uint64_t dma2_cnt:5;
1243 uint64_t reserved_29_31:3;
1244 uint64_t dma3_cnt:5;
1245 uint64_t reserved_37_39:3;
1246 uint64_t dma4_cnt:5;
1247 uint64_t reserved_45_47:3;
1249 uint64_t reserved_53_62:10;
1253 struct cvmx_npei_dma_pcie_req_num_s cn52xx;
1254 struct cvmx_npei_dma_pcie_req_num_s cn56xx;
1257 union cvmx_npei_dma_state1 {
1259 struct cvmx_npei_dma_state1_s {
1260 #ifdef __BIG_ENDIAN_BITFIELD
1261 uint64_t reserved_40_63:24;
1273 uint64_t reserved_40_63:24;
1276 struct cvmx_npei_dma_state1_s cn52xx;
1279 union cvmx_npei_dma_state1_p1 {
1281 struct cvmx_npei_dma_state1_p1_s {
1282 #ifdef __BIG_ENDIAN_BITFIELD
1283 uint64_t reserved_60_63:4;
1284 uint64_t d0_difst:7;
1285 uint64_t d1_difst:7;
1286 uint64_t d2_difst:7;
1287 uint64_t d3_difst:7;
1288 uint64_t d4_difst:7;
1289 uint64_t d0_reqst:5;
1290 uint64_t d1_reqst:5;
1291 uint64_t d2_reqst:5;
1292 uint64_t d3_reqst:5;
1293 uint64_t d4_reqst:5;
1295 uint64_t d4_reqst:5;
1296 uint64_t d3_reqst:5;
1297 uint64_t d2_reqst:5;
1298 uint64_t d1_reqst:5;
1299 uint64_t d0_reqst:5;
1300 uint64_t d4_difst:7;
1301 uint64_t d3_difst:7;
1302 uint64_t d2_difst:7;
1303 uint64_t d1_difst:7;
1304 uint64_t d0_difst:7;
1305 uint64_t reserved_60_63:4;
1308 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
1309 #ifdef __BIG_ENDIAN_BITFIELD
1310 uint64_t reserved_60_63:4;
1311 uint64_t d0_difst:7;
1312 uint64_t d1_difst:7;
1313 uint64_t d2_difst:7;
1314 uint64_t d3_difst:7;
1315 uint64_t reserved_25_31:7;
1316 uint64_t d0_reqst:5;
1317 uint64_t d1_reqst:5;
1318 uint64_t d2_reqst:5;
1319 uint64_t d3_reqst:5;
1320 uint64_t reserved_0_4:5;
1322 uint64_t reserved_0_4:5;
1323 uint64_t d3_reqst:5;
1324 uint64_t d2_reqst:5;
1325 uint64_t d1_reqst:5;
1326 uint64_t d0_reqst:5;
1327 uint64_t reserved_25_31:7;
1328 uint64_t d3_difst:7;
1329 uint64_t d2_difst:7;
1330 uint64_t d1_difst:7;
1331 uint64_t d0_difst:7;
1332 uint64_t reserved_60_63:4;
1335 struct cvmx_npei_dma_state1_p1_s cn56xxp1;
1338 union cvmx_npei_dma_state2 {
1340 struct cvmx_npei_dma_state2_s {
1341 #ifdef __BIG_ENDIAN_BITFIELD
1342 uint64_t reserved_28_63:36;
1344 uint64_t reserved_21_23:3;
1346 uint64_t reserved_10_15:6;
1350 uint64_t reserved_10_15:6;
1352 uint64_t reserved_21_23:3;
1354 uint64_t reserved_28_63:36;
1357 struct cvmx_npei_dma_state2_s cn52xx;
1360 union cvmx_npei_dma_state2_p1 {
1362 struct cvmx_npei_dma_state2_p1_s {
1363 #ifdef __BIG_ENDIAN_BITFIELD
1364 uint64_t reserved_45_63:19;
1365 uint64_t d0_dffst:9;
1366 uint64_t d1_dffst:9;
1367 uint64_t d2_dffst:9;
1368 uint64_t d3_dffst:9;
1369 uint64_t d4_dffst:9;
1371 uint64_t d4_dffst:9;
1372 uint64_t d3_dffst:9;
1373 uint64_t d2_dffst:9;
1374 uint64_t d1_dffst:9;
1375 uint64_t d0_dffst:9;
1376 uint64_t reserved_45_63:19;
1379 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
1380 #ifdef __BIG_ENDIAN_BITFIELD
1381 uint64_t reserved_45_63:19;
1382 uint64_t d0_dffst:9;
1383 uint64_t d1_dffst:9;
1384 uint64_t d2_dffst:9;
1385 uint64_t d3_dffst:9;
1386 uint64_t reserved_0_8:9;
1388 uint64_t reserved_0_8:9;
1389 uint64_t d3_dffst:9;
1390 uint64_t d2_dffst:9;
1391 uint64_t d1_dffst:9;
1392 uint64_t d0_dffst:9;
1393 uint64_t reserved_45_63:19;
1396 struct cvmx_npei_dma_state2_p1_s cn56xxp1;
1399 union cvmx_npei_dma_state3_p1 {
1401 struct cvmx_npei_dma_state3_p1_s {
1402 #ifdef __BIG_ENDIAN_BITFIELD
1403 uint64_t reserved_60_63:4;
1404 uint64_t d0_drest:15;
1405 uint64_t d1_drest:15;
1406 uint64_t d2_drest:15;
1407 uint64_t d3_drest:15;
1409 uint64_t d3_drest:15;
1410 uint64_t d2_drest:15;
1411 uint64_t d1_drest:15;
1412 uint64_t d0_drest:15;
1413 uint64_t reserved_60_63:4;
1416 struct cvmx_npei_dma_state3_p1_s cn52xxp1;
1417 struct cvmx_npei_dma_state3_p1_s cn56xxp1;
1420 union cvmx_npei_dma_state4_p1 {
1422 struct cvmx_npei_dma_state4_p1_s {
1423 #ifdef __BIG_ENDIAN_BITFIELD
1424 uint64_t reserved_52_63:12;
1425 uint64_t d0_dwest:13;
1426 uint64_t d1_dwest:13;
1427 uint64_t d2_dwest:13;
1428 uint64_t d3_dwest:13;
1430 uint64_t d3_dwest:13;
1431 uint64_t d2_dwest:13;
1432 uint64_t d1_dwest:13;
1433 uint64_t d0_dwest:13;
1434 uint64_t reserved_52_63:12;
1437 struct cvmx_npei_dma_state4_p1_s cn52xxp1;
1438 struct cvmx_npei_dma_state4_p1_s cn56xxp1;
1441 union cvmx_npei_dma_state5_p1 {
1443 struct cvmx_npei_dma_state5_p1_s {
1444 #ifdef __BIG_ENDIAN_BITFIELD
1445 uint64_t reserved_28_63:36;
1446 uint64_t d4_drest:15;
1447 uint64_t d4_dwest:13;
1449 uint64_t d4_dwest:13;
1450 uint64_t d4_drest:15;
1451 uint64_t reserved_28_63:36;
1454 struct cvmx_npei_dma_state5_p1_s cn56xxp1;
1457 union cvmx_npei_int_a_enb {
1459 struct cvmx_npei_int_a_enb_s {
1460 #ifdef __BIG_ENDIAN_BITFIELD
1461 uint64_t reserved_10_63:54;
1462 uint64_t pout_err:1;
1469 uint64_t pins_err:1;
1470 uint64_t dma1_cpl:1;
1471 uint64_t dma0_cpl:1;
1473 uint64_t dma0_cpl:1;
1474 uint64_t dma1_cpl:1;
1475 uint64_t pins_err:1;
1482 uint64_t pout_err:1;
1483 uint64_t reserved_10_63:54;
1486 struct cvmx_npei_int_a_enb_s cn52xx;
1487 struct cvmx_npei_int_a_enb_cn52xxp1 {
1488 #ifdef __BIG_ENDIAN_BITFIELD
1489 uint64_t reserved_2_63:62;
1490 uint64_t dma1_cpl:1;
1491 uint64_t dma0_cpl:1;
1493 uint64_t dma0_cpl:1;
1494 uint64_t dma1_cpl:1;
1495 uint64_t reserved_2_63:62;
1498 struct cvmx_npei_int_a_enb_s cn56xx;
1501 union cvmx_npei_int_a_enb2 {
1503 struct cvmx_npei_int_a_enb2_s {
1504 #ifdef __BIG_ENDIAN_BITFIELD
1505 uint64_t reserved_10_63:54;
1506 uint64_t pout_err:1;
1513 uint64_t pins_err:1;
1514 uint64_t dma1_cpl:1;
1515 uint64_t dma0_cpl:1;
1517 uint64_t dma0_cpl:1;
1518 uint64_t dma1_cpl:1;
1519 uint64_t pins_err:1;
1526 uint64_t pout_err:1;
1527 uint64_t reserved_10_63:54;
1530 struct cvmx_npei_int_a_enb2_s cn52xx;
1531 struct cvmx_npei_int_a_enb2_cn52xxp1 {
1532 #ifdef __BIG_ENDIAN_BITFIELD
1533 uint64_t reserved_2_63:62;
1534 uint64_t dma1_cpl:1;
1535 uint64_t dma0_cpl:1;
1537 uint64_t dma0_cpl:1;
1538 uint64_t dma1_cpl:1;
1539 uint64_t reserved_2_63:62;
1542 struct cvmx_npei_int_a_enb2_s cn56xx;
1545 union cvmx_npei_int_a_sum {
1547 struct cvmx_npei_int_a_sum_s {
1548 #ifdef __BIG_ENDIAN_BITFIELD
1549 uint64_t reserved_10_63:54;
1550 uint64_t pout_err:1;
1557 uint64_t pins_err:1;
1558 uint64_t dma1_cpl:1;
1559 uint64_t dma0_cpl:1;
1561 uint64_t dma0_cpl:1;
1562 uint64_t dma1_cpl:1;
1563 uint64_t pins_err:1;
1570 uint64_t pout_err:1;
1571 uint64_t reserved_10_63:54;
1574 struct cvmx_npei_int_a_sum_s cn52xx;
1575 struct cvmx_npei_int_a_sum_cn52xxp1 {
1576 #ifdef __BIG_ENDIAN_BITFIELD
1577 uint64_t reserved_2_63:62;
1578 uint64_t dma1_cpl:1;
1579 uint64_t dma0_cpl:1;
1581 uint64_t dma0_cpl:1;
1582 uint64_t dma1_cpl:1;
1583 uint64_t reserved_2_63:62;
1586 struct cvmx_npei_int_a_sum_s cn56xx;
1589 union cvmx_npei_int_enb {
1591 struct cvmx_npei_int_enb_s {
1592 #ifdef __BIG_ENDIAN_BITFIELD
1593 uint64_t mio_inta:1;
1594 uint64_t reserved_62_62:1;
1600 uint64_t c1_up_wf:1;
1601 uint64_t c0_up_wf:1;
1602 uint64_t c1_un_wf:1;
1603 uint64_t c0_un_wf:1;
1604 uint64_t c1_un_bx:1;
1605 uint64_t c1_un_wi:1;
1606 uint64_t c1_un_b2:1;
1607 uint64_t c1_un_b1:1;
1608 uint64_t c1_un_b0:1;
1609 uint64_t c1_up_bx:1;
1610 uint64_t c1_up_wi:1;
1611 uint64_t c1_up_b2:1;
1612 uint64_t c1_up_b1:1;
1613 uint64_t c1_up_b0:1;
1614 uint64_t c0_un_bx:1;
1615 uint64_t c0_un_wi:1;
1616 uint64_t c0_un_b2:1;
1617 uint64_t c0_un_b1:1;
1618 uint64_t c0_un_b0:1;
1619 uint64_t c0_up_bx:1;
1620 uint64_t c0_up_wi:1;
1621 uint64_t c0_up_b2:1;
1622 uint64_t c0_up_b1:1;
1623 uint64_t c0_up_b0:1;
1624 uint64_t c1_hpint:1;
1631 uint64_t c0_hpint:1;
1683 uint64_t c0_hpint:1;
1690 uint64_t c1_hpint:1;
1691 uint64_t c0_up_b0:1;
1692 uint64_t c0_up_b1:1;
1693 uint64_t c0_up_b2:1;
1694 uint64_t c0_up_wi:1;
1695 uint64_t c0_up_bx:1;
1696 uint64_t c0_un_b0:1;
1697 uint64_t c0_un_b1:1;
1698 uint64_t c0_un_b2:1;
1699 uint64_t c0_un_wi:1;
1700 uint64_t c0_un_bx:1;
1701 uint64_t c1_up_b0:1;
1702 uint64_t c1_up_b1:1;
1703 uint64_t c1_up_b2:1;
1704 uint64_t c1_up_wi:1;
1705 uint64_t c1_up_bx:1;
1706 uint64_t c1_un_b0:1;
1707 uint64_t c1_un_b1:1;
1708 uint64_t c1_un_b2:1;
1709 uint64_t c1_un_wi:1;
1710 uint64_t c1_un_bx:1;
1711 uint64_t c0_un_wf:1;
1712 uint64_t c1_un_wf:1;
1713 uint64_t c0_up_wf:1;
1714 uint64_t c1_up_wf:1;
1720 uint64_t reserved_62_62:1;
1721 uint64_t mio_inta:1;
1724 struct cvmx_npei_int_enb_s cn52xx;
1725 struct cvmx_npei_int_enb_cn52xxp1 {
1726 #ifdef __BIG_ENDIAN_BITFIELD
1727 uint64_t mio_inta:1;
1728 uint64_t reserved_62_62:1;
1734 uint64_t c1_up_wf:1;
1735 uint64_t c0_up_wf:1;
1736 uint64_t c1_un_wf:1;
1737 uint64_t c0_un_wf:1;
1738 uint64_t c1_un_bx:1;
1739 uint64_t c1_un_wi:1;
1740 uint64_t c1_un_b2:1;
1741 uint64_t c1_un_b1:1;
1742 uint64_t c1_un_b0:1;
1743 uint64_t c1_up_bx:1;
1744 uint64_t c1_up_wi:1;
1745 uint64_t c1_up_b2:1;
1746 uint64_t c1_up_b1:1;
1747 uint64_t c1_up_b0:1;
1748 uint64_t c0_un_bx:1;
1749 uint64_t c0_un_wi:1;
1750 uint64_t c0_un_b2:1;
1751 uint64_t c0_un_b1:1;
1752 uint64_t c0_un_b0:1;
1753 uint64_t c0_up_bx:1;
1754 uint64_t c0_up_wi:1;
1755 uint64_t c0_up_b2:1;
1756 uint64_t c0_up_b1:1;
1757 uint64_t c0_up_b0:1;
1758 uint64_t c1_hpint:1;
1765 uint64_t c0_hpint:1;
1782 uint64_t reserved_8_8:1;
1800 uint64_t reserved_8_8:1;
1817 uint64_t c0_hpint:1;
1824 uint64_t c1_hpint:1;
1825 uint64_t c0_up_b0:1;
1826 uint64_t c0_up_b1:1;
1827 uint64_t c0_up_b2:1;
1828 uint64_t c0_up_wi:1;
1829 uint64_t c0_up_bx:1;
1830 uint64_t c0_un_b0:1;
1831 uint64_t c0_un_b1:1;
1832 uint64_t c0_un_b2:1;
1833 uint64_t c0_un_wi:1;
1834 uint64_t c0_un_bx:1;
1835 uint64_t c1_up_b0:1;
1836 uint64_t c1_up_b1:1;
1837 uint64_t c1_up_b2:1;
1838 uint64_t c1_up_wi:1;
1839 uint64_t c1_up_bx:1;
1840 uint64_t c1_un_b0:1;
1841 uint64_t c1_un_b1:1;
1842 uint64_t c1_un_b2:1;
1843 uint64_t c1_un_wi:1;
1844 uint64_t c1_un_bx:1;
1845 uint64_t c0_un_wf:1;
1846 uint64_t c1_un_wf:1;
1847 uint64_t c0_up_wf:1;
1848 uint64_t c1_up_wf:1;
1854 uint64_t reserved_62_62:1;
1855 uint64_t mio_inta:1;
1858 struct cvmx_npei_int_enb_s cn56xx;
1859 struct cvmx_npei_int_enb_cn56xxp1 {
1860 #ifdef __BIG_ENDIAN_BITFIELD
1861 uint64_t mio_inta:1;
1862 uint64_t reserved_61_62:2;
1867 uint64_t c1_up_wf:1;
1868 uint64_t c0_up_wf:1;
1869 uint64_t c1_un_wf:1;
1870 uint64_t c0_un_wf:1;
1871 uint64_t c1_un_bx:1;
1872 uint64_t c1_un_wi:1;
1873 uint64_t c1_un_b2:1;
1874 uint64_t c1_un_b1:1;
1875 uint64_t c1_un_b0:1;
1876 uint64_t c1_up_bx:1;
1877 uint64_t c1_up_wi:1;
1878 uint64_t c1_up_b2:1;
1879 uint64_t c1_up_b1:1;
1880 uint64_t c1_up_b0:1;
1881 uint64_t c0_un_bx:1;
1882 uint64_t c0_un_wi:1;
1883 uint64_t c0_un_b2:1;
1884 uint64_t c0_un_b1:1;
1885 uint64_t c0_un_b0:1;
1886 uint64_t c0_up_bx:1;
1887 uint64_t c0_up_wi:1;
1888 uint64_t c0_up_b2:1;
1889 uint64_t c0_up_b1:1;
1890 uint64_t c0_up_b0:1;
1891 uint64_t c1_hpint:1;
1894 uint64_t reserved_29_29:1;
1896 uint64_t reserved_27_27:1;
1898 uint64_t c0_hpint:1;
1901 uint64_t reserved_22_22:1;
1903 uint64_t reserved_20_20:1;
1945 uint64_t reserved_20_20:1;
1947 uint64_t reserved_22_22:1;
1950 uint64_t c0_hpint:1;
1952 uint64_t reserved_27_27:1;
1954 uint64_t reserved_29_29:1;
1957 uint64_t c1_hpint:1;
1958 uint64_t c0_up_b0:1;
1959 uint64_t c0_up_b1:1;
1960 uint64_t c0_up_b2:1;
1961 uint64_t c0_up_wi:1;
1962 uint64_t c0_up_bx:1;
1963 uint64_t c0_un_b0:1;
1964 uint64_t c0_un_b1:1;
1965 uint64_t c0_un_b2:1;
1966 uint64_t c0_un_wi:1;
1967 uint64_t c0_un_bx:1;
1968 uint64_t c1_up_b0:1;
1969 uint64_t c1_up_b1:1;
1970 uint64_t c1_up_b2:1;
1971 uint64_t c1_up_wi:1;
1972 uint64_t c1_up_bx:1;
1973 uint64_t c1_un_b0:1;
1974 uint64_t c1_un_b1:1;
1975 uint64_t c1_un_b2:1;
1976 uint64_t c1_un_wi:1;
1977 uint64_t c1_un_bx:1;
1978 uint64_t c0_un_wf:1;
1979 uint64_t c1_un_wf:1;
1980 uint64_t c0_up_wf:1;
1981 uint64_t c1_up_wf:1;
1986 uint64_t reserved_61_62:2;
1987 uint64_t mio_inta:1;
1992 union cvmx_npei_int_enb2 {
1994 struct cvmx_npei_int_enb2_s {
1995 #ifdef __BIG_ENDIAN_BITFIELD
1996 uint64_t reserved_62_63:2;
2002 uint64_t c1_up_wf:1;
2003 uint64_t c0_up_wf:1;
2004 uint64_t c1_un_wf:1;
2005 uint64_t c0_un_wf:1;
2006 uint64_t c1_un_bx:1;
2007 uint64_t c1_un_wi:1;
2008 uint64_t c1_un_b2:1;
2009 uint64_t c1_un_b1:1;
2010 uint64_t c1_un_b0:1;
2011 uint64_t c1_up_bx:1;
2012 uint64_t c1_up_wi:1;
2013 uint64_t c1_up_b2:1;
2014 uint64_t c1_up_b1:1;
2015 uint64_t c1_up_b0:1;
2016 uint64_t c0_un_bx:1;
2017 uint64_t c0_un_wi:1;
2018 uint64_t c0_un_b2:1;
2019 uint64_t c0_un_b1:1;
2020 uint64_t c0_un_b0:1;
2021 uint64_t c0_up_bx:1;
2022 uint64_t c0_up_wi:1;
2023 uint64_t c0_up_b2:1;
2024 uint64_t c0_up_b1:1;
2025 uint64_t c0_up_b0:1;
2026 uint64_t c1_hpint:1;
2033 uint64_t c0_hpint:1;
2085 uint64_t c0_hpint:1;
2092 uint64_t c1_hpint:1;
2093 uint64_t c0_up_b0:1;
2094 uint64_t c0_up_b1:1;
2095 uint64_t c0_up_b2:1;
2096 uint64_t c0_up_wi:1;
2097 uint64_t c0_up_bx:1;
2098 uint64_t c0_un_b0:1;
2099 uint64_t c0_un_b1:1;
2100 uint64_t c0_un_b2:1;
2101 uint64_t c0_un_wi:1;
2102 uint64_t c0_un_bx:1;
2103 uint64_t c1_up_b0:1;
2104 uint64_t c1_up_b1:1;
2105 uint64_t c1_up_b2:1;
2106 uint64_t c1_up_wi:1;
2107 uint64_t c1_up_bx:1;
2108 uint64_t c1_un_b0:1;
2109 uint64_t c1_un_b1:1;
2110 uint64_t c1_un_b2:1;
2111 uint64_t c1_un_wi:1;
2112 uint64_t c1_un_bx:1;
2113 uint64_t c0_un_wf:1;
2114 uint64_t c1_un_wf:1;
2115 uint64_t c0_up_wf:1;
2116 uint64_t c1_up_wf:1;
2122 uint64_t reserved_62_63:2;
2125 struct cvmx_npei_int_enb2_s cn52xx;
2126 struct cvmx_npei_int_enb2_cn52xxp1 {
2127 #ifdef __BIG_ENDIAN_BITFIELD
2128 uint64_t reserved_62_63:2;
2134 uint64_t c1_up_wf:1;
2135 uint64_t c0_up_wf:1;
2136 uint64_t c1_un_wf:1;
2137 uint64_t c0_un_wf:1;
2138 uint64_t c1_un_bx:1;
2139 uint64_t c1_un_wi:1;
2140 uint64_t c1_un_b2:1;
2141 uint64_t c1_un_b1:1;
2142 uint64_t c1_un_b0:1;
2143 uint64_t c1_up_bx:1;
2144 uint64_t c1_up_wi:1;
2145 uint64_t c1_up_b2:1;
2146 uint64_t c1_up_b1:1;
2147 uint64_t c1_up_b0:1;
2148 uint64_t c0_un_bx:1;
2149 uint64_t c0_un_wi:1;
2150 uint64_t c0_un_b2:1;
2151 uint64_t c0_un_b1:1;
2152 uint64_t c0_un_b0:1;
2153 uint64_t c0_up_bx:1;
2154 uint64_t c0_up_wi:1;
2155 uint64_t c0_up_b2:1;
2156 uint64_t c0_up_b1:1;
2157 uint64_t c0_up_b0:1;
2158 uint64_t c1_hpint:1;
2165 uint64_t c0_hpint:1;
2182 uint64_t reserved_8_8:1;
2200 uint64_t reserved_8_8:1;
2217 uint64_t c0_hpint:1;
2224 uint64_t c1_hpint:1;
2225 uint64_t c0_up_b0:1;
2226 uint64_t c0_up_b1:1;
2227 uint64_t c0_up_b2:1;
2228 uint64_t c0_up_wi:1;
2229 uint64_t c0_up_bx:1;
2230 uint64_t c0_un_b0:1;
2231 uint64_t c0_un_b1:1;
2232 uint64_t c0_un_b2:1;
2233 uint64_t c0_un_wi:1;
2234 uint64_t c0_un_bx:1;
2235 uint64_t c1_up_b0:1;
2236 uint64_t c1_up_b1:1;
2237 uint64_t c1_up_b2:1;
2238 uint64_t c1_up_wi:1;
2239 uint64_t c1_up_bx:1;
2240 uint64_t c1_un_b0:1;
2241 uint64_t c1_un_b1:1;
2242 uint64_t c1_un_b2:1;
2243 uint64_t c1_un_wi:1;
2244 uint64_t c1_un_bx:1;
2245 uint64_t c0_un_wf:1;
2246 uint64_t c1_un_wf:1;
2247 uint64_t c0_up_wf:1;
2248 uint64_t c1_up_wf:1;
2254 uint64_t reserved_62_63:2;
2257 struct cvmx_npei_int_enb2_s cn56xx;
2258 struct cvmx_npei_int_enb2_cn56xxp1 {
2259 #ifdef __BIG_ENDIAN_BITFIELD
2260 uint64_t reserved_61_63:3;
2265 uint64_t c1_up_wf:1;
2266 uint64_t c0_up_wf:1;
2267 uint64_t c1_un_wf:1;
2268 uint64_t c0_un_wf:1;
2269 uint64_t c1_un_bx:1;
2270 uint64_t c1_un_wi:1;
2271 uint64_t c1_un_b2:1;
2272 uint64_t c1_un_b1:1;
2273 uint64_t c1_un_b0:1;
2274 uint64_t c1_up_bx:1;
2275 uint64_t c1_up_wi:1;
2276 uint64_t c1_up_b2:1;
2277 uint64_t c1_up_b1:1;
2278 uint64_t c1_up_b0:1;
2279 uint64_t c0_un_bx:1;
2280 uint64_t c0_un_wi:1;
2281 uint64_t c0_un_b2:1;
2282 uint64_t c0_un_b1:1;
2283 uint64_t c0_un_b0:1;
2284 uint64_t c0_up_bx:1;
2285 uint64_t c0_up_wi:1;
2286 uint64_t c0_up_b2:1;
2287 uint64_t c0_up_b1:1;
2288 uint64_t c0_up_b0:1;
2289 uint64_t c1_hpint:1;
2292 uint64_t reserved_29_29:1;
2294 uint64_t reserved_27_27:1;
2296 uint64_t c0_hpint:1;
2299 uint64_t reserved_22_22:1;
2301 uint64_t reserved_20_20:1;
2343 uint64_t reserved_20_20:1;
2345 uint64_t reserved_22_22:1;
2348 uint64_t c0_hpint:1;
2350 uint64_t reserved_27_27:1;
2352 uint64_t reserved_29_29:1;
2355 uint64_t c1_hpint:1;
2356 uint64_t c0_up_b0:1;
2357 uint64_t c0_up_b1:1;
2358 uint64_t c0_up_b2:1;
2359 uint64_t c0_up_wi:1;
2360 uint64_t c0_up_bx:1;
2361 uint64_t c0_un_b0:1;
2362 uint64_t c0_un_b1:1;
2363 uint64_t c0_un_b2:1;
2364 uint64_t c0_un_wi:1;
2365 uint64_t c0_un_bx:1;
2366 uint64_t c1_up_b0:1;
2367 uint64_t c1_up_b1:1;
2368 uint64_t c1_up_b2:1;
2369 uint64_t c1_up_wi:1;
2370 uint64_t c1_up_bx:1;
2371 uint64_t c1_un_b0:1;
2372 uint64_t c1_un_b1:1;
2373 uint64_t c1_un_b2:1;
2374 uint64_t c1_un_wi:1;
2375 uint64_t c1_un_bx:1;
2376 uint64_t c0_un_wf:1;
2377 uint64_t c1_un_wf:1;
2378 uint64_t c0_up_wf:1;
2379 uint64_t c1_up_wf:1;
2384 uint64_t reserved_61_63:3;
2389 union cvmx_npei_int_info {
2391 struct cvmx_npei_int_info_s {
2392 #ifdef __BIG_ENDIAN_BITFIELD
2393 uint64_t reserved_12_63:52;
2399 uint64_t reserved_12_63:52;
2402 struct cvmx_npei_int_info_s cn52xx;
2403 struct cvmx_npei_int_info_s cn56xx;
2404 struct cvmx_npei_int_info_s cn56xxp1;
2407 union cvmx_npei_int_sum {
2409 struct cvmx_npei_int_sum_s {
2410 #ifdef __BIG_ENDIAN_BITFIELD
2411 uint64_t mio_inta:1;
2412 uint64_t reserved_62_62:1;
2418 uint64_t c1_up_wf:1;
2419 uint64_t c0_up_wf:1;
2420 uint64_t c1_un_wf:1;
2421 uint64_t c0_un_wf:1;
2422 uint64_t c1_un_bx:1;
2423 uint64_t c1_un_wi:1;
2424 uint64_t c1_un_b2:1;
2425 uint64_t c1_un_b1:1;
2426 uint64_t c1_un_b0:1;
2427 uint64_t c1_up_bx:1;
2428 uint64_t c1_up_wi:1;
2429 uint64_t c1_up_b2:1;
2430 uint64_t c1_up_b1:1;
2431 uint64_t c1_up_b0:1;
2432 uint64_t c0_un_bx:1;
2433 uint64_t c0_un_wi:1;
2434 uint64_t c0_un_b2:1;
2435 uint64_t c0_un_b1:1;
2436 uint64_t c0_un_b0:1;
2437 uint64_t c0_up_bx:1;
2438 uint64_t c0_up_wi:1;
2439 uint64_t c0_up_b2:1;
2440 uint64_t c0_up_b1:1;
2441 uint64_t c0_up_b0:1;
2442 uint64_t c1_hpint:1;
2449 uint64_t c0_hpint:1;
2501 uint64_t c0_hpint:1;
2508 uint64_t c1_hpint:1;
2509 uint64_t c0_up_b0:1;
2510 uint64_t c0_up_b1:1;
2511 uint64_t c0_up_b2:1;
2512 uint64_t c0_up_wi:1;
2513 uint64_t c0_up_bx:1;
2514 uint64_t c0_un_b0:1;
2515 uint64_t c0_un_b1:1;
2516 uint64_t c0_un_b2:1;
2517 uint64_t c0_un_wi:1;
2518 uint64_t c0_un_bx:1;
2519 uint64_t c1_up_b0:1;
2520 uint64_t c1_up_b1:1;
2521 uint64_t c1_up_b2:1;
2522 uint64_t c1_up_wi:1;
2523 uint64_t c1_up_bx:1;
2524 uint64_t c1_un_b0:1;
2525 uint64_t c1_un_b1:1;
2526 uint64_t c1_un_b2:1;
2527 uint64_t c1_un_wi:1;
2528 uint64_t c1_un_bx:1;
2529 uint64_t c0_un_wf:1;
2530 uint64_t c1_un_wf:1;
2531 uint64_t c0_up_wf:1;
2532 uint64_t c1_up_wf:1;
2538 uint64_t reserved_62_62:1;
2539 uint64_t mio_inta:1;
2542 struct cvmx_npei_int_sum_s cn52xx;
2543 struct cvmx_npei_int_sum_cn52xxp1 {
2544 #ifdef __BIG_ENDIAN_BITFIELD
2545 uint64_t mio_inta:1;
2546 uint64_t reserved_62_62:1;
2552 uint64_t c1_up_wf:1;
2553 uint64_t c0_up_wf:1;
2554 uint64_t c1_un_wf:1;
2555 uint64_t c0_un_wf:1;
2556 uint64_t c1_un_bx:1;
2557 uint64_t c1_un_wi:1;
2558 uint64_t c1_un_b2:1;
2559 uint64_t c1_un_b1:1;
2560 uint64_t c1_un_b0:1;
2561 uint64_t c1_up_bx:1;
2562 uint64_t c1_up_wi:1;
2563 uint64_t c1_up_b2:1;
2564 uint64_t c1_up_b1:1;
2565 uint64_t c1_up_b0:1;
2566 uint64_t c0_un_bx:1;
2567 uint64_t c0_un_wi:1;
2568 uint64_t c0_un_b2:1;
2569 uint64_t c0_un_b1:1;
2570 uint64_t c0_un_b0:1;
2571 uint64_t c0_up_bx:1;
2572 uint64_t c0_up_wi:1;
2573 uint64_t c0_up_b2:1;
2574 uint64_t c0_up_b1:1;
2575 uint64_t c0_up_b0:1;
2576 uint64_t c1_hpint:1;
2583 uint64_t c0_hpint:1;
2590 uint64_t reserved_15_18:4;
2597 uint64_t reserved_8_8:1;
2615 uint64_t reserved_8_8:1;
2622 uint64_t reserved_15_18:4;
2629 uint64_t c0_hpint:1;
2636 uint64_t c1_hpint:1;
2637 uint64_t c0_up_b0:1;
2638 uint64_t c0_up_b1:1;
2639 uint64_t c0_up_b2:1;
2640 uint64_t c0_up_wi:1;
2641 uint64_t c0_up_bx:1;
2642 uint64_t c0_un_b0:1;
2643 uint64_t c0_un_b1:1;
2644 uint64_t c0_un_b2:1;
2645 uint64_t c0_un_wi:1;
2646 uint64_t c0_un_bx:1;
2647 uint64_t c1_up_b0:1;
2648 uint64_t c1_up_b1:1;
2649 uint64_t c1_up_b2:1;
2650 uint64_t c1_up_wi:1;
2651 uint64_t c1_up_bx:1;
2652 uint64_t c1_un_b0:1;
2653 uint64_t c1_un_b1:1;
2654 uint64_t c1_un_b2:1;
2655 uint64_t c1_un_wi:1;
2656 uint64_t c1_un_bx:1;
2657 uint64_t c0_un_wf:1;
2658 uint64_t c1_un_wf:1;
2659 uint64_t c0_up_wf:1;
2660 uint64_t c1_up_wf:1;
2666 uint64_t reserved_62_62:1;
2667 uint64_t mio_inta:1;
2670 struct cvmx_npei_int_sum_s cn56xx;
2671 struct cvmx_npei_int_sum_cn56xxp1 {
2672 #ifdef __BIG_ENDIAN_BITFIELD
2673 uint64_t mio_inta:1;
2674 uint64_t reserved_61_62:2;
2679 uint64_t c1_up_wf:1;
2680 uint64_t c0_up_wf:1;
2681 uint64_t c1_un_wf:1;
2682 uint64_t c0_un_wf:1;
2683 uint64_t c1_un_bx:1;
2684 uint64_t c1_un_wi:1;
2685 uint64_t c1_un_b2:1;
2686 uint64_t c1_un_b1:1;
2687 uint64_t c1_un_b0:1;
2688 uint64_t c1_up_bx:1;
2689 uint64_t c1_up_wi:1;
2690 uint64_t c1_up_b2:1;
2691 uint64_t c1_up_b1:1;
2692 uint64_t c1_up_b0:1;
2693 uint64_t c0_un_bx:1;
2694 uint64_t c0_un_wi:1;
2695 uint64_t c0_un_b2:1;
2696 uint64_t c0_un_b1:1;
2697 uint64_t c0_un_b0:1;
2698 uint64_t c0_up_bx:1;
2699 uint64_t c0_up_wi:1;
2700 uint64_t c0_up_b2:1;
2701 uint64_t c0_up_b1:1;
2702 uint64_t c0_up_b0:1;
2703 uint64_t c1_hpint:1;
2706 uint64_t reserved_29_29:1;
2708 uint64_t reserved_27_27:1;
2710 uint64_t c0_hpint:1;
2713 uint64_t reserved_22_22:1;
2715 uint64_t reserved_20_20:1;
2717 uint64_t reserved_15_18:4;
2749 uint64_t reserved_15_18:4;
2751 uint64_t reserved_20_20:1;
2753 uint64_t reserved_22_22:1;
2756 uint64_t c0_hpint:1;
2758 uint64_t reserved_27_27:1;
2760 uint64_t reserved_29_29:1;
2763 uint64_t c1_hpint:1;
2764 uint64_t c0_up_b0:1;
2765 uint64_t c0_up_b1:1;
2766 uint64_t c0_up_b2:1;
2767 uint64_t c0_up_wi:1;
2768 uint64_t c0_up_bx:1;
2769 uint64_t c0_un_b0:1;
2770 uint64_t c0_un_b1:1;
2771 uint64_t c0_un_b2:1;
2772 uint64_t c0_un_wi:1;
2773 uint64_t c0_un_bx:1;
2774 uint64_t c1_up_b0:1;
2775 uint64_t c1_up_b1:1;
2776 uint64_t c1_up_b2:1;
2777 uint64_t c1_up_wi:1;
2778 uint64_t c1_up_bx:1;
2779 uint64_t c1_un_b0:1;
2780 uint64_t c1_un_b1:1;
2781 uint64_t c1_un_b2:1;
2782 uint64_t c1_un_wi:1;
2783 uint64_t c1_un_bx:1;
2784 uint64_t c0_un_wf:1;
2785 uint64_t c1_un_wf:1;
2786 uint64_t c0_up_wf:1;
2787 uint64_t c1_up_wf:1;
2792 uint64_t reserved_61_62:2;
2793 uint64_t mio_inta:1;
2798 union cvmx_npei_int_sum2 {
2800 struct cvmx_npei_int_sum2_s {
2801 #ifdef __BIG_ENDIAN_BITFIELD
2802 uint64_t mio_inta:1;
2803 uint64_t reserved_62_62:1;
2809 uint64_t c1_up_wf:1;
2810 uint64_t c0_up_wf:1;
2811 uint64_t c1_un_wf:1;
2812 uint64_t c0_un_wf:1;
2813 uint64_t c1_un_bx:1;
2814 uint64_t c1_un_wi:1;
2815 uint64_t c1_un_b2:1;
2816 uint64_t c1_un_b1:1;
2817 uint64_t c1_un_b0:1;
2818 uint64_t c1_up_bx:1;
2819 uint64_t c1_up_wi:1;
2820 uint64_t c1_up_b2:1;
2821 uint64_t c1_up_b1:1;
2822 uint64_t c1_up_b0:1;
2823 uint64_t c0_un_bx:1;
2824 uint64_t c0_un_wi:1;
2825 uint64_t c0_un_b2:1;
2826 uint64_t c0_un_b1:1;
2827 uint64_t c0_un_b0:1;
2828 uint64_t c0_up_bx:1;
2829 uint64_t c0_up_wi:1;
2830 uint64_t c0_up_b2:1;
2831 uint64_t c0_up_b1:1;
2832 uint64_t c0_up_b0:1;
2833 uint64_t c1_hpint:1;
2840 uint64_t c0_hpint:1;
2847 uint64_t reserved_15_18:4;
2854 uint64_t reserved_8_8:1;
2872 uint64_t reserved_8_8:1;
2879 uint64_t reserved_15_18:4;
2886 uint64_t c0_hpint:1;
2893 uint64_t c1_hpint:1;
2894 uint64_t c0_up_b0:1;
2895 uint64_t c0_up_b1:1;
2896 uint64_t c0_up_b2:1;
2897 uint64_t c0_up_wi:1;
2898 uint64_t c0_up_bx:1;
2899 uint64_t c0_un_b0:1;
2900 uint64_t c0_un_b1:1;
2901 uint64_t c0_un_b2:1;
2902 uint64_t c0_un_wi:1;
2903 uint64_t c0_un_bx:1;
2904 uint64_t c1_up_b0:1;
2905 uint64_t c1_up_b1:1;
2906 uint64_t c1_up_b2:1;
2907 uint64_t c1_up_wi:1;
2908 uint64_t c1_up_bx:1;
2909 uint64_t c1_un_b0:1;
2910 uint64_t c1_un_b1:1;
2911 uint64_t c1_un_b2:1;
2912 uint64_t c1_un_wi:1;
2913 uint64_t c1_un_bx:1;
2914 uint64_t c0_un_wf:1;
2915 uint64_t c1_un_wf:1;
2916 uint64_t c0_up_wf:1;
2917 uint64_t c1_up_wf:1;
2923 uint64_t reserved_62_62:1;
2924 uint64_t mio_inta:1;
2927 struct cvmx_npei_int_sum2_s cn52xx;
2928 struct cvmx_npei_int_sum2_s cn52xxp1;
2929 struct cvmx_npei_int_sum2_s cn56xx;
2932 union cvmx_npei_last_win_rdata0 {
2934 struct cvmx_npei_last_win_rdata0_s {
2935 #ifdef __BIG_ENDIAN_BITFIELD
2941 struct cvmx_npei_last_win_rdata0_s cn52xx;
2942 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
2943 struct cvmx_npei_last_win_rdata0_s cn56xx;
2944 struct cvmx_npei_last_win_rdata0_s cn56xxp1;
2947 union cvmx_npei_last_win_rdata1 {
2949 struct cvmx_npei_last_win_rdata1_s {
2950 #ifdef __BIG_ENDIAN_BITFIELD
2956 struct cvmx_npei_last_win_rdata1_s cn52xx;
2957 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
2958 struct cvmx_npei_last_win_rdata1_s cn56xx;
2959 struct cvmx_npei_last_win_rdata1_s cn56xxp1;
2962 union cvmx_npei_mem_access_ctl {
2964 struct cvmx_npei_mem_access_ctl_s {
2965 #ifdef __BIG_ENDIAN_BITFIELD
2966 uint64_t reserved_14_63:50;
2967 uint64_t max_word:4;
2971 uint64_t max_word:4;
2972 uint64_t reserved_14_63:50;
2975 struct cvmx_npei_mem_access_ctl_s cn52xx;
2976 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
2977 struct cvmx_npei_mem_access_ctl_s cn56xx;
2978 struct cvmx_npei_mem_access_ctl_s cn56xxp1;
2981 union cvmx_npei_mem_access_subidx {
2983 struct cvmx_npei_mem_access_subidx_s {
2984 #ifdef __BIG_ENDIAN_BITFIELD
2985 uint64_t reserved_42_63:22;
3007 uint64_t reserved_42_63:22;
3010 struct cvmx_npei_mem_access_subidx_s cn52xx;
3011 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
3012 struct cvmx_npei_mem_access_subidx_s cn56xx;
3013 struct cvmx_npei_mem_access_subidx_s cn56xxp1;
3016 union cvmx_npei_msi_enb0 {
3018 struct cvmx_npei_msi_enb0_s {
3019 #ifdef __BIG_ENDIAN_BITFIELD
3025 struct cvmx_npei_msi_enb0_s cn52xx;
3026 struct cvmx_npei_msi_enb0_s cn52xxp1;
3027 struct cvmx_npei_msi_enb0_s cn56xx;
3028 struct cvmx_npei_msi_enb0_s cn56xxp1;
3031 union cvmx_npei_msi_enb1 {
3033 struct cvmx_npei_msi_enb1_s {
3034 #ifdef __BIG_ENDIAN_BITFIELD
3040 struct cvmx_npei_msi_enb1_s cn52xx;
3041 struct cvmx_npei_msi_enb1_s cn52xxp1;
3042 struct cvmx_npei_msi_enb1_s cn56xx;
3043 struct cvmx_npei_msi_enb1_s cn56xxp1;
3046 union cvmx_npei_msi_enb2 {
3048 struct cvmx_npei_msi_enb2_s {
3049 #ifdef __BIG_ENDIAN_BITFIELD
3055 struct cvmx_npei_msi_enb2_s cn52xx;
3056 struct cvmx_npei_msi_enb2_s cn52xxp1;
3057 struct cvmx_npei_msi_enb2_s cn56xx;
3058 struct cvmx_npei_msi_enb2_s cn56xxp1;
3061 union cvmx_npei_msi_enb3 {
3063 struct cvmx_npei_msi_enb3_s {
3064 #ifdef __BIG_ENDIAN_BITFIELD
3070 struct cvmx_npei_msi_enb3_s cn52xx;
3071 struct cvmx_npei_msi_enb3_s cn52xxp1;
3072 struct cvmx_npei_msi_enb3_s cn56xx;
3073 struct cvmx_npei_msi_enb3_s cn56xxp1;
3076 union cvmx_npei_msi_rcv0 {
3078 struct cvmx_npei_msi_rcv0_s {
3079 #ifdef __BIG_ENDIAN_BITFIELD
3085 struct cvmx_npei_msi_rcv0_s cn52xx;
3086 struct cvmx_npei_msi_rcv0_s cn52xxp1;
3087 struct cvmx_npei_msi_rcv0_s cn56xx;
3088 struct cvmx_npei_msi_rcv0_s cn56xxp1;
3091 union cvmx_npei_msi_rcv1 {
3093 struct cvmx_npei_msi_rcv1_s {
3094 #ifdef __BIG_ENDIAN_BITFIELD
3100 struct cvmx_npei_msi_rcv1_s cn52xx;
3101 struct cvmx_npei_msi_rcv1_s cn52xxp1;
3102 struct cvmx_npei_msi_rcv1_s cn56xx;
3103 struct cvmx_npei_msi_rcv1_s cn56xxp1;
3106 union cvmx_npei_msi_rcv2 {
3108 struct cvmx_npei_msi_rcv2_s {
3109 #ifdef __BIG_ENDIAN_BITFIELD
3115 struct cvmx_npei_msi_rcv2_s cn52xx;
3116 struct cvmx_npei_msi_rcv2_s cn52xxp1;
3117 struct cvmx_npei_msi_rcv2_s cn56xx;
3118 struct cvmx_npei_msi_rcv2_s cn56xxp1;
3121 union cvmx_npei_msi_rcv3 {
3123 struct cvmx_npei_msi_rcv3_s {
3124 #ifdef __BIG_ENDIAN_BITFIELD
3130 struct cvmx_npei_msi_rcv3_s cn52xx;
3131 struct cvmx_npei_msi_rcv3_s cn52xxp1;
3132 struct cvmx_npei_msi_rcv3_s cn56xx;
3133 struct cvmx_npei_msi_rcv3_s cn56xxp1;
3136 union cvmx_npei_msi_rd_map {
3138 struct cvmx_npei_msi_rd_map_s {
3139 #ifdef __BIG_ENDIAN_BITFIELD
3140 uint64_t reserved_16_63:48;
3146 uint64_t reserved_16_63:48;
3149 struct cvmx_npei_msi_rd_map_s cn52xx;
3150 struct cvmx_npei_msi_rd_map_s cn52xxp1;
3151 struct cvmx_npei_msi_rd_map_s cn56xx;
3152 struct cvmx_npei_msi_rd_map_s cn56xxp1;
3155 union cvmx_npei_msi_w1c_enb0 {
3157 struct cvmx_npei_msi_w1c_enb0_s {
3158 #ifdef __BIG_ENDIAN_BITFIELD
3164 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
3165 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
3168 union cvmx_npei_msi_w1c_enb1 {
3170 struct cvmx_npei_msi_w1c_enb1_s {
3171 #ifdef __BIG_ENDIAN_BITFIELD
3177 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
3178 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
3181 union cvmx_npei_msi_w1c_enb2 {
3183 struct cvmx_npei_msi_w1c_enb2_s {
3184 #ifdef __BIG_ENDIAN_BITFIELD
3190 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
3191 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
3194 union cvmx_npei_msi_w1c_enb3 {
3196 struct cvmx_npei_msi_w1c_enb3_s {
3197 #ifdef __BIG_ENDIAN_BITFIELD
3203 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
3204 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
3207 union cvmx_npei_msi_w1s_enb0 {
3209 struct cvmx_npei_msi_w1s_enb0_s {
3210 #ifdef __BIG_ENDIAN_BITFIELD
3216 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
3217 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
3220 union cvmx_npei_msi_w1s_enb1 {
3222 struct cvmx_npei_msi_w1s_enb1_s {
3223 #ifdef __BIG_ENDIAN_BITFIELD
3229 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
3230 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
3233 union cvmx_npei_msi_w1s_enb2 {
3235 struct cvmx_npei_msi_w1s_enb2_s {
3236 #ifdef __BIG_ENDIAN_BITFIELD
3242 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
3243 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
3246 union cvmx_npei_msi_w1s_enb3 {
3248 struct cvmx_npei_msi_w1s_enb3_s {
3249 #ifdef __BIG_ENDIAN_BITFIELD
3255 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
3256 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
3259 union cvmx_npei_msi_wr_map {
3261 struct cvmx_npei_msi_wr_map_s {
3262 #ifdef __BIG_ENDIAN_BITFIELD
3263 uint64_t reserved_16_63:48;
3269 uint64_t reserved_16_63:48;
3272 struct cvmx_npei_msi_wr_map_s cn52xx;
3273 struct cvmx_npei_msi_wr_map_s cn52xxp1;
3274 struct cvmx_npei_msi_wr_map_s cn56xx;
3275 struct cvmx_npei_msi_wr_map_s cn56xxp1;
3278 union cvmx_npei_pcie_credit_cnt {
3280 struct cvmx_npei_pcie_credit_cnt_s {
3281 #ifdef __BIG_ENDIAN_BITFIELD
3282 uint64_t reserved_48_63:16;
3296 uint64_t reserved_48_63:16;
3299 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
3300 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
3303 union cvmx_npei_pcie_msi_rcv {
3305 struct cvmx_npei_pcie_msi_rcv_s {
3306 #ifdef __BIG_ENDIAN_BITFIELD
3307 uint64_t reserved_8_63:56;
3311 uint64_t reserved_8_63:56;
3314 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
3315 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
3316 struct cvmx_npei_pcie_msi_rcv_s cn56xx;
3317 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
3320 union cvmx_npei_pcie_msi_rcv_b1 {
3322 struct cvmx_npei_pcie_msi_rcv_b1_s {
3323 #ifdef __BIG_ENDIAN_BITFIELD
3324 uint64_t reserved_16_63:48;
3326 uint64_t reserved_0_7:8;
3328 uint64_t reserved_0_7:8;
3330 uint64_t reserved_16_63:48;
3333 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
3334 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
3335 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
3336 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
3339 union cvmx_npei_pcie_msi_rcv_b2 {
3341 struct cvmx_npei_pcie_msi_rcv_b2_s {
3342 #ifdef __BIG_ENDIAN_BITFIELD
3343 uint64_t reserved_24_63:40;
3345 uint64_t reserved_0_15:16;
3347 uint64_t reserved_0_15:16;
3349 uint64_t reserved_24_63:40;
3352 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
3353 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
3354 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
3355 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
3358 union cvmx_npei_pcie_msi_rcv_b3 {
3360 struct cvmx_npei_pcie_msi_rcv_b3_s {
3361 #ifdef __BIG_ENDIAN_BITFIELD
3362 uint64_t reserved_32_63:32;
3364 uint64_t reserved_0_23:24;
3366 uint64_t reserved_0_23:24;
3368 uint64_t reserved_32_63:32;
3371 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
3372 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
3373 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
3374 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
3377 union cvmx_npei_pktx_cnts {
3379 struct cvmx_npei_pktx_cnts_s {
3380 #ifdef __BIG_ENDIAN_BITFIELD
3381 uint64_t reserved_54_63:10;
3387 uint64_t reserved_54_63:10;
3390 struct cvmx_npei_pktx_cnts_s cn52xx;
3391 struct cvmx_npei_pktx_cnts_s cn56xx;
3394 union cvmx_npei_pktx_in_bp {
3396 struct cvmx_npei_pktx_in_bp_s {
3397 #ifdef __BIG_ENDIAN_BITFIELD
3405 struct cvmx_npei_pktx_in_bp_s cn52xx;
3406 struct cvmx_npei_pktx_in_bp_s cn56xx;
3409 union cvmx_npei_pktx_instr_baddr {
3411 struct cvmx_npei_pktx_instr_baddr_s {
3412 #ifdef __BIG_ENDIAN_BITFIELD
3414 uint64_t reserved_0_2:3;
3416 uint64_t reserved_0_2:3;
3420 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
3421 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
3424 union cvmx_npei_pktx_instr_baoff_dbell {
3426 struct cvmx_npei_pktx_instr_baoff_dbell_s {
3427 #ifdef __BIG_ENDIAN_BITFIELD
3435 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
3436 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
3439 union cvmx_npei_pktx_instr_fifo_rsize {
3441 struct cvmx_npei_pktx_instr_fifo_rsize_s {
3442 #ifdef __BIG_ENDIAN_BITFIELD
3456 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
3457 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
3460 union cvmx_npei_pktx_instr_header {
3462 struct cvmx_npei_pktx_instr_header_s {
3463 #ifdef __BIG_ENDIAN_BITFIELD
3464 uint64_t reserved_44_63:20;
3466 uint64_t reserved_38_42:5;
3467 uint64_t rparmode:2;
3468 uint64_t reserved_35_35:1;
3469 uint64_t rskp_len:7;
3470 uint64_t reserved_22_27:6;
3471 uint64_t use_ihdr:1;
3472 uint64_t reserved_16_20:5;
3473 uint64_t par_mode:2;
3474 uint64_t reserved_13_13:1;
3476 uint64_t reserved_0_5:6;
3478 uint64_t reserved_0_5:6;
3480 uint64_t reserved_13_13:1;
3481 uint64_t par_mode:2;
3482 uint64_t reserved_16_20:5;
3483 uint64_t use_ihdr:1;
3484 uint64_t reserved_22_27:6;
3485 uint64_t rskp_len:7;
3486 uint64_t reserved_35_35:1;
3487 uint64_t rparmode:2;
3488 uint64_t reserved_38_42:5;
3490 uint64_t reserved_44_63:20;
3493 struct cvmx_npei_pktx_instr_header_s cn52xx;
3494 struct cvmx_npei_pktx_instr_header_s cn56xx;
3497 union cvmx_npei_pktx_slist_baddr {
3499 struct cvmx_npei_pktx_slist_baddr_s {
3500 #ifdef __BIG_ENDIAN_BITFIELD
3502 uint64_t reserved_0_3:4;
3504 uint64_t reserved_0_3:4;
3508 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
3509 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
3512 union cvmx_npei_pktx_slist_baoff_dbell {
3514 struct cvmx_npei_pktx_slist_baoff_dbell_s {
3515 #ifdef __BIG_ENDIAN_BITFIELD
3523 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
3524 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
3527 union cvmx_npei_pktx_slist_fifo_rsize {
3529 struct cvmx_npei_pktx_slist_fifo_rsize_s {
3530 #ifdef __BIG_ENDIAN_BITFIELD
3531 uint64_t reserved_32_63:32;
3535 uint64_t reserved_32_63:32;
3538 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
3539 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
3542 union cvmx_npei_pkt_cnt_int {
3544 struct cvmx_npei_pkt_cnt_int_s {
3545 #ifdef __BIG_ENDIAN_BITFIELD
3546 uint64_t reserved_32_63:32;
3550 uint64_t reserved_32_63:32;
3553 struct cvmx_npei_pkt_cnt_int_s cn52xx;
3554 struct cvmx_npei_pkt_cnt_int_s cn56xx;
3557 union cvmx_npei_pkt_cnt_int_enb {
3559 struct cvmx_npei_pkt_cnt_int_enb_s {
3560 #ifdef __BIG_ENDIAN_BITFIELD
3561 uint64_t reserved_32_63:32;
3565 uint64_t reserved_32_63:32;
3568 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
3569 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
3572 union cvmx_npei_pkt_data_out_es {
3574 struct cvmx_npei_pkt_data_out_es_s {
3575 #ifdef __BIG_ENDIAN_BITFIELD
3581 struct cvmx_npei_pkt_data_out_es_s cn52xx;
3582 struct cvmx_npei_pkt_data_out_es_s cn56xx;
3585 union cvmx_npei_pkt_data_out_ns {
3587 struct cvmx_npei_pkt_data_out_ns_s {
3588 #ifdef __BIG_ENDIAN_BITFIELD
3589 uint64_t reserved_32_63:32;
3593 uint64_t reserved_32_63:32;
3596 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
3597 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
3600 union cvmx_npei_pkt_data_out_ror {
3602 struct cvmx_npei_pkt_data_out_ror_s {
3603 #ifdef __BIG_ENDIAN_BITFIELD
3604 uint64_t reserved_32_63:32;
3608 uint64_t reserved_32_63:32;
3611 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
3612 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
3615 union cvmx_npei_pkt_dpaddr {
3617 struct cvmx_npei_pkt_dpaddr_s {
3618 #ifdef __BIG_ENDIAN_BITFIELD
3619 uint64_t reserved_32_63:32;
3623 uint64_t reserved_32_63:32;
3626 struct cvmx_npei_pkt_dpaddr_s cn52xx;
3627 struct cvmx_npei_pkt_dpaddr_s cn56xx;
3630 union cvmx_npei_pkt_in_bp {
3632 struct cvmx_npei_pkt_in_bp_s {
3633 #ifdef __BIG_ENDIAN_BITFIELD
3634 uint64_t reserved_32_63:32;
3638 uint64_t reserved_32_63:32;
3641 struct cvmx_npei_pkt_in_bp_s cn52xx;
3642 struct cvmx_npei_pkt_in_bp_s cn56xx;
3645 union cvmx_npei_pkt_in_donex_cnts {
3647 struct cvmx_npei_pkt_in_donex_cnts_s {
3648 #ifdef __BIG_ENDIAN_BITFIELD
3649 uint64_t reserved_32_63:32;
3653 uint64_t reserved_32_63:32;
3656 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
3657 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
3660 union cvmx_npei_pkt_in_instr_counts {
3662 struct cvmx_npei_pkt_in_instr_counts_s {
3663 #ifdef __BIG_ENDIAN_BITFIELD
3671 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
3672 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
3675 union cvmx_npei_pkt_in_pcie_port {
3677 struct cvmx_npei_pkt_in_pcie_port_s {
3678 #ifdef __BIG_ENDIAN_BITFIELD
3684 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
3685 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
3688 union cvmx_npei_pkt_input_control {
3690 struct cvmx_npei_pkt_input_control_s {
3691 #ifdef __BIG_ENDIAN_BITFIELD
3692 uint64_t reserved_23_63:41;
3694 uint64_t pbp_dhi:13;
3710 uint64_t pbp_dhi:13;
3712 uint64_t reserved_23_63:41;
3715 struct cvmx_npei_pkt_input_control_s cn52xx;
3716 struct cvmx_npei_pkt_input_control_s cn56xx;
3719 union cvmx_npei_pkt_instr_enb {
3721 struct cvmx_npei_pkt_instr_enb_s {
3722 #ifdef __BIG_ENDIAN_BITFIELD
3723 uint64_t reserved_32_63:32;
3727 uint64_t reserved_32_63:32;
3730 struct cvmx_npei_pkt_instr_enb_s cn52xx;
3731 struct cvmx_npei_pkt_instr_enb_s cn56xx;
3734 union cvmx_npei_pkt_instr_rd_size {
3736 struct cvmx_npei_pkt_instr_rd_size_s {
3737 #ifdef __BIG_ENDIAN_BITFIELD
3743 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
3744 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
3747 union cvmx_npei_pkt_instr_size {
3749 struct cvmx_npei_pkt_instr_size_s {
3750 #ifdef __BIG_ENDIAN_BITFIELD
3751 uint64_t reserved_32_63:32;
3755 uint64_t reserved_32_63:32;
3758 struct cvmx_npei_pkt_instr_size_s cn52xx;
3759 struct cvmx_npei_pkt_instr_size_s cn56xx;
3762 union cvmx_npei_pkt_int_levels {
3764 struct cvmx_npei_pkt_int_levels_s {
3765 #ifdef __BIG_ENDIAN_BITFIELD
3766 uint64_t reserved_54_63:10;
3772 uint64_t reserved_54_63:10;
3775 struct cvmx_npei_pkt_int_levels_s cn52xx;
3776 struct cvmx_npei_pkt_int_levels_s cn56xx;
3779 union cvmx_npei_pkt_iptr {
3781 struct cvmx_npei_pkt_iptr_s {
3782 #ifdef __BIG_ENDIAN_BITFIELD
3783 uint64_t reserved_32_63:32;
3787 uint64_t reserved_32_63:32;
3790 struct cvmx_npei_pkt_iptr_s cn52xx;
3791 struct cvmx_npei_pkt_iptr_s cn56xx;
3794 union cvmx_npei_pkt_out_bmode {
3796 struct cvmx_npei_pkt_out_bmode_s {
3797 #ifdef __BIG_ENDIAN_BITFIELD
3798 uint64_t reserved_32_63:32;
3802 uint64_t reserved_32_63:32;
3805 struct cvmx_npei_pkt_out_bmode_s cn52xx;
3806 struct cvmx_npei_pkt_out_bmode_s cn56xx;
3809 union cvmx_npei_pkt_out_enb {
3811 struct cvmx_npei_pkt_out_enb_s {
3812 #ifdef __BIG_ENDIAN_BITFIELD
3813 uint64_t reserved_32_63:32;
3817 uint64_t reserved_32_63:32;
3820 struct cvmx_npei_pkt_out_enb_s cn52xx;
3821 struct cvmx_npei_pkt_out_enb_s cn56xx;
3824 union cvmx_npei_pkt_output_wmark {
3826 struct cvmx_npei_pkt_output_wmark_s {
3827 #ifdef __BIG_ENDIAN_BITFIELD
3828 uint64_t reserved_32_63:32;
3832 uint64_t reserved_32_63:32;
3835 struct cvmx_npei_pkt_output_wmark_s cn52xx;
3836 struct cvmx_npei_pkt_output_wmark_s cn56xx;
3839 union cvmx_npei_pkt_pcie_port {
3841 struct cvmx_npei_pkt_pcie_port_s {
3842 #ifdef __BIG_ENDIAN_BITFIELD
3848 struct cvmx_npei_pkt_pcie_port_s cn52xx;
3849 struct cvmx_npei_pkt_pcie_port_s cn56xx;
3852 union cvmx_npei_pkt_port_in_rst {
3854 struct cvmx_npei_pkt_port_in_rst_s {
3855 #ifdef __BIG_ENDIAN_BITFIELD
3857 uint64_t out_rst:32;
3859 uint64_t out_rst:32;
3863 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
3864 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
3867 union cvmx_npei_pkt_slist_es {
3869 struct cvmx_npei_pkt_slist_es_s {
3870 #ifdef __BIG_ENDIAN_BITFIELD
3876 struct cvmx_npei_pkt_slist_es_s cn52xx;
3877 struct cvmx_npei_pkt_slist_es_s cn56xx;
3880 union cvmx_npei_pkt_slist_id_size {
3882 struct cvmx_npei_pkt_slist_id_size_s {
3883 #ifdef __BIG_ENDIAN_BITFIELD
3884 uint64_t reserved_23_63:41;
3890 uint64_t reserved_23_63:41;
3893 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
3894 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
3897 union cvmx_npei_pkt_slist_ns {
3899 struct cvmx_npei_pkt_slist_ns_s {
3900 #ifdef __BIG_ENDIAN_BITFIELD
3901 uint64_t reserved_32_63:32;
3905 uint64_t reserved_32_63:32;
3908 struct cvmx_npei_pkt_slist_ns_s cn52xx;
3909 struct cvmx_npei_pkt_slist_ns_s cn56xx;
3912 union cvmx_npei_pkt_slist_ror {
3914 struct cvmx_npei_pkt_slist_ror_s {
3915 #ifdef __BIG_ENDIAN_BITFIELD
3916 uint64_t reserved_32_63:32;
3920 uint64_t reserved_32_63:32;
3923 struct cvmx_npei_pkt_slist_ror_s cn52xx;
3924 struct cvmx_npei_pkt_slist_ror_s cn56xx;
3927 union cvmx_npei_pkt_time_int {
3929 struct cvmx_npei_pkt_time_int_s {
3930 #ifdef __BIG_ENDIAN_BITFIELD
3931 uint64_t reserved_32_63:32;
3935 uint64_t reserved_32_63:32;
3938 struct cvmx_npei_pkt_time_int_s cn52xx;
3939 struct cvmx_npei_pkt_time_int_s cn56xx;
3942 union cvmx_npei_pkt_time_int_enb {
3944 struct cvmx_npei_pkt_time_int_enb_s {
3945 #ifdef __BIG_ENDIAN_BITFIELD
3946 uint64_t reserved_32_63:32;
3950 uint64_t reserved_32_63:32;
3953 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
3954 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
3957 union cvmx_npei_rsl_int_blocks {
3959 struct cvmx_npei_rsl_int_blocks_s {
3960 #ifdef __BIG_ENDIAN_BITFIELD
3961 uint64_t reserved_31_63:33;
3965 uint64_t reserved_24_27:4;
3968 uint64_t reserved_21_21:1;
3981 uint64_t reserved_8_8:1;
3999 uint64_t reserved_8_8:1;
4012 uint64_t reserved_21_21:1;
4015 uint64_t reserved_24_27:4;
4019 uint64_t reserved_31_63:33;
4022 struct cvmx_npei_rsl_int_blocks_s cn52xx;
4023 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
4024 struct cvmx_npei_rsl_int_blocks_s cn56xx;
4025 struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
4028 union cvmx_npei_scratch_1 {
4030 struct cvmx_npei_scratch_1_s {
4031 #ifdef __BIG_ENDIAN_BITFIELD
4037 struct cvmx_npei_scratch_1_s cn52xx;
4038 struct cvmx_npei_scratch_1_s cn52xxp1;
4039 struct cvmx_npei_scratch_1_s cn56xx;
4040 struct cvmx_npei_scratch_1_s cn56xxp1;
4043 union cvmx_npei_state1 {
4045 struct cvmx_npei_state1_s {
4046 #ifdef __BIG_ENDIAN_BITFIELD
4058 struct cvmx_npei_state1_s cn52xx;
4059 struct cvmx_npei_state1_s cn52xxp1;
4060 struct cvmx_npei_state1_s cn56xx;
4061 struct cvmx_npei_state1_s cn56xxp1;
4064 union cvmx_npei_state2 {
4066 struct cvmx_npei_state2_s {
4067 #ifdef __BIG_ENDIAN_BITFIELD
4068 uint64_t reserved_48_63:16;
4082 uint64_t reserved_48_63:16;
4085 struct cvmx_npei_state2_s cn52xx;
4086 struct cvmx_npei_state2_s cn52xxp1;
4087 struct cvmx_npei_state2_s cn56xx;
4088 struct cvmx_npei_state2_s cn56xxp1;
4091 union cvmx_npei_state3 {
4093 struct cvmx_npei_state3_s {
4094 #ifdef __BIG_ENDIAN_BITFIELD
4095 uint64_t reserved_56_63:8;
4105 uint64_t reserved_56_63:8;
4108 struct cvmx_npei_state3_s cn52xx;
4109 struct cvmx_npei_state3_s cn52xxp1;
4110 struct cvmx_npei_state3_s cn56xx;
4111 struct cvmx_npei_state3_s cn56xxp1;
4114 union cvmx_npei_win_rd_addr {
4116 struct cvmx_npei_win_rd_addr_s {
4117 #ifdef __BIG_ENDIAN_BITFIELD
4118 uint64_t reserved_51_63:13;
4121 uint64_t rd_addr:48;
4123 uint64_t rd_addr:48;
4126 uint64_t reserved_51_63:13;
4129 struct cvmx_npei_win_rd_addr_s cn52xx;
4130 struct cvmx_npei_win_rd_addr_s cn52xxp1;
4131 struct cvmx_npei_win_rd_addr_s cn56xx;
4132 struct cvmx_npei_win_rd_addr_s cn56xxp1;
4135 union cvmx_npei_win_rd_data {
4137 struct cvmx_npei_win_rd_data_s {
4138 #ifdef __BIG_ENDIAN_BITFIELD
4139 uint64_t rd_data:64;
4141 uint64_t rd_data:64;
4144 struct cvmx_npei_win_rd_data_s cn52xx;
4145 struct cvmx_npei_win_rd_data_s cn52xxp1;
4146 struct cvmx_npei_win_rd_data_s cn56xx;
4147 struct cvmx_npei_win_rd_data_s cn56xxp1;
4150 union cvmx_npei_win_wr_addr {
4152 struct cvmx_npei_win_wr_addr_s {
4153 #ifdef __BIG_ENDIAN_BITFIELD
4154 uint64_t reserved_49_63:15;
4156 uint64_t wr_addr:46;
4157 uint64_t reserved_0_1:2;
4159 uint64_t reserved_0_1:2;
4160 uint64_t wr_addr:46;
4162 uint64_t reserved_49_63:15;
4165 struct cvmx_npei_win_wr_addr_s cn52xx;
4166 struct cvmx_npei_win_wr_addr_s cn52xxp1;
4167 struct cvmx_npei_win_wr_addr_s cn56xx;
4168 struct cvmx_npei_win_wr_addr_s cn56xxp1;
4171 union cvmx_npei_win_wr_data {
4173 struct cvmx_npei_win_wr_data_s {
4174 #ifdef __BIG_ENDIAN_BITFIELD
4175 uint64_t wr_data:64;
4177 uint64_t wr_data:64;
4180 struct cvmx_npei_win_wr_data_s cn52xx;
4181 struct cvmx_npei_win_wr_data_s cn52xxp1;
4182 struct cvmx_npei_win_wr_data_s cn56xx;
4183 struct cvmx_npei_win_wr_data_s cn56xxp1;
4186 union cvmx_npei_win_wr_mask {
4188 struct cvmx_npei_win_wr_mask_s {
4189 #ifdef __BIG_ENDIAN_BITFIELD
4190 uint64_t reserved_8_63:56;
4194 uint64_t reserved_8_63:56;
4197 struct cvmx_npei_win_wr_mask_s cn52xx;
4198 struct cvmx_npei_win_wr_mask_s cn52xxp1;
4199 struct cvmx_npei_win_wr_mask_s cn56xx;
4200 struct cvmx_npei_win_wr_mask_s cn56xxp1;
4203 union cvmx_npei_window_ctl {
4205 struct cvmx_npei_window_ctl_s {
4206 #ifdef __BIG_ENDIAN_BITFIELD
4207 uint64_t reserved_32_63:32;
4211 uint64_t reserved_32_63:32;
4214 struct cvmx_npei_window_ctl_s cn52xx;
4215 struct cvmx_npei_window_ctl_s cn52xxp1;
4216 struct cvmx_npei_window_ctl_s cn56xx;
4217 struct cvmx_npei_window_ctl_s cn56xxp1;