1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_MIO_DEFS_H__
29 #define __CVMX_MIO_DEFS_H__
31 #define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
32 #define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
33 #define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
34 #define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
35 #define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
36 #define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
37 #define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
38 #define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
39 #define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
40 #define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
41 #define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
42 #define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
43 #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
44 #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
45 #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
46 #define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
47 #define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
48 #define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
49 #define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
50 #define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
51 #define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
52 #define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
53 #define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
54 #define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
55 #define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
56 #define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
57 #define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
58 #define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
59 #define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
60 #define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
61 #define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
62 #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
63 #define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
64 #define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
65 #define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
66 #define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
67 #define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
68 #define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
69 #define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
70 #define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
71 #define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
72 #define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
73 #define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
74 #define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
75 #define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
76 #define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
77 #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
78 #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
79 #define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
80 #define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
81 #define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
82 #define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
83 #define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
84 #define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
85 #define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
86 #define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
87 #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
88 #define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
89 #define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
90 #define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
91 #define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
92 #define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
93 #define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
94 #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
95 #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
96 #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
97 #define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull))
98 #define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
99 #define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
100 #define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
101 #define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
102 #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
103 #define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
104 #define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
105 #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
106 #define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
107 #define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
108 #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
109 #define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
110 #define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
111 #define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
112 #define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
113 #define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
114 #define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
115 #define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
116 #define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
117 #define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
118 #define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
119 #define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
120 #define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
121 #define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
122 #define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
123 #define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
124 #define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
125 #define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
126 #define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
127 #define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
128 #define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
129 #define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
130 #define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
131 #define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
132 #define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
133 #define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
134 #define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
135 #define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
136 #define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
137 #define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
138 #define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
139 #define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
140 #define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
141 #define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
142 #define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
143 #define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
144 #define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
145 #define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
146 #define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
147 #define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
148 #define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
149 #define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
150 #define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
151 #define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
152 #define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
153 #define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
154 #define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
155 #define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
156 #define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
157 #define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
158 #define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
159 #define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
160 #define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
161 #define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
162 #define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
163 #define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
164 #define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
165 #define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
167 union cvmx_mio_boot_bist_stat {
169 struct cvmx_mio_boot_bist_stat_s {
170 #ifdef __BIG_ENDIAN_BITFIELD
171 uint64_t reserved_0_63:64;
173 uint64_t reserved_0_63:64;
176 struct cvmx_mio_boot_bist_stat_cn30xx {
177 #ifdef __BIG_ENDIAN_BITFIELD
178 uint64_t reserved_4_63:60;
188 uint64_t reserved_4_63:60;
191 struct cvmx_mio_boot_bist_stat_cn38xx {
192 #ifdef __BIG_ENDIAN_BITFIELD
193 uint64_t reserved_3_63:61;
201 uint64_t reserved_3_63:61;
204 struct cvmx_mio_boot_bist_stat_cn50xx {
205 #ifdef __BIG_ENDIAN_BITFIELD
206 uint64_t reserved_6_63:58;
220 uint64_t reserved_6_63:58;
223 struct cvmx_mio_boot_bist_stat_cn52xx {
224 #ifdef __BIG_ENDIAN_BITFIELD
225 uint64_t reserved_6_63:58;
237 uint64_t reserved_6_63:58;
240 struct cvmx_mio_boot_bist_stat_cn52xxp1 {
241 #ifdef __BIG_ENDIAN_BITFIELD
242 uint64_t reserved_4_63:60;
252 uint64_t reserved_4_63:60;
255 struct cvmx_mio_boot_bist_stat_cn61xx {
256 #ifdef __BIG_ENDIAN_BITFIELD
257 uint64_t reserved_12_63:52;
261 uint64_t reserved_12_63:52;
264 struct cvmx_mio_boot_bist_stat_cn63xx {
265 #ifdef __BIG_ENDIAN_BITFIELD
266 uint64_t reserved_9_63:55;
270 uint64_t reserved_9_63:55;
273 struct cvmx_mio_boot_bist_stat_cn66xx {
274 #ifdef __BIG_ENDIAN_BITFIELD
275 uint64_t reserved_10_63:54;
279 uint64_t reserved_10_63:54;
284 union cvmx_mio_boot_comp {
286 struct cvmx_mio_boot_comp_s {
287 #ifdef __BIG_ENDIAN_BITFIELD
288 uint64_t reserved_0_63:64;
290 uint64_t reserved_0_63:64;
293 struct cvmx_mio_boot_comp_cn50xx {
294 #ifdef __BIG_ENDIAN_BITFIELD
295 uint64_t reserved_10_63:54;
301 uint64_t reserved_10_63:54;
304 struct cvmx_mio_boot_comp_cn61xx {
305 #ifdef __BIG_ENDIAN_BITFIELD
306 uint64_t reserved_12_63:52;
312 uint64_t reserved_12_63:52;
317 union cvmx_mio_boot_dma_cfgx {
319 struct cvmx_mio_boot_dma_cfgx_s {
320 #ifdef __BIG_ENDIAN_BITFIELD
324 uint64_t reserved_60_60:1;
338 uint64_t reserved_60_60:1;
346 union cvmx_mio_boot_dma_intx {
348 struct cvmx_mio_boot_dma_intx_s {
349 #ifdef __BIG_ENDIAN_BITFIELD
350 uint64_t reserved_2_63:62;
356 uint64_t reserved_2_63:62;
361 union cvmx_mio_boot_dma_int_enx {
363 struct cvmx_mio_boot_dma_int_enx_s {
364 #ifdef __BIG_ENDIAN_BITFIELD
365 uint64_t reserved_2_63:62;
371 uint64_t reserved_2_63:62;
376 union cvmx_mio_boot_dma_timx {
378 struct cvmx_mio_boot_dma_timx_s {
379 #ifdef __BIG_ENDIAN_BITFIELD
386 uint64_t reserved_48_54:7;
404 uint64_t reserved_48_54:7;
415 union cvmx_mio_boot_err {
417 struct cvmx_mio_boot_err_s {
418 #ifdef __BIG_ENDIAN_BITFIELD
419 uint64_t reserved_2_63:62;
425 uint64_t reserved_2_63:62;
430 union cvmx_mio_boot_int {
432 struct cvmx_mio_boot_int_s {
433 #ifdef __BIG_ENDIAN_BITFIELD
434 uint64_t reserved_2_63:62;
440 uint64_t reserved_2_63:62;
445 union cvmx_mio_boot_loc_adr {
447 struct cvmx_mio_boot_loc_adr_s {
448 #ifdef __BIG_ENDIAN_BITFIELD
449 uint64_t reserved_8_63:56;
451 uint64_t reserved_0_2:3;
453 uint64_t reserved_0_2:3;
455 uint64_t reserved_8_63:56;
460 union cvmx_mio_boot_loc_cfgx {
462 struct cvmx_mio_boot_loc_cfgx_s {
463 #ifdef __BIG_ENDIAN_BITFIELD
464 uint64_t reserved_32_63:32;
466 uint64_t reserved_28_30:3;
468 uint64_t reserved_0_2:3;
470 uint64_t reserved_0_2:3;
472 uint64_t reserved_28_30:3;
474 uint64_t reserved_32_63:32;
479 union cvmx_mio_boot_loc_dat {
481 struct cvmx_mio_boot_loc_dat_s {
482 #ifdef __BIG_ENDIAN_BITFIELD
490 union cvmx_mio_boot_pin_defs {
492 struct cvmx_mio_boot_pin_defs_s {
493 #ifdef __BIG_ENDIAN_BITFIELD
494 uint64_t reserved_32_63:32;
514 uint64_t reserved_32_63:32;
517 struct cvmx_mio_boot_pin_defs_cn52xx {
518 #ifdef __BIG_ENDIAN_BITFIELD
519 uint64_t reserved_16_63:48;
522 uint64_t reserved_13_13:1;
527 uint64_t reserved_0_7:8;
529 uint64_t reserved_0_7:8;
534 uint64_t reserved_13_13:1;
537 uint64_t reserved_16_63:48;
540 struct cvmx_mio_boot_pin_defs_cn56xx {
541 #ifdef __BIG_ENDIAN_BITFIELD
542 uint64_t reserved_16_63:48;
549 uint64_t reserved_0_8:9;
551 uint64_t reserved_0_8:9;
558 uint64_t reserved_16_63:48;
561 struct cvmx_mio_boot_pin_defs_cn61xx {
562 #ifdef __BIG_ENDIAN_BITFIELD
563 uint64_t reserved_32_63:32;
567 uint64_t reserved_13_13:1;
579 uint64_t reserved_13_13:1;
583 uint64_t reserved_32_63:32;
588 union cvmx_mio_boot_reg_cfgx {
590 struct cvmx_mio_boot_reg_cfgx_s {
591 #ifdef __BIG_ENDIAN_BITFIELD
592 uint64_t reserved_44_63:20;
618 uint64_t reserved_44_63:20;
621 struct cvmx_mio_boot_reg_cfgx_cn30xx {
622 #ifdef __BIG_ENDIAN_BITFIELD
623 uint64_t reserved_37_63:27;
643 uint64_t reserved_37_63:27;
646 struct cvmx_mio_boot_reg_cfgx_cn38xx {
647 #ifdef __BIG_ENDIAN_BITFIELD
648 uint64_t reserved_32_63:32;
651 uint64_t reserved_28_29:2;
657 uint64_t reserved_28_29:2;
660 uint64_t reserved_32_63:32;
663 struct cvmx_mio_boot_reg_cfgx_cn50xx {
664 #ifdef __BIG_ENDIAN_BITFIELD
665 uint64_t reserved_42_63:22;
689 uint64_t reserved_42_63:22;
694 union cvmx_mio_boot_reg_timx {
696 struct cvmx_mio_boot_reg_timx_s {
697 #ifdef __BIG_ENDIAN_BITFIELD
727 struct cvmx_mio_boot_reg_timx_cn38xx {
728 #ifdef __BIG_ENDIAN_BITFIELD
732 uint64_t reserved_54_59:6;
752 uint64_t reserved_54_59:6;
760 union cvmx_mio_boot_thr {
762 struct cvmx_mio_boot_thr_s {
763 #ifdef __BIG_ENDIAN_BITFIELD
764 uint64_t reserved_22_63:42;
766 uint64_t reserved_14_15:2;
768 uint64_t reserved_6_7:2;
772 uint64_t reserved_6_7:2;
774 uint64_t reserved_14_15:2;
776 uint64_t reserved_22_63:42;
779 struct cvmx_mio_boot_thr_cn30xx {
780 #ifdef __BIG_ENDIAN_BITFIELD
781 uint64_t reserved_14_63:50;
783 uint64_t reserved_6_7:2;
787 uint64_t reserved_6_7:2;
789 uint64_t reserved_14_63:50;
794 union cvmx_mio_emm_buf_dat {
796 struct cvmx_mio_emm_buf_dat_s {
797 #ifdef __BIG_ENDIAN_BITFIELD
805 union cvmx_mio_emm_buf_idx {
807 struct cvmx_mio_emm_buf_idx_s {
808 #ifdef __BIG_ENDIAN_BITFIELD
809 uint64_t reserved_17_63:47;
811 uint64_t reserved_7_15:9;
817 uint64_t reserved_7_15:9;
819 uint64_t reserved_17_63:47;
824 union cvmx_mio_emm_cfg {
826 struct cvmx_mio_emm_cfg_s {
827 #ifdef __BIG_ENDIAN_BITFIELD
828 uint64_t reserved_17_63:47;
829 uint64_t boot_fail:1;
830 uint64_t reserved_4_15:12;
834 uint64_t reserved_4_15:12;
835 uint64_t boot_fail:1;
836 uint64_t reserved_17_63:47;
841 union cvmx_mio_emm_cmd {
843 struct cvmx_mio_emm_cmd_s {
844 #ifdef __BIG_ENDIAN_BITFIELD
845 uint64_t reserved_62_63:2;
848 uint64_t reserved_56_58:3;
851 uint64_t reserved_43_48:6;
852 uint64_t ctype_xor:2;
853 uint64_t rtype_xor:3;
859 uint64_t rtype_xor:3;
860 uint64_t ctype_xor:2;
861 uint64_t reserved_43_48:6;
864 uint64_t reserved_56_58:3;
867 uint64_t reserved_62_63:2;
872 union cvmx_mio_emm_dma {
874 struct cvmx_mio_emm_dma_s {
875 #ifdef __BIG_ENDIAN_BITFIELD
876 uint64_t reserved_62_63:2;
885 uint64_t block_cnt:16;
886 uint64_t card_addr:32;
888 uint64_t card_addr:32;
889 uint64_t block_cnt:16;
898 uint64_t reserved_62_63:2;
903 union cvmx_mio_emm_int {
905 struct cvmx_mio_emm_int_s {
906 #ifdef __BIG_ENDIAN_BITFIELD
907 uint64_t reserved_7_63:57;
908 uint64_t switch_err:1;
909 uint64_t switch_done:1;
921 uint64_t switch_done:1;
922 uint64_t switch_err:1;
923 uint64_t reserved_7_63:57;
928 union cvmx_mio_emm_int_en {
930 struct cvmx_mio_emm_int_en_s {
931 #ifdef __BIG_ENDIAN_BITFIELD
932 uint64_t reserved_7_63:57;
933 uint64_t switch_err:1;
934 uint64_t switch_done:1;
946 uint64_t switch_done:1;
947 uint64_t switch_err:1;
948 uint64_t reserved_7_63:57;
953 union cvmx_mio_emm_modex {
955 struct cvmx_mio_emm_modex_s {
956 #ifdef __BIG_ENDIAN_BITFIELD
957 uint64_t reserved_49_63:15;
958 uint64_t hs_timing:1;
959 uint64_t reserved_43_47:5;
960 uint64_t bus_width:3;
961 uint64_t reserved_36_39:4;
962 uint64_t power_class:4;
968 uint64_t power_class:4;
969 uint64_t reserved_36_39:4;
970 uint64_t bus_width:3;
971 uint64_t reserved_43_47:5;
972 uint64_t hs_timing:1;
973 uint64_t reserved_49_63:15;
978 union cvmx_mio_emm_rca {
980 struct cvmx_mio_emm_rca_s {
981 #ifdef __BIG_ENDIAN_BITFIELD
982 uint64_t reserved_16_63:48;
983 uint64_t card_rca:16;
985 uint64_t card_rca:16;
986 uint64_t reserved_16_63:48;
991 union cvmx_mio_emm_rsp_hi {
993 struct cvmx_mio_emm_rsp_hi_s {
994 #ifdef __BIG_ENDIAN_BITFIELD
1002 union cvmx_mio_emm_rsp_lo {
1004 struct cvmx_mio_emm_rsp_lo_s {
1005 #ifdef __BIG_ENDIAN_BITFIELD
1013 union cvmx_mio_emm_rsp_sts {
1015 struct cvmx_mio_emm_rsp_sts_s {
1016 #ifdef __BIG_ENDIAN_BITFIELD
1017 uint64_t reserved_62_63:2;
1020 uint64_t switch_val:1;
1022 uint64_t dma_pend:1;
1023 uint64_t reserved_29_55:27;
1024 uint64_t dbuf_err:1;
1025 uint64_t reserved_24_27:4;
1027 uint64_t blk_timeout:1;
1028 uint64_t blk_crc_err:1;
1029 uint64_t rsp_busybit:1;
1030 uint64_t stp_timeout:1;
1031 uint64_t stp_crc_err:1;
1032 uint64_t stp_bad_sts:1;
1034 uint64_t rsp_timeout:1;
1035 uint64_t rsp_crc_err:1;
1036 uint64_t rsp_bad_sts:1;
1038 uint64_t rsp_type:3;
1039 uint64_t cmd_type:2;
1041 uint64_t cmd_done:1;
1043 uint64_t cmd_done:1;
1045 uint64_t cmd_type:2;
1046 uint64_t rsp_type:3;
1048 uint64_t rsp_bad_sts:1;
1049 uint64_t rsp_crc_err:1;
1050 uint64_t rsp_timeout:1;
1052 uint64_t stp_bad_sts:1;
1053 uint64_t stp_crc_err:1;
1054 uint64_t stp_timeout:1;
1055 uint64_t rsp_busybit:1;
1056 uint64_t blk_crc_err:1;
1057 uint64_t blk_timeout:1;
1059 uint64_t reserved_24_27:4;
1060 uint64_t dbuf_err:1;
1061 uint64_t reserved_29_55:27;
1062 uint64_t dma_pend:1;
1064 uint64_t switch_val:1;
1067 uint64_t reserved_62_63:2;
1072 union cvmx_mio_emm_sample {
1074 struct cvmx_mio_emm_sample_s {
1075 #ifdef __BIG_ENDIAN_BITFIELD
1076 uint64_t reserved_26_63:38;
1077 uint64_t cmd_cnt:10;
1078 uint64_t reserved_10_15:6;
1079 uint64_t dat_cnt:10;
1081 uint64_t dat_cnt:10;
1082 uint64_t reserved_10_15:6;
1083 uint64_t cmd_cnt:10;
1084 uint64_t reserved_26_63:38;
1089 union cvmx_mio_emm_sts_mask {
1091 struct cvmx_mio_emm_sts_mask_s {
1092 #ifdef __BIG_ENDIAN_BITFIELD
1093 uint64_t reserved_32_63:32;
1094 uint64_t sts_msk:32;
1096 uint64_t sts_msk:32;
1097 uint64_t reserved_32_63:32;
1102 union cvmx_mio_emm_switch {
1104 struct cvmx_mio_emm_switch_s {
1105 #ifdef __BIG_ENDIAN_BITFIELD
1106 uint64_t reserved_62_63:2;
1108 uint64_t switch_exe:1;
1109 uint64_t switch_err0:1;
1110 uint64_t switch_err1:1;
1111 uint64_t switch_err2:1;
1112 uint64_t reserved_49_55:7;
1113 uint64_t hs_timing:1;
1114 uint64_t reserved_43_47:5;
1115 uint64_t bus_width:3;
1116 uint64_t reserved_36_39:4;
1117 uint64_t power_class:4;
1123 uint64_t power_class:4;
1124 uint64_t reserved_36_39:4;
1125 uint64_t bus_width:3;
1126 uint64_t reserved_43_47:5;
1127 uint64_t hs_timing:1;
1128 uint64_t reserved_49_55:7;
1129 uint64_t switch_err2:1;
1130 uint64_t switch_err1:1;
1131 uint64_t switch_err0:1;
1132 uint64_t switch_exe:1;
1134 uint64_t reserved_62_63:2;
1139 union cvmx_mio_emm_wdog {
1141 struct cvmx_mio_emm_wdog_s {
1142 #ifdef __BIG_ENDIAN_BITFIELD
1143 uint64_t reserved_26_63:38;
1144 uint64_t clk_cnt:26;
1146 uint64_t clk_cnt:26;
1147 uint64_t reserved_26_63:38;
1152 union cvmx_mio_fus_bnk_datx {
1154 struct cvmx_mio_fus_bnk_datx_s {
1155 #ifdef __BIG_ENDIAN_BITFIELD
1163 union cvmx_mio_fus_dat0 {
1165 struct cvmx_mio_fus_dat0_s {
1166 #ifdef __BIG_ENDIAN_BITFIELD
1167 uint64_t reserved_32_63:32;
1168 uint64_t man_info:32;
1170 uint64_t man_info:32;
1171 uint64_t reserved_32_63:32;
1176 union cvmx_mio_fus_dat1 {
1178 struct cvmx_mio_fus_dat1_s {
1179 #ifdef __BIG_ENDIAN_BITFIELD
1180 uint64_t reserved_32_63:32;
1181 uint64_t man_info:32;
1183 uint64_t man_info:32;
1184 uint64_t reserved_32_63:32;
1189 union cvmx_mio_fus_dat2 {
1191 struct cvmx_mio_fus_dat2_s {
1192 #ifdef __BIG_ENDIAN_BITFIELD
1193 uint64_t reserved_59_63:5;
1194 uint64_t run_platform:3;
1195 uint64_t gbl_pwr_throttle:8;
1197 uint64_t rom_info:10;
1198 uint64_t power_limit:2;
1199 uint64_t dorm_crypto:1;
1202 uint64_t reserved_30_31:2;
1204 uint64_t nodfa_cp2:1;
1206 uint64_t nocrypto:1;
1208 uint64_t bist_dis:1;
1210 uint64_t reserved_0_15:16;
1212 uint64_t reserved_0_15:16;
1214 uint64_t bist_dis:1;
1216 uint64_t nocrypto:1;
1218 uint64_t nodfa_cp2:1;
1220 uint64_t reserved_30_31:2;
1223 uint64_t dorm_crypto:1;
1224 uint64_t power_limit:2;
1225 uint64_t rom_info:10;
1227 uint64_t gbl_pwr_throttle:8;
1228 uint64_t run_platform:3;
1229 uint64_t reserved_59_63:5;
1232 struct cvmx_mio_fus_dat2_cn30xx {
1233 #ifdef __BIG_ENDIAN_BITFIELD
1234 uint64_t reserved_29_63:35;
1235 uint64_t nodfa_cp2:1;
1237 uint64_t nocrypto:1;
1239 uint64_t bist_dis:1;
1242 uint64_t reserved_1_11:11;
1246 uint64_t reserved_1_11:11;
1249 uint64_t bist_dis:1;
1251 uint64_t nocrypto:1;
1253 uint64_t nodfa_cp2:1;
1254 uint64_t reserved_29_63:35;
1257 struct cvmx_mio_fus_dat2_cn31xx {
1258 #ifdef __BIG_ENDIAN_BITFIELD
1259 uint64_t reserved_29_63:35;
1260 uint64_t nodfa_cp2:1;
1262 uint64_t nocrypto:1;
1264 uint64_t bist_dis:1;
1267 uint64_t reserved_2_11:10;
1271 uint64_t reserved_2_11:10;
1274 uint64_t bist_dis:1;
1276 uint64_t nocrypto:1;
1278 uint64_t nodfa_cp2:1;
1279 uint64_t reserved_29_63:35;
1282 struct cvmx_mio_fus_dat2_cn38xx {
1283 #ifdef __BIG_ENDIAN_BITFIELD
1284 uint64_t reserved_29_63:35;
1285 uint64_t nodfa_cp2:1;
1287 uint64_t nocrypto:1;
1289 uint64_t bist_dis:1;
1295 uint64_t bist_dis:1;
1297 uint64_t nocrypto:1;
1299 uint64_t nodfa_cp2:1;
1300 uint64_t reserved_29_63:35;
1303 struct cvmx_mio_fus_dat2_cn50xx {
1304 #ifdef __BIG_ENDIAN_BITFIELD
1305 uint64_t reserved_34_63:30;
1308 uint64_t reserved_30_31:2;
1310 uint64_t nodfa_cp2:1;
1312 uint64_t nocrypto:1;
1314 uint64_t bist_dis:1;
1316 uint64_t reserved_2_15:14;
1320 uint64_t reserved_2_15:14;
1322 uint64_t bist_dis:1;
1324 uint64_t nocrypto:1;
1326 uint64_t nodfa_cp2:1;
1328 uint64_t reserved_30_31:2;
1331 uint64_t reserved_34_63:30;
1334 struct cvmx_mio_fus_dat2_cn52xx {
1335 #ifdef __BIG_ENDIAN_BITFIELD
1336 uint64_t reserved_34_63:30;
1339 uint64_t reserved_30_31:2;
1341 uint64_t nodfa_cp2:1;
1343 uint64_t nocrypto:1;
1345 uint64_t bist_dis:1;
1347 uint64_t reserved_4_15:12;
1351 uint64_t reserved_4_15:12;
1353 uint64_t bist_dis:1;
1355 uint64_t nocrypto:1;
1357 uint64_t nodfa_cp2:1;
1359 uint64_t reserved_30_31:2;
1362 uint64_t reserved_34_63:30;
1365 struct cvmx_mio_fus_dat2_cn56xx {
1366 #ifdef __BIG_ENDIAN_BITFIELD
1367 uint64_t reserved_34_63:30;
1370 uint64_t reserved_30_31:2;
1372 uint64_t nodfa_cp2:1;
1374 uint64_t nocrypto:1;
1376 uint64_t bist_dis:1;
1378 uint64_t reserved_12_15:4;
1382 uint64_t reserved_12_15:4;
1384 uint64_t bist_dis:1;
1386 uint64_t nocrypto:1;
1388 uint64_t nodfa_cp2:1;
1390 uint64_t reserved_30_31:2;
1393 uint64_t reserved_34_63:30;
1396 struct cvmx_mio_fus_dat2_cn58xx {
1397 #ifdef __BIG_ENDIAN_BITFIELD
1398 uint64_t reserved_30_63:34;
1400 uint64_t nodfa_cp2:1;
1402 uint64_t nocrypto:1;
1404 uint64_t bist_dis:1;
1410 uint64_t bist_dis:1;
1412 uint64_t nocrypto:1;
1414 uint64_t nodfa_cp2:1;
1416 uint64_t reserved_30_63:34;
1419 struct cvmx_mio_fus_dat2_cn61xx {
1420 #ifdef __BIG_ENDIAN_BITFIELD
1421 uint64_t reserved_48_63:16;
1423 uint64_t rom_info:10;
1424 uint64_t power_limit:2;
1425 uint64_t dorm_crypto:1;
1428 uint64_t reserved_29_31:3;
1429 uint64_t nodfa_cp2:1;
1431 uint64_t nocrypto:1;
1432 uint64_t reserved_24_25:2;
1434 uint64_t reserved_4_15:12;
1438 uint64_t reserved_4_15:12;
1440 uint64_t reserved_24_25:2;
1441 uint64_t nocrypto:1;
1443 uint64_t nodfa_cp2:1;
1444 uint64_t reserved_29_31:3;
1447 uint64_t dorm_crypto:1;
1448 uint64_t power_limit:2;
1449 uint64_t rom_info:10;
1451 uint64_t reserved_48_63:16;
1454 struct cvmx_mio_fus_dat2_cn63xx {
1455 #ifdef __BIG_ENDIAN_BITFIELD
1456 uint64_t reserved_35_63:29;
1457 uint64_t dorm_crypto:1;
1460 uint64_t reserved_29_31:3;
1461 uint64_t nodfa_cp2:1;
1463 uint64_t nocrypto:1;
1464 uint64_t reserved_24_25:2;
1466 uint64_t reserved_6_15:10;
1470 uint64_t reserved_6_15:10;
1472 uint64_t reserved_24_25:2;
1473 uint64_t nocrypto:1;
1475 uint64_t nodfa_cp2:1;
1476 uint64_t reserved_29_31:3;
1479 uint64_t dorm_crypto:1;
1480 uint64_t reserved_35_63:29;
1483 struct cvmx_mio_fus_dat2_cn66xx {
1484 #ifdef __BIG_ENDIAN_BITFIELD
1485 uint64_t reserved_48_63:16;
1487 uint64_t rom_info:10;
1488 uint64_t power_limit:2;
1489 uint64_t dorm_crypto:1;
1492 uint64_t reserved_29_31:3;
1493 uint64_t nodfa_cp2:1;
1495 uint64_t nocrypto:1;
1496 uint64_t reserved_24_25:2;
1498 uint64_t reserved_10_15:6;
1502 uint64_t reserved_10_15:6;
1504 uint64_t reserved_24_25:2;
1505 uint64_t nocrypto:1;
1507 uint64_t nodfa_cp2:1;
1508 uint64_t reserved_29_31:3;
1511 uint64_t dorm_crypto:1;
1512 uint64_t power_limit:2;
1513 uint64_t rom_info:10;
1515 uint64_t reserved_48_63:16;
1518 struct cvmx_mio_fus_dat2_cn68xx {
1519 #ifdef __BIG_ENDIAN_BITFIELD
1520 uint64_t reserved_37_63:27;
1521 uint64_t power_limit:2;
1522 uint64_t dorm_crypto:1;
1525 uint64_t reserved_29_31:3;
1526 uint64_t nodfa_cp2:1;
1528 uint64_t nocrypto:1;
1529 uint64_t reserved_24_25:2;
1531 uint64_t reserved_0_15:16;
1533 uint64_t reserved_0_15:16;
1535 uint64_t reserved_24_25:2;
1536 uint64_t nocrypto:1;
1538 uint64_t nodfa_cp2:1;
1539 uint64_t reserved_29_31:3;
1542 uint64_t dorm_crypto:1;
1543 uint64_t power_limit:2;
1544 uint64_t reserved_37_63:27;
1547 struct cvmx_mio_fus_dat2_cn70xx {
1548 #ifdef __BIG_ENDIAN_BITFIELD
1549 uint64_t reserved_48_63:16;
1551 uint64_t rom_info:10;
1552 uint64_t power_limit:2;
1553 uint64_t dorm_crypto:1;
1556 uint64_t reserved_31_29:3;
1557 uint64_t nodfa_cp2:1;
1559 uint64_t nocrypto:1;
1560 uint64_t reserved_25_24:2;
1562 uint64_t reserved_15_0:16;
1564 uint64_t reserved_15_0:16;
1566 uint64_t reserved_25_24:2;
1567 uint64_t nocrypto:1;
1569 uint64_t nodfa_cp2:1;
1570 uint64_t reserved_31_29:3;
1573 uint64_t dorm_crypto:1;
1574 uint64_t power_limit:2;
1575 uint64_t rom_info:10;
1577 uint64_t reserved_48_63:16;
1580 struct cvmx_mio_fus_dat2_cn73xx {
1581 #ifdef __BIG_ENDIAN_BITFIELD
1582 uint64_t reserved_59_63:5;
1583 uint64_t run_platform:3;
1584 uint64_t gbl_pwr_throttle:8;
1586 uint64_t rom_info:10;
1587 uint64_t power_limit:2;
1588 uint64_t dorm_crypto:1;
1591 uint64_t reserved_31_29:3;
1592 uint64_t nodfa_cp2:1;
1594 uint64_t nocrypto:1;
1595 uint64_t reserved_25_24:2;
1597 uint64_t reserved_15_0:16;
1599 uint64_t reserved_15_0:16;
1601 uint64_t reserved_25_24:2;
1602 uint64_t nocrypto:1;
1604 uint64_t nodfa_cp2:1;
1605 uint64_t reserved_31_29:3;
1608 uint64_t dorm_crypto:1;
1609 uint64_t power_limit:2;
1610 uint64_t rom_info:10;
1612 uint64_t gbl_pwr_throttle:8;
1613 uint64_t run_platform:3;
1614 uint64_t reserved_59_63:5;
1617 struct cvmx_mio_fus_dat2_cn78xx {
1618 #ifdef __BIG_ENDIAN_BITFIELD
1619 uint64_t reserved_59_63:5;
1620 uint64_t run_platform:3;
1621 uint64_t reserved_48_55:8;
1623 uint64_t rom_info:10;
1624 uint64_t power_limit:2;
1625 uint64_t dorm_crypto:1;
1628 uint64_t reserved_31_29:3;
1629 uint64_t nodfa_cp2:1;
1631 uint64_t nocrypto:1;
1632 uint64_t reserved_25_24:2;
1634 uint64_t reserved_0_15:16;
1636 uint64_t reserved_0_15:16;
1638 uint64_t reserved_25_24:2;
1639 uint64_t nocrypto:1;
1641 uint64_t nodfa_cp2:1;
1642 uint64_t reserved_31_29:3;
1645 uint64_t dorm_crypto:1;
1646 uint64_t power_limit:2;
1647 uint64_t rom_info:10;
1649 uint64_t reserved_48_55:8;
1650 uint64_t run_platform:3;
1651 uint64_t reserved_59_63:5;
1654 struct cvmx_mio_fus_dat2_cn78xxp2 {
1655 #ifdef __BIG_ENDIAN_BITFIELD
1656 uint64_t reserved_59_63:5;
1657 uint64_t run_platform:3;
1658 uint64_t gbl_pwr_throttle:8;
1660 uint64_t rom_info:10;
1661 uint64_t power_limit:2;
1662 uint64_t dorm_crypto:1;
1665 uint64_t reserved_31_29:3;
1666 uint64_t nodfa_cp2:1;
1668 uint64_t nocrypto:1;
1669 uint64_t reserved_25_24:2;
1671 uint64_t reserved_0_15:16;
1673 uint64_t reserved_0_15:16;
1675 uint64_t reserved_25_24:2;
1676 uint64_t nocrypto:1;
1678 uint64_t nodfa_cp2:1;
1679 uint64_t reserved_31_29:3;
1682 uint64_t dorm_crypto:1;
1683 uint64_t power_limit:2;
1684 uint64_t rom_info:10;
1686 uint64_t gbl_pwr_throttle:8;
1687 uint64_t run_platform:3;
1688 uint64_t reserved_59_63:5;
1693 union cvmx_mio_fus_dat3 {
1695 struct cvmx_mio_fus_dat3_s {
1696 #ifdef __BIG_ENDIAN_BITFIELD
1698 uint64_t pll_ctl:10;
1699 uint64_t dfa_info_dte:3;
1700 uint64_t dfa_info_clm:4;
1701 uint64_t pll_alt_matrix:1;
1702 uint64_t reserved_38_39:2;
1703 uint64_t efus_lck_rsv:1;
1704 uint64_t efus_lck_man:1;
1705 uint64_t pll_half_dis:1;
1706 uint64_t l2c_crip:3;
1707 uint64_t reserved_28_31:4;
1708 uint64_t efus_lck:1;
1709 uint64_t efus_ign:1;
1711 uint64_t nodfa_dte:1;
1712 uint64_t reserved_0_23:24;
1714 uint64_t reserved_0_23:24;
1715 uint64_t nodfa_dte:1;
1717 uint64_t efus_ign:1;
1718 uint64_t efus_lck:1;
1719 uint64_t reserved_28_31:4;
1720 uint64_t l2c_crip:3;
1721 uint64_t pll_half_dis:1;
1722 uint64_t efus_lck_man:1;
1723 uint64_t efus_lck_rsv:1;
1724 uint64_t reserved_38_39:2;
1725 uint64_t pll_alt_matrix:1;
1726 uint64_t dfa_info_clm:4;
1727 uint64_t dfa_info_dte:3;
1728 uint64_t pll_ctl:10;
1732 struct cvmx_mio_fus_dat3_cn30xx {
1733 #ifdef __BIG_ENDIAN_BITFIELD
1734 uint64_t reserved_32_63:32;
1735 uint64_t pll_div4:1;
1736 uint64_t reserved_29_30:2;
1738 uint64_t efus_lck:1;
1739 uint64_t efus_ign:1;
1741 uint64_t nodfa_dte:1;
1745 uint64_t nodfa_dte:1;
1747 uint64_t efus_ign:1;
1748 uint64_t efus_lck:1;
1750 uint64_t reserved_29_30:2;
1751 uint64_t pll_div4:1;
1752 uint64_t reserved_32_63:32;
1755 struct cvmx_mio_fus_dat3_cn31xx {
1756 #ifdef __BIG_ENDIAN_BITFIELD
1757 uint64_t reserved_32_63:32;
1758 uint64_t pll_div4:1;
1759 uint64_t zip_crip:2;
1761 uint64_t efus_lck:1;
1762 uint64_t efus_ign:1;
1764 uint64_t nodfa_dte:1;
1768 uint64_t nodfa_dte:1;
1770 uint64_t efus_ign:1;
1771 uint64_t efus_lck:1;
1773 uint64_t zip_crip:2;
1774 uint64_t pll_div4:1;
1775 uint64_t reserved_32_63:32;
1778 struct cvmx_mio_fus_dat3_cn38xx {
1779 #ifdef __BIG_ENDIAN_BITFIELD
1780 uint64_t reserved_31_63:33;
1781 uint64_t zip_crip:2;
1783 uint64_t efus_lck:1;
1784 uint64_t efus_ign:1;
1786 uint64_t nodfa_dte:1;
1790 uint64_t nodfa_dte:1;
1792 uint64_t efus_ign:1;
1793 uint64_t efus_lck:1;
1795 uint64_t zip_crip:2;
1796 uint64_t reserved_31_63:33;
1799 struct cvmx_mio_fus_dat3_cn38xxp2 {
1800 #ifdef __BIG_ENDIAN_BITFIELD
1801 uint64_t reserved_29_63:35;
1803 uint64_t efus_lck:1;
1804 uint64_t efus_ign:1;
1806 uint64_t nodfa_dte:1;
1810 uint64_t nodfa_dte:1;
1812 uint64_t efus_ign:1;
1813 uint64_t efus_lck:1;
1815 uint64_t reserved_29_63:35;
1818 struct cvmx_mio_fus_dat3_cn61xx {
1819 #ifdef __BIG_ENDIAN_BITFIELD
1820 uint64_t reserved_58_63:6;
1821 uint64_t pll_ctl:10;
1822 uint64_t dfa_info_dte:3;
1823 uint64_t dfa_info_clm:4;
1824 uint64_t reserved_40_40:1;
1826 uint64_t efus_lck_rsv:1;
1827 uint64_t efus_lck_man:1;
1828 uint64_t pll_half_dis:1;
1829 uint64_t l2c_crip:3;
1830 uint64_t reserved_31_31:1;
1831 uint64_t zip_info:2;
1833 uint64_t efus_lck:1;
1834 uint64_t efus_ign:1;
1836 uint64_t nodfa_dte:1;
1837 uint64_t reserved_0_23:24;
1839 uint64_t reserved_0_23:24;
1840 uint64_t nodfa_dte:1;
1842 uint64_t efus_ign:1;
1843 uint64_t efus_lck:1;
1845 uint64_t zip_info:2;
1846 uint64_t reserved_31_31:1;
1847 uint64_t l2c_crip:3;
1848 uint64_t pll_half_dis:1;
1849 uint64_t efus_lck_man:1;
1850 uint64_t efus_lck_rsv:1;
1852 uint64_t reserved_40_40:1;
1853 uint64_t dfa_info_clm:4;
1854 uint64_t dfa_info_dte:3;
1855 uint64_t pll_ctl:10;
1856 uint64_t reserved_58_63:6;
1859 struct cvmx_mio_fus_dat3_cn70xx {
1860 #ifdef __BIG_ENDIAN_BITFIELD
1862 uint64_t pll_ctl:10;
1863 uint64_t dfa_info_dte:3;
1864 uint64_t dfa_info_clm:4;
1865 uint64_t pll_alt_matrix:1;
1866 uint64_t pll_bwadj_denom:2;
1867 uint64_t efus_lck_rsv:1;
1868 uint64_t efus_lck_man:1;
1869 uint64_t pll_half_dis:1;
1870 uint64_t l2c_crip:3;
1871 uint64_t use_int_refclk:1;
1872 uint64_t zip_info:2;
1873 uint64_t bar2_sz_conf:1;
1874 uint64_t efus_lck:1;
1875 uint64_t efus_ign:1;
1877 uint64_t nodfa_dte:1;
1879 uint64_t reserved_0_17:18;
1881 uint64_t reserved_0_17:18;
1883 uint64_t nodfa_dte:1;
1885 uint64_t efus_ign:1;
1886 uint64_t efus_lck:1;
1887 uint64_t bar2_sz_conf:1;
1888 uint64_t zip_info:2;
1889 uint64_t use_int_refclk:1;
1890 uint64_t l2c_crip:3;
1891 uint64_t pll_half_dis:1;
1892 uint64_t efus_lck_man:1;
1893 uint64_t efus_lck_rsv:1;
1894 uint64_t pll_bwadj_denom:2;
1895 uint64_t pll_alt_matrix:1;
1896 uint64_t dfa_info_clm:4;
1897 uint64_t dfa_info_dte:3;
1898 uint64_t pll_ctl:10;
1902 struct cvmx_mio_fus_dat3_cn70xxp1 {
1903 #ifdef __BIG_ENDIAN_BITFIELD
1905 uint64_t pll_ctl:10;
1906 uint64_t dfa_info_dte:3;
1907 uint64_t dfa_info_clm:4;
1908 uint64_t reserved_38_40:3;
1909 uint64_t efus_lck_rsv:1;
1910 uint64_t efus_lck_man:1;
1911 uint64_t pll_half_dis:1;
1912 uint64_t l2c_crip:3;
1913 uint64_t reserved_31_31:1;
1914 uint64_t zip_info:2;
1915 uint64_t bar2_sz_conf:1;
1916 uint64_t efus_lck:1;
1917 uint64_t efus_ign:1;
1919 uint64_t nodfa_dte:1;
1921 uint64_t reserved_0_17:18;
1923 uint64_t reserved_0_17:18;
1925 uint64_t nodfa_dte:1;
1927 uint64_t efus_ign:1;
1928 uint64_t efus_lck:1;
1929 uint64_t bar2_sz_conf:1;
1930 uint64_t zip_info:2;
1931 uint64_t reserved_31_31:1;
1932 uint64_t l2c_crip:3;
1933 uint64_t pll_half_dis:1;
1934 uint64_t efus_lck_man:1;
1935 uint64_t efus_lck_rsv:1;
1936 uint64_t reserved_38_40:3;
1937 uint64_t dfa_info_clm:4;
1938 uint64_t dfa_info_dte:3;
1939 uint64_t pll_ctl:10;
1943 struct cvmx_mio_fus_dat3_cn73xx {
1944 #ifdef __BIG_ENDIAN_BITFIELD
1946 uint64_t pll_ctl:10;
1947 uint64_t dfa_info_dte:3;
1948 uint64_t dfa_info_clm:4;
1949 uint64_t pll_alt_matrix:1;
1950 uint64_t pll_bwadj_denom:2;
1951 uint64_t efus_lck_rsv:1;
1952 uint64_t efus_lck_man:1;
1953 uint64_t pll_half_dis:1;
1954 uint64_t l2c_crip:3;
1955 uint64_t use_int_refclk:1;
1956 uint64_t zip_info:2;
1957 uint64_t bar2_sz_conf:1;
1958 uint64_t efus_lck:1;
1959 uint64_t efus_ign:1;
1961 uint64_t nodfa_dte:1;
1963 uint64_t nohna_dte:1;
1964 uint64_t hna_info_dte:3;
1965 uint64_t hna_info_clm:4;
1966 uint64_t reserved_9_9:1;
1967 uint64_t core_pll_mul:5;
1968 uint64_t pnr_pll_mul:4;
1970 uint64_t pnr_pll_mul:4;
1971 uint64_t core_pll_mul:5;
1972 uint64_t reserved_9_9:1;
1973 uint64_t hna_info_clm:4;
1974 uint64_t hna_info_dte:3;
1975 uint64_t nohna_dte:1;
1977 uint64_t nodfa_dte:1;
1979 uint64_t efus_ign:1;
1980 uint64_t efus_lck:1;
1981 uint64_t bar2_sz_conf:1;
1982 uint64_t zip_info:2;
1983 uint64_t use_int_refclk:1;
1984 uint64_t l2c_crip:3;
1985 uint64_t pll_half_dis:1;
1986 uint64_t efus_lck_man:1;
1987 uint64_t efus_lck_rsv:1;
1988 uint64_t pll_bwadj_denom:2;
1989 uint64_t pll_alt_matrix:1;
1990 uint64_t dfa_info_clm:4;
1991 uint64_t dfa_info_dte:3;
1992 uint64_t pll_ctl:10;
1996 struct cvmx_mio_fus_dat3_cn78xx {
1997 #ifdef __BIG_ENDIAN_BITFIELD
1999 uint64_t pll_ctl:10;
2000 uint64_t dfa_info_dte:3;
2001 uint64_t dfa_info_clm:4;
2002 uint64_t reserved_38_40:3;
2003 uint64_t efus_lck_rsv:1;
2004 uint64_t efus_lck_man:1;
2005 uint64_t pll_half_dis:1;
2006 uint64_t l2c_crip:3;
2007 uint64_t reserved_31_31:1;
2008 uint64_t zip_info:2;
2009 uint64_t bar2_sz_conf:1;
2010 uint64_t efus_lck:1;
2011 uint64_t efus_ign:1;
2013 uint64_t nodfa_dte:1;
2015 uint64_t nohna_dte:1;
2016 uint64_t hna_info_dte:3;
2017 uint64_t hna_info_clm:4;
2018 uint64_t reserved_0_9:10;
2020 uint64_t reserved_0_9:10;
2021 uint64_t hna_info_clm:4;
2022 uint64_t hna_info_dte:3;
2023 uint64_t nohna_dte:1;
2025 uint64_t nodfa_dte:1;
2027 uint64_t efus_ign:1;
2028 uint64_t efus_lck:1;
2029 uint64_t bar2_sz_conf:1;
2030 uint64_t zip_info:2;
2031 uint64_t reserved_31_31:1;
2032 uint64_t l2c_crip:3;
2033 uint64_t pll_half_dis:1;
2034 uint64_t efus_lck_man:1;
2035 uint64_t efus_lck_rsv:1;
2036 uint64_t reserved_38_40:3;
2037 uint64_t dfa_info_clm:4;
2038 uint64_t dfa_info_dte:3;
2039 uint64_t pll_ctl:10;
2043 struct cvmx_mio_fus_dat3_cnf75xx {
2044 #ifdef __BIG_ENDIAN_BITFIELD
2046 uint64_t pll_ctl:10;
2047 uint64_t dfa_info_dte:3;
2048 uint64_t dfa_info_clm:4;
2049 uint64_t pll_alt_matrix:1;
2050 uint64_t pll_bwadj_denom:2;
2051 uint64_t efus_lck_rsv:1;
2052 uint64_t efus_lck_man:1;
2053 uint64_t pll_half_dis:1;
2054 uint64_t l2c_crip:3;
2055 uint64_t use_int_refclk:1;
2056 uint64_t zip_info:2;
2057 uint64_t bar2_sz_conf:1;
2058 uint64_t efus_lck:1;
2059 uint64_t efus_ign:1;
2061 uint64_t nodfa_dte:1;
2063 uint64_t reserved_9_17:9;
2064 uint64_t core_pll_mul:5;
2065 uint64_t pnr_pll_mul:4;
2067 uint64_t pnr_pll_mul:4;
2068 uint64_t core_pll_mul:5;
2069 uint64_t reserved_9_17:9;
2071 uint64_t nodfa_dte:1;
2073 uint64_t efus_ign:1;
2074 uint64_t efus_lck:1;
2075 uint64_t bar2_sz_conf:1;
2076 uint64_t zip_info:2;
2077 uint64_t use_int_refclk:1;
2078 uint64_t l2c_crip:3;
2079 uint64_t pll_half_dis:1;
2080 uint64_t efus_lck_man:1;
2081 uint64_t efus_lck_rsv:1;
2082 uint64_t pll_bwadj_denom:2;
2083 uint64_t pll_alt_matrix:1;
2084 uint64_t dfa_info_clm:4;
2085 uint64_t dfa_info_dte:3;
2086 uint64_t pll_ctl:10;
2092 union cvmx_mio_fus_ema {
2094 struct cvmx_mio_fus_ema_s {
2095 #ifdef __BIG_ENDIAN_BITFIELD
2096 uint64_t reserved_7_63:57;
2098 uint64_t reserved_3_3:1;
2102 uint64_t reserved_3_3:1;
2104 uint64_t reserved_7_63:57;
2107 struct cvmx_mio_fus_ema_cn58xx {
2108 #ifdef __BIG_ENDIAN_BITFIELD
2109 uint64_t reserved_2_63:62;
2113 uint64_t reserved_2_63:62;
2118 union cvmx_mio_fus_pdf {
2120 struct cvmx_mio_fus_pdf_s {
2121 #ifdef __BIG_ENDIAN_BITFIELD
2129 union cvmx_mio_fus_pll {
2131 struct cvmx_mio_fus_pll_s {
2132 #ifdef __BIG_ENDIAN_BITFIELD
2133 uint64_t reserved_48_63:16;
2134 uint64_t rclk_align_r:8;
2135 uint64_t rclk_align_l:8;
2136 uint64_t reserved_8_31:24;
2137 uint64_t c_cout_rst:1;
2138 uint64_t c_cout_sel:2;
2139 uint64_t pnr_cout_rst:1;
2140 uint64_t pnr_cout_sel:2;
2146 uint64_t pnr_cout_sel:2;
2147 uint64_t pnr_cout_rst:1;
2148 uint64_t c_cout_sel:2;
2149 uint64_t c_cout_rst:1;
2150 uint64_t reserved_8_31:24;
2151 uint64_t rclk_align_l:8;
2152 uint64_t rclk_align_r:8;
2153 uint64_t reserved_48_63:16;
2156 struct cvmx_mio_fus_pll_cn50xx {
2157 #ifdef __BIG_ENDIAN_BITFIELD
2158 uint64_t reserved_2_63:62;
2164 uint64_t reserved_2_63:62;
2167 struct cvmx_mio_fus_pll_cn61xx {
2168 #ifdef __BIG_ENDIAN_BITFIELD
2169 uint64_t reserved_8_63:56;
2170 uint64_t c_cout_rst:1;
2171 uint64_t c_cout_sel:2;
2172 uint64_t pnr_cout_rst:1;
2173 uint64_t pnr_cout_sel:2;
2179 uint64_t pnr_cout_sel:2;
2180 uint64_t pnr_cout_rst:1;
2181 uint64_t c_cout_sel:2;
2182 uint64_t c_cout_rst:1;
2183 uint64_t reserved_8_63:56;
2188 union cvmx_mio_fus_prog {
2190 struct cvmx_mio_fus_prog_s {
2191 #ifdef __BIG_ENDIAN_BITFIELD
2192 uint64_t reserved_2_63:62;
2198 uint64_t reserved_2_63:62;
2201 struct cvmx_mio_fus_prog_cn30xx {
2202 #ifdef __BIG_ENDIAN_BITFIELD
2203 uint64_t reserved_1_63:63;
2207 uint64_t reserved_1_63:63;
2212 union cvmx_mio_fus_prog_times {
2214 struct cvmx_mio_fus_prog_times_s {
2215 #ifdef __BIG_ENDIAN_BITFIELD
2216 uint64_t reserved_35_63:29;
2217 uint64_t vgate_pin:1;
2218 uint64_t fsrc_pin:1;
2219 uint64_t prog_pin:1;
2220 uint64_t reserved_6_31:26;
2224 uint64_t reserved_6_31:26;
2225 uint64_t prog_pin:1;
2226 uint64_t fsrc_pin:1;
2227 uint64_t vgate_pin:1;
2228 uint64_t reserved_35_63:29;
2231 struct cvmx_mio_fus_prog_times_cn50xx {
2232 #ifdef __BIG_ENDIAN_BITFIELD
2233 uint64_t reserved_33_63:31;
2234 uint64_t prog_pin:1;
2237 uint64_t sclk_hi:12;
2241 uint64_t sclk_hi:12;
2244 uint64_t prog_pin:1;
2245 uint64_t reserved_33_63:31;
2248 struct cvmx_mio_fus_prog_times_cn61xx {
2249 #ifdef __BIG_ENDIAN_BITFIELD
2250 uint64_t reserved_35_63:29;
2251 uint64_t vgate_pin:1;
2252 uint64_t fsrc_pin:1;
2253 uint64_t prog_pin:1;
2256 uint64_t sclk_hi:15;
2260 uint64_t sclk_hi:15;
2263 uint64_t prog_pin:1;
2264 uint64_t fsrc_pin:1;
2265 uint64_t vgate_pin:1;
2266 uint64_t reserved_35_63:29;
2271 union cvmx_mio_fus_rcmd {
2273 struct cvmx_mio_fus_rcmd_s {
2274 #ifdef __BIG_ENDIAN_BITFIELD
2275 uint64_t reserved_24_63:40;
2277 uint64_t reserved_13_15:3;
2279 uint64_t reserved_9_11:3;
2285 uint64_t reserved_9_11:3;
2287 uint64_t reserved_13_15:3;
2289 uint64_t reserved_24_63:40;
2292 struct cvmx_mio_fus_rcmd_cn30xx {
2293 #ifdef __BIG_ENDIAN_BITFIELD
2294 uint64_t reserved_24_63:40;
2296 uint64_t reserved_13_15:3;
2298 uint64_t reserved_9_11:3;
2300 uint64_t reserved_7_7:1;
2304 uint64_t reserved_7_7:1;
2306 uint64_t reserved_9_11:3;
2308 uint64_t reserved_13_15:3;
2310 uint64_t reserved_24_63:40;
2315 union cvmx_mio_fus_read_times {
2317 struct cvmx_mio_fus_read_times_s {
2318 #ifdef __BIG_ENDIAN_BITFIELD
2319 uint64_t reserved_26_63:38;
2331 uint64_t reserved_26_63:38;
2336 union cvmx_mio_fus_repair_res0 {
2338 struct cvmx_mio_fus_repair_res0_s {
2339 #ifdef __BIG_ENDIAN_BITFIELD
2340 uint64_t reserved_55_63:9;
2341 uint64_t too_many:1;
2342 uint64_t repair2:18;
2343 uint64_t repair1:18;
2344 uint64_t repair0:18;
2346 uint64_t repair0:18;
2347 uint64_t repair1:18;
2348 uint64_t repair2:18;
2349 uint64_t too_many:1;
2350 uint64_t reserved_55_63:9;
2355 union cvmx_mio_fus_repair_res1 {
2357 struct cvmx_mio_fus_repair_res1_s {
2358 #ifdef __BIG_ENDIAN_BITFIELD
2359 uint64_t reserved_54_63:10;
2360 uint64_t repair5:18;
2361 uint64_t repair4:18;
2362 uint64_t repair3:18;
2364 uint64_t repair3:18;
2365 uint64_t repair4:18;
2366 uint64_t repair5:18;
2367 uint64_t reserved_54_63:10;
2372 union cvmx_mio_fus_repair_res2 {
2374 struct cvmx_mio_fus_repair_res2_s {
2375 #ifdef __BIG_ENDIAN_BITFIELD
2376 uint64_t reserved_18_63:46;
2377 uint64_t repair6:18;
2379 uint64_t repair6:18;
2380 uint64_t reserved_18_63:46;
2385 union cvmx_mio_fus_spr_repair_res {
2387 struct cvmx_mio_fus_spr_repair_res_s {
2388 #ifdef __BIG_ENDIAN_BITFIELD
2389 uint64_t reserved_42_63:22;
2390 uint64_t repair2:14;
2391 uint64_t repair1:14;
2392 uint64_t repair0:14;
2394 uint64_t repair0:14;
2395 uint64_t repair1:14;
2396 uint64_t repair2:14;
2397 uint64_t reserved_42_63:22;
2402 union cvmx_mio_fus_spr_repair_sum {
2404 struct cvmx_mio_fus_spr_repair_sum_s {
2405 #ifdef __BIG_ENDIAN_BITFIELD
2406 uint64_t reserved_1_63:63;
2407 uint64_t too_many:1;
2409 uint64_t too_many:1;
2410 uint64_t reserved_1_63:63;
2415 union cvmx_mio_fus_tgg {
2417 struct cvmx_mio_fus_tgg_s {
2418 #ifdef __BIG_ENDIAN_BITFIELD
2428 union cvmx_mio_fus_unlock {
2430 struct cvmx_mio_fus_unlock_s {
2431 #ifdef __BIG_ENDIAN_BITFIELD
2432 uint64_t reserved_24_63:40;
2436 uint64_t reserved_24_63:40;
2441 union cvmx_mio_fus_wadr {
2443 struct cvmx_mio_fus_wadr_s {
2444 #ifdef __BIG_ENDIAN_BITFIELD
2445 uint64_t reserved_10_63:54;
2449 uint64_t reserved_10_63:54;
2452 struct cvmx_mio_fus_wadr_cn50xx {
2453 #ifdef __BIG_ENDIAN_BITFIELD
2454 uint64_t reserved_2_63:62;
2458 uint64_t reserved_2_63:62;
2461 struct cvmx_mio_fus_wadr_cn52xx {
2462 #ifdef __BIG_ENDIAN_BITFIELD
2463 uint64_t reserved_3_63:61;
2467 uint64_t reserved_3_63:61;
2470 struct cvmx_mio_fus_wadr_cn61xx {
2471 #ifdef __BIG_ENDIAN_BITFIELD
2472 uint64_t reserved_4_63:60;
2476 uint64_t reserved_4_63:60;
2481 union cvmx_mio_gpio_comp {
2483 struct cvmx_mio_gpio_comp_s {
2484 #ifdef __BIG_ENDIAN_BITFIELD
2485 uint64_t reserved_12_63:52;
2491 uint64_t reserved_12_63:52;
2496 union cvmx_mio_ndf_dma_cfg {
2498 struct cvmx_mio_ndf_dma_cfg_s {
2499 #ifdef __BIG_ENDIAN_BITFIELD
2503 uint64_t reserved_60_60:1;
2517 uint64_t reserved_60_60:1;
2525 union cvmx_mio_ndf_dma_int {
2527 struct cvmx_mio_ndf_dma_int_s {
2528 #ifdef __BIG_ENDIAN_BITFIELD
2529 uint64_t reserved_1_63:63;
2533 uint64_t reserved_1_63:63;
2538 union cvmx_mio_ndf_dma_int_en {
2540 struct cvmx_mio_ndf_dma_int_en_s {
2541 #ifdef __BIG_ENDIAN_BITFIELD
2542 uint64_t reserved_1_63:63;
2546 uint64_t reserved_1_63:63;
2551 union cvmx_mio_pll_ctl {
2553 struct cvmx_mio_pll_ctl_s {
2554 #ifdef __BIG_ENDIAN_BITFIELD
2555 uint64_t reserved_5_63:59;
2559 uint64_t reserved_5_63:59;
2564 union cvmx_mio_pll_setting {
2566 struct cvmx_mio_pll_setting_s {
2567 #ifdef __BIG_ENDIAN_BITFIELD
2568 uint64_t reserved_17_63:47;
2569 uint64_t setting:17;
2571 uint64_t setting:17;
2572 uint64_t reserved_17_63:47;
2577 union cvmx_mio_ptp_ckout_hi_incr {
2579 struct cvmx_mio_ptp_ckout_hi_incr_s {
2580 #ifdef __BIG_ENDIAN_BITFIELD
2581 uint64_t nanosec:32;
2582 uint64_t frnanosec:32;
2584 uint64_t frnanosec:32;
2585 uint64_t nanosec:32;
2590 union cvmx_mio_ptp_ckout_lo_incr {
2592 struct cvmx_mio_ptp_ckout_lo_incr_s {
2593 #ifdef __BIG_ENDIAN_BITFIELD
2594 uint64_t nanosec:32;
2595 uint64_t frnanosec:32;
2597 uint64_t frnanosec:32;
2598 uint64_t nanosec:32;
2603 union cvmx_mio_ptp_ckout_thresh_hi {
2605 struct cvmx_mio_ptp_ckout_thresh_hi_s {
2606 #ifdef __BIG_ENDIAN_BITFIELD
2607 uint64_t nanosec:64;
2609 uint64_t nanosec:64;
2614 union cvmx_mio_ptp_ckout_thresh_lo {
2616 struct cvmx_mio_ptp_ckout_thresh_lo_s {
2617 #ifdef __BIG_ENDIAN_BITFIELD
2618 uint64_t reserved_32_63:32;
2619 uint64_t frnanosec:32;
2621 uint64_t frnanosec:32;
2622 uint64_t reserved_32_63:32;
2627 union cvmx_mio_ptp_clock_cfg {
2629 struct cvmx_mio_ptp_clock_cfg_s {
2630 #ifdef __BIG_ENDIAN_BITFIELD
2631 uint64_t reserved_42_63:22;
2634 uint64_t ext_clk_edge:2;
2635 uint64_t ckout_out4:1;
2639 uint64_t ckout_out:4;
2640 uint64_t ckout_inv:1;
2641 uint64_t ckout_en:1;
2642 uint64_t evcnt_in:6;
2643 uint64_t evcnt_edge:1;
2644 uint64_t evcnt_en:1;
2645 uint64_t tstmp_in:6;
2646 uint64_t tstmp_edge:1;
2647 uint64_t tstmp_en:1;
2648 uint64_t ext_clk_in:6;
2649 uint64_t ext_clk_en:1;
2653 uint64_t ext_clk_en:1;
2654 uint64_t ext_clk_in:6;
2655 uint64_t tstmp_en:1;
2656 uint64_t tstmp_edge:1;
2657 uint64_t tstmp_in:6;
2658 uint64_t evcnt_en:1;
2659 uint64_t evcnt_edge:1;
2660 uint64_t evcnt_in:6;
2661 uint64_t ckout_en:1;
2662 uint64_t ckout_inv:1;
2663 uint64_t ckout_out:4;
2667 uint64_t ckout_out4:1;
2668 uint64_t ext_clk_edge:2;
2671 uint64_t reserved_42_63:22;
2674 struct cvmx_mio_ptp_clock_cfg_cn63xx {
2675 #ifdef __BIG_ENDIAN_BITFIELD
2676 uint64_t reserved_24_63:40;
2677 uint64_t evcnt_in:6;
2678 uint64_t evcnt_edge:1;
2679 uint64_t evcnt_en:1;
2680 uint64_t tstmp_in:6;
2681 uint64_t tstmp_edge:1;
2682 uint64_t tstmp_en:1;
2683 uint64_t ext_clk_in:6;
2684 uint64_t ext_clk_en:1;
2688 uint64_t ext_clk_en:1;
2689 uint64_t ext_clk_in:6;
2690 uint64_t tstmp_en:1;
2691 uint64_t tstmp_edge:1;
2692 uint64_t tstmp_in:6;
2693 uint64_t evcnt_en:1;
2694 uint64_t evcnt_edge:1;
2695 uint64_t evcnt_in:6;
2696 uint64_t reserved_24_63:40;
2699 struct cvmx_mio_ptp_clock_cfg_cn66xx {
2700 #ifdef __BIG_ENDIAN_BITFIELD
2701 uint64_t reserved_40_63:24;
2702 uint64_t ext_clk_edge:2;
2703 uint64_t ckout_out4:1;
2707 uint64_t ckout_out:4;
2708 uint64_t ckout_inv:1;
2709 uint64_t ckout_en:1;
2710 uint64_t evcnt_in:6;
2711 uint64_t evcnt_edge:1;
2712 uint64_t evcnt_en:1;
2713 uint64_t tstmp_in:6;
2714 uint64_t tstmp_edge:1;
2715 uint64_t tstmp_en:1;
2716 uint64_t ext_clk_in:6;
2717 uint64_t ext_clk_en:1;
2721 uint64_t ext_clk_en:1;
2722 uint64_t ext_clk_in:6;
2723 uint64_t tstmp_en:1;
2724 uint64_t tstmp_edge:1;
2725 uint64_t tstmp_in:6;
2726 uint64_t evcnt_en:1;
2727 uint64_t evcnt_edge:1;
2728 uint64_t evcnt_in:6;
2729 uint64_t ckout_en:1;
2730 uint64_t ckout_inv:1;
2731 uint64_t ckout_out:4;
2735 uint64_t ckout_out4:1;
2736 uint64_t ext_clk_edge:2;
2737 uint64_t reserved_40_63:24;
2742 union cvmx_mio_ptp_clock_comp {
2744 struct cvmx_mio_ptp_clock_comp_s {
2745 #ifdef __BIG_ENDIAN_BITFIELD
2746 uint64_t nanosec:32;
2747 uint64_t frnanosec:32;
2749 uint64_t frnanosec:32;
2750 uint64_t nanosec:32;
2755 union cvmx_mio_ptp_clock_hi {
2757 struct cvmx_mio_ptp_clock_hi_s {
2758 #ifdef __BIG_ENDIAN_BITFIELD
2759 uint64_t nanosec:64;
2761 uint64_t nanosec:64;
2766 union cvmx_mio_ptp_clock_lo {
2768 struct cvmx_mio_ptp_clock_lo_s {
2769 #ifdef __BIG_ENDIAN_BITFIELD
2770 uint64_t reserved_32_63:32;
2771 uint64_t frnanosec:32;
2773 uint64_t frnanosec:32;
2774 uint64_t reserved_32_63:32;
2779 union cvmx_mio_ptp_evt_cnt {
2781 struct cvmx_mio_ptp_evt_cnt_s {
2782 #ifdef __BIG_ENDIAN_BITFIELD
2790 union cvmx_mio_ptp_phy_1pps_in {
2792 struct cvmx_mio_ptp_phy_1pps_in_s {
2793 #ifdef __BIG_ENDIAN_BITFIELD
2794 uint64_t reserved_5_63:59;
2798 uint64_t reserved_5_63:59;
2803 union cvmx_mio_ptp_pps_hi_incr {
2805 struct cvmx_mio_ptp_pps_hi_incr_s {
2806 #ifdef __BIG_ENDIAN_BITFIELD
2807 uint64_t nanosec:32;
2808 uint64_t frnanosec:32;
2810 uint64_t frnanosec:32;
2811 uint64_t nanosec:32;
2816 union cvmx_mio_ptp_pps_lo_incr {
2818 struct cvmx_mio_ptp_pps_lo_incr_s {
2819 #ifdef __BIG_ENDIAN_BITFIELD
2820 uint64_t nanosec:32;
2821 uint64_t frnanosec:32;
2823 uint64_t frnanosec:32;
2824 uint64_t nanosec:32;
2829 union cvmx_mio_ptp_pps_thresh_hi {
2831 struct cvmx_mio_ptp_pps_thresh_hi_s {
2832 #ifdef __BIG_ENDIAN_BITFIELD
2833 uint64_t nanosec:64;
2835 uint64_t nanosec:64;
2840 union cvmx_mio_ptp_pps_thresh_lo {
2842 struct cvmx_mio_ptp_pps_thresh_lo_s {
2843 #ifdef __BIG_ENDIAN_BITFIELD
2844 uint64_t reserved_32_63:32;
2845 uint64_t frnanosec:32;
2847 uint64_t frnanosec:32;
2848 uint64_t reserved_32_63:32;
2853 union cvmx_mio_ptp_timestamp {
2855 struct cvmx_mio_ptp_timestamp_s {
2856 #ifdef __BIG_ENDIAN_BITFIELD
2857 uint64_t nanosec:64;
2859 uint64_t nanosec:64;
2864 union cvmx_mio_qlmx_cfg {
2866 struct cvmx_mio_qlmx_cfg_s {
2867 #ifdef __BIG_ENDIAN_BITFIELD
2868 uint64_t reserved_15_63:49;
2870 uint64_t reserved_12_13:2;
2872 uint64_t reserved_4_7:4;
2876 uint64_t reserved_4_7:4;
2878 uint64_t reserved_12_13:2;
2880 uint64_t reserved_15_63:49;
2883 struct cvmx_mio_qlmx_cfg_cn61xx {
2884 #ifdef __BIG_ENDIAN_BITFIELD
2885 uint64_t reserved_15_63:49;
2887 uint64_t reserved_12_13:2;
2889 uint64_t reserved_2_7:6;
2893 uint64_t reserved_2_7:6;
2895 uint64_t reserved_12_13:2;
2897 uint64_t reserved_15_63:49;
2900 struct cvmx_mio_qlmx_cfg_cn66xx {
2901 #ifdef __BIG_ENDIAN_BITFIELD
2902 uint64_t reserved_12_63:52;
2904 uint64_t reserved_4_7:4;
2908 uint64_t reserved_4_7:4;
2910 uint64_t reserved_12_63:52;
2913 struct cvmx_mio_qlmx_cfg_cn68xx {
2914 #ifdef __BIG_ENDIAN_BITFIELD
2915 uint64_t reserved_12_63:52;
2917 uint64_t reserved_3_7:5;
2921 uint64_t reserved_3_7:5;
2923 uint64_t reserved_12_63:52;
2928 union cvmx_mio_rst_boot {
2930 struct cvmx_mio_rst_boot_s {
2931 #ifdef __BIG_ENDIAN_BITFIELD
2932 uint64_t chipkill:1;
2933 uint64_t jtcsrdis:1;
2934 uint64_t ejtagdis:1;
2936 uint64_t ckill_ppdis:1;
2937 uint64_t jt_tstmode:1;
2938 uint64_t reserved_50_57:8;
2939 uint64_t lboot_ext:2;
2940 uint64_t reserved_44_47:4;
2941 uint64_t qlm4_spd:4;
2942 uint64_t qlm3_spd:4;
2945 uint64_t qlm2_spd:4;
2946 uint64_t qlm1_spd:4;
2947 uint64_t qlm0_spd:4;
2950 uint64_t rboot_pin:1;
2952 uint64_t rboot_pin:1;
2955 uint64_t qlm0_spd:4;
2956 uint64_t qlm1_spd:4;
2957 uint64_t qlm2_spd:4;
2960 uint64_t qlm3_spd:4;
2961 uint64_t qlm4_spd:4;
2962 uint64_t reserved_44_47:4;
2963 uint64_t lboot_ext:2;
2964 uint64_t reserved_50_57:8;
2965 uint64_t jt_tstmode:1;
2966 uint64_t ckill_ppdis:1;
2968 uint64_t ejtagdis:1;
2969 uint64_t jtcsrdis:1;
2970 uint64_t chipkill:1;
2973 struct cvmx_mio_rst_boot_cn61xx {
2974 #ifdef __BIG_ENDIAN_BITFIELD
2975 uint64_t chipkill:1;
2976 uint64_t jtcsrdis:1;
2977 uint64_t ejtagdis:1;
2979 uint64_t ckill_ppdis:1;
2980 uint64_t jt_tstmode:1;
2981 uint64_t reserved_50_57:8;
2982 uint64_t lboot_ext:2;
2983 uint64_t reserved_36_47:12;
2986 uint64_t qlm2_spd:4;
2987 uint64_t qlm1_spd:4;
2988 uint64_t qlm0_spd:4;
2991 uint64_t rboot_pin:1;
2993 uint64_t rboot_pin:1;
2996 uint64_t qlm0_spd:4;
2997 uint64_t qlm1_spd:4;
2998 uint64_t qlm2_spd:4;
3001 uint64_t reserved_36_47:12;
3002 uint64_t lboot_ext:2;
3003 uint64_t reserved_50_57:8;
3004 uint64_t jt_tstmode:1;
3005 uint64_t ckill_ppdis:1;
3007 uint64_t ejtagdis:1;
3008 uint64_t jtcsrdis:1;
3009 uint64_t chipkill:1;
3012 struct cvmx_mio_rst_boot_cn63xx {
3013 #ifdef __BIG_ENDIAN_BITFIELD
3014 uint64_t reserved_36_63:28;
3017 uint64_t qlm2_spd:4;
3018 uint64_t qlm1_spd:4;
3019 uint64_t qlm0_spd:4;
3022 uint64_t rboot_pin:1;
3024 uint64_t rboot_pin:1;
3027 uint64_t qlm0_spd:4;
3028 uint64_t qlm1_spd:4;
3029 uint64_t qlm2_spd:4;
3032 uint64_t reserved_36_63:28;
3035 struct cvmx_mio_rst_boot_cn66xx {
3036 #ifdef __BIG_ENDIAN_BITFIELD
3037 uint64_t chipkill:1;
3038 uint64_t jtcsrdis:1;
3039 uint64_t ejtagdis:1;
3041 uint64_t ckill_ppdis:1;
3042 uint64_t reserved_50_58:9;
3043 uint64_t lboot_ext:2;
3044 uint64_t reserved_36_47:12;
3047 uint64_t qlm2_spd:4;
3048 uint64_t qlm1_spd:4;
3049 uint64_t qlm0_spd:4;
3052 uint64_t rboot_pin:1;
3054 uint64_t rboot_pin:1;
3057 uint64_t qlm0_spd:4;
3058 uint64_t qlm1_spd:4;
3059 uint64_t qlm2_spd:4;
3062 uint64_t reserved_36_47:12;
3063 uint64_t lboot_ext:2;
3064 uint64_t reserved_50_58:9;
3065 uint64_t ckill_ppdis:1;
3067 uint64_t ejtagdis:1;
3068 uint64_t jtcsrdis:1;
3069 uint64_t chipkill:1;
3072 struct cvmx_mio_rst_boot_cn68xx {
3073 #ifdef __BIG_ENDIAN_BITFIELD
3074 uint64_t reserved_59_63:5;
3075 uint64_t jt_tstmode:1;
3076 uint64_t reserved_44_57:14;
3077 uint64_t qlm4_spd:4;
3078 uint64_t qlm3_spd:4;
3081 uint64_t qlm2_spd:4;
3082 uint64_t qlm1_spd:4;
3083 uint64_t qlm0_spd:4;
3086 uint64_t rboot_pin:1;
3088 uint64_t rboot_pin:1;
3091 uint64_t qlm0_spd:4;
3092 uint64_t qlm1_spd:4;
3093 uint64_t qlm2_spd:4;
3096 uint64_t qlm3_spd:4;
3097 uint64_t qlm4_spd:4;
3098 uint64_t reserved_44_57:14;
3099 uint64_t jt_tstmode:1;
3100 uint64_t reserved_59_63:5;
3103 struct cvmx_mio_rst_boot_cn68xxp1 {
3104 #ifdef __BIG_ENDIAN_BITFIELD
3105 uint64_t reserved_44_63:20;
3106 uint64_t qlm4_spd:4;
3107 uint64_t qlm3_spd:4;
3110 uint64_t qlm2_spd:4;
3111 uint64_t qlm1_spd:4;
3112 uint64_t qlm0_spd:4;
3115 uint64_t rboot_pin:1;
3117 uint64_t rboot_pin:1;
3120 uint64_t qlm0_spd:4;
3121 uint64_t qlm1_spd:4;
3122 uint64_t qlm2_spd:4;
3125 uint64_t qlm3_spd:4;
3126 uint64_t qlm4_spd:4;
3127 uint64_t reserved_44_63:20;
3132 union cvmx_mio_rst_cfg {
3134 struct cvmx_mio_rst_cfg_s {
3135 #ifdef __BIG_ENDIAN_BITFIELD
3136 uint64_t reserved_3_63:61;
3137 uint64_t cntl_clr_bist:1;
3138 uint64_t warm_clr_bist:1;
3139 uint64_t soft_clr_bist:1;
3141 uint64_t soft_clr_bist:1;
3142 uint64_t warm_clr_bist:1;
3143 uint64_t cntl_clr_bist:1;
3144 uint64_t reserved_3_63:61;
3147 struct cvmx_mio_rst_cfg_cn61xx {
3148 #ifdef __BIG_ENDIAN_BITFIELD
3149 uint64_t bist_delay:58;
3150 uint64_t reserved_3_5:3;
3151 uint64_t cntl_clr_bist:1;
3152 uint64_t warm_clr_bist:1;
3153 uint64_t soft_clr_bist:1;
3155 uint64_t soft_clr_bist:1;
3156 uint64_t warm_clr_bist:1;
3157 uint64_t cntl_clr_bist:1;
3158 uint64_t reserved_3_5:3;
3159 uint64_t bist_delay:58;
3162 struct cvmx_mio_rst_cfg_cn63xxp1 {
3163 #ifdef __BIG_ENDIAN_BITFIELD
3164 uint64_t bist_delay:58;
3165 uint64_t reserved_2_5:4;
3166 uint64_t warm_clr_bist:1;
3167 uint64_t soft_clr_bist:1;
3169 uint64_t soft_clr_bist:1;
3170 uint64_t warm_clr_bist:1;
3171 uint64_t reserved_2_5:4;
3172 uint64_t bist_delay:58;
3175 struct cvmx_mio_rst_cfg_cn68xx {
3176 #ifdef __BIG_ENDIAN_BITFIELD
3177 uint64_t bist_delay:56;
3178 uint64_t reserved_3_7:5;
3179 uint64_t cntl_clr_bist:1;
3180 uint64_t warm_clr_bist:1;
3181 uint64_t soft_clr_bist:1;
3183 uint64_t soft_clr_bist:1;
3184 uint64_t warm_clr_bist:1;
3185 uint64_t cntl_clr_bist:1;
3186 uint64_t reserved_3_7:5;
3187 uint64_t bist_delay:56;
3192 union cvmx_mio_rst_ckill {
3194 struct cvmx_mio_rst_ckill_s {
3195 #ifdef __BIG_ENDIAN_BITFIELD
3196 uint64_t reserved_47_63:17;
3200 uint64_t reserved_47_63:17;
3205 union cvmx_mio_rst_cntlx {
3207 struct cvmx_mio_rst_cntlx_s {
3208 #ifdef __BIG_ENDIAN_BITFIELD
3209 uint64_t reserved_13_63:51;
3210 uint64_t in_rev_ln:1;
3211 uint64_t rev_lanes:1;
3212 uint64_t gen1_only:1;
3213 uint64_t prst_link:1;
3214 uint64_t rst_done:1;
3215 uint64_t rst_link:1;
3216 uint64_t host_mode:1;
3220 uint64_t rst_chip:1;
3224 uint64_t rst_chip:1;
3228 uint64_t host_mode:1;
3229 uint64_t rst_link:1;
3230 uint64_t rst_done:1;
3231 uint64_t prst_link:1;
3232 uint64_t gen1_only:1;
3233 uint64_t rev_lanes:1;
3234 uint64_t in_rev_ln:1;
3235 uint64_t reserved_13_63:51;
3238 struct cvmx_mio_rst_cntlx_cn66xx {
3239 #ifdef __BIG_ENDIAN_BITFIELD
3240 uint64_t reserved_10_63:54;
3241 uint64_t prst_link:1;
3242 uint64_t rst_done:1;
3243 uint64_t rst_link:1;
3244 uint64_t host_mode:1;
3248 uint64_t rst_chip:1;
3252 uint64_t rst_chip:1;
3256 uint64_t host_mode:1;
3257 uint64_t rst_link:1;
3258 uint64_t rst_done:1;
3259 uint64_t prst_link:1;
3260 uint64_t reserved_10_63:54;
3265 union cvmx_mio_rst_ctlx {
3267 struct cvmx_mio_rst_ctlx_s {
3268 #ifdef __BIG_ENDIAN_BITFIELD
3269 uint64_t reserved_13_63:51;
3270 uint64_t in_rev_ln:1;
3271 uint64_t rev_lanes:1;
3272 uint64_t gen1_only:1;
3273 uint64_t prst_link:1;
3274 uint64_t rst_done:1;
3275 uint64_t rst_link:1;
3276 uint64_t host_mode:1;
3280 uint64_t rst_chip:1;
3284 uint64_t rst_chip:1;
3288 uint64_t host_mode:1;
3289 uint64_t rst_link:1;
3290 uint64_t rst_done:1;
3291 uint64_t prst_link:1;
3292 uint64_t gen1_only:1;
3293 uint64_t rev_lanes:1;
3294 uint64_t in_rev_ln:1;
3295 uint64_t reserved_13_63:51;
3298 struct cvmx_mio_rst_ctlx_cn63xx {
3299 #ifdef __BIG_ENDIAN_BITFIELD
3300 uint64_t reserved_10_63:54;
3301 uint64_t prst_link:1;
3302 uint64_t rst_done:1;
3303 uint64_t rst_link:1;
3304 uint64_t host_mode:1;
3308 uint64_t rst_chip:1;
3312 uint64_t rst_chip:1;
3316 uint64_t host_mode:1;
3317 uint64_t rst_link:1;
3318 uint64_t rst_done:1;
3319 uint64_t prst_link:1;
3320 uint64_t reserved_10_63:54;
3323 struct cvmx_mio_rst_ctlx_cn63xxp1 {
3324 #ifdef __BIG_ENDIAN_BITFIELD
3325 uint64_t reserved_9_63:55;
3326 uint64_t rst_done:1;
3327 uint64_t rst_link:1;
3328 uint64_t host_mode:1;
3332 uint64_t rst_chip:1;
3336 uint64_t rst_chip:1;
3340 uint64_t host_mode:1;
3341 uint64_t rst_link:1;
3342 uint64_t rst_done:1;
3343 uint64_t reserved_9_63:55;
3348 union cvmx_mio_rst_delay {
3350 struct cvmx_mio_rst_delay_s {
3351 #ifdef __BIG_ENDIAN_BITFIELD
3352 uint64_t reserved_32_63:32;
3353 uint64_t warm_rst_dly:16;
3354 uint64_t soft_rst_dly:16;
3356 uint64_t soft_rst_dly:16;
3357 uint64_t warm_rst_dly:16;
3358 uint64_t reserved_32_63:32;
3363 union cvmx_mio_rst_int {
3365 struct cvmx_mio_rst_int_s {
3366 #ifdef __BIG_ENDIAN_BITFIELD
3367 uint64_t reserved_10_63:54;
3370 uint64_t reserved_4_7:4;
3371 uint64_t rst_link3:1;
3372 uint64_t rst_link2:1;
3373 uint64_t rst_link1:1;
3374 uint64_t rst_link0:1;
3376 uint64_t rst_link0:1;
3377 uint64_t rst_link1:1;
3378 uint64_t rst_link2:1;
3379 uint64_t rst_link3:1;
3380 uint64_t reserved_4_7:4;
3383 uint64_t reserved_10_63:54;
3386 struct cvmx_mio_rst_int_cn61xx {
3387 #ifdef __BIG_ENDIAN_BITFIELD
3388 uint64_t reserved_10_63:54;
3391 uint64_t reserved_2_7:6;
3392 uint64_t rst_link1:1;
3393 uint64_t rst_link0:1;
3395 uint64_t rst_link0:1;
3396 uint64_t rst_link1:1;
3397 uint64_t reserved_2_7:6;
3400 uint64_t reserved_10_63:54;
3405 union cvmx_mio_rst_int_en {
3407 struct cvmx_mio_rst_int_en_s {
3408 #ifdef __BIG_ENDIAN_BITFIELD
3409 uint64_t reserved_10_63:54;
3412 uint64_t reserved_4_7:4;
3413 uint64_t rst_link3:1;
3414 uint64_t rst_link2:1;
3415 uint64_t rst_link1:1;
3416 uint64_t rst_link0:1;
3418 uint64_t rst_link0:1;
3419 uint64_t rst_link1:1;
3420 uint64_t rst_link2:1;
3421 uint64_t rst_link3:1;
3422 uint64_t reserved_4_7:4;
3425 uint64_t reserved_10_63:54;
3428 struct cvmx_mio_rst_int_en_cn61xx {
3429 #ifdef __BIG_ENDIAN_BITFIELD
3430 uint64_t reserved_10_63:54;
3433 uint64_t reserved_2_7:6;
3434 uint64_t rst_link1:1;
3435 uint64_t rst_link0:1;
3437 uint64_t rst_link0:1;
3438 uint64_t rst_link1:1;
3439 uint64_t reserved_2_7:6;
3442 uint64_t reserved_10_63:54;
3447 union cvmx_mio_twsx_int {
3449 struct cvmx_mio_twsx_int_s {
3450 #ifdef __BIG_ENDIAN_BITFIELD
3451 uint64_t reserved_12_63:52;
3456 uint64_t reserved_7_7:1;
3460 uint64_t reserved_3_3:1;
3461 uint64_t core_int:1;
3467 uint64_t core_int:1;
3468 uint64_t reserved_3_3:1;
3472 uint64_t reserved_7_7:1;
3477 uint64_t reserved_12_63:52;
3480 struct cvmx_mio_twsx_int_cn38xxp2 {
3481 #ifdef __BIG_ENDIAN_BITFIELD
3482 uint64_t reserved_7_63:57;
3486 uint64_t reserved_3_3:1;
3487 uint64_t core_int:1;
3493 uint64_t core_int:1;
3494 uint64_t reserved_3_3:1;
3498 uint64_t reserved_7_63:57;
3503 union cvmx_mio_twsx_sw_twsi {
3505 struct cvmx_mio_twsx_sw_twsi_s {
3506 #ifdef __BIG_ENDIAN_BITFIELD
3536 union cvmx_mio_twsx_sw_twsi_ext {
3538 struct cvmx_mio_twsx_sw_twsi_ext_s {
3539 #ifdef __BIG_ENDIAN_BITFIELD
3540 uint64_t reserved_40_63:24;
3546 uint64_t reserved_40_63:24;
3551 union cvmx_mio_twsx_twsi_sw {
3553 struct cvmx_mio_twsx_twsi_sw_s {
3554 #ifdef __BIG_ENDIAN_BITFIELD
3556 uint64_t reserved_32_61:30;
3560 uint64_t reserved_32_61:30;
3566 union cvmx_mio_uartx_dlh {
3568 struct cvmx_mio_uartx_dlh_s {
3569 #ifdef __BIG_ENDIAN_BITFIELD
3570 uint64_t reserved_8_63:56;
3574 uint64_t reserved_8_63:56;
3579 union cvmx_mio_uartx_dll {
3581 struct cvmx_mio_uartx_dll_s {
3582 #ifdef __BIG_ENDIAN_BITFIELD
3583 uint64_t reserved_8_63:56;
3587 uint64_t reserved_8_63:56;
3592 union cvmx_mio_uartx_far {
3594 struct cvmx_mio_uartx_far_s {
3595 #ifdef __BIG_ENDIAN_BITFIELD
3596 uint64_t reserved_1_63:63;
3600 uint64_t reserved_1_63:63;
3605 union cvmx_mio_uartx_fcr {
3607 struct cvmx_mio_uartx_fcr_s {
3608 #ifdef __BIG_ENDIAN_BITFIELD
3609 uint64_t reserved_8_63:56;
3612 uint64_t reserved_3_3:1;
3620 uint64_t reserved_3_3:1;
3623 uint64_t reserved_8_63:56;
3628 union cvmx_mio_uartx_htx {
3630 struct cvmx_mio_uartx_htx_s {
3631 #ifdef __BIG_ENDIAN_BITFIELD
3632 uint64_t reserved_1_63:63;
3636 uint64_t reserved_1_63:63;
3641 union cvmx_mio_uartx_ier {
3643 struct cvmx_mio_uartx_ier_s {
3644 #ifdef __BIG_ENDIAN_BITFIELD
3645 uint64_t reserved_8_63:56;
3647 uint64_t reserved_4_6:3;
3657 uint64_t reserved_4_6:3;
3659 uint64_t reserved_8_63:56;
3664 union cvmx_mio_uartx_iir {
3666 struct cvmx_mio_uartx_iir_s {
3667 #ifdef __BIG_ENDIAN_BITFIELD
3668 uint64_t reserved_8_63:56;
3670 uint64_t reserved_4_5:2;
3674 uint64_t reserved_4_5:2;
3676 uint64_t reserved_8_63:56;
3681 union cvmx_mio_uartx_lcr {
3683 struct cvmx_mio_uartx_lcr_s {
3684 #ifdef __BIG_ENDIAN_BITFIELD
3685 uint64_t reserved_8_63:56;
3688 uint64_t reserved_5_5:1;
3698 uint64_t reserved_5_5:1;
3701 uint64_t reserved_8_63:56;
3706 union cvmx_mio_uartx_lsr {
3708 struct cvmx_mio_uartx_lsr_s {
3709 #ifdef __BIG_ENDIAN_BITFIELD
3710 uint64_t reserved_8_63:56;
3728 uint64_t reserved_8_63:56;
3733 union cvmx_mio_uartx_mcr {
3735 struct cvmx_mio_uartx_mcr_s {
3736 #ifdef __BIG_ENDIAN_BITFIELD
3737 uint64_t reserved_6_63:58;
3751 uint64_t reserved_6_63:58;
3756 union cvmx_mio_uartx_msr {
3758 struct cvmx_mio_uartx_msr_s {
3759 #ifdef __BIG_ENDIAN_BITFIELD
3760 uint64_t reserved_8_63:56;
3778 uint64_t reserved_8_63:56;
3783 union cvmx_mio_uartx_rbr {
3785 struct cvmx_mio_uartx_rbr_s {
3786 #ifdef __BIG_ENDIAN_BITFIELD
3787 uint64_t reserved_8_63:56;
3791 uint64_t reserved_8_63:56;
3796 union cvmx_mio_uartx_rfl {
3798 struct cvmx_mio_uartx_rfl_s {
3799 #ifdef __BIG_ENDIAN_BITFIELD
3800 uint64_t reserved_7_63:57;
3804 uint64_t reserved_7_63:57;
3809 union cvmx_mio_uartx_rfw {
3811 struct cvmx_mio_uartx_rfw_s {
3812 #ifdef __BIG_ENDIAN_BITFIELD
3813 uint64_t reserved_10_63:54;
3821 uint64_t reserved_10_63:54;
3826 union cvmx_mio_uartx_sbcr {
3828 struct cvmx_mio_uartx_sbcr_s {
3829 #ifdef __BIG_ENDIAN_BITFIELD
3830 uint64_t reserved_1_63:63;
3834 uint64_t reserved_1_63:63;
3839 union cvmx_mio_uartx_scr {
3841 struct cvmx_mio_uartx_scr_s {
3842 #ifdef __BIG_ENDIAN_BITFIELD
3843 uint64_t reserved_8_63:56;
3847 uint64_t reserved_8_63:56;
3852 union cvmx_mio_uartx_sfe {
3854 struct cvmx_mio_uartx_sfe_s {
3855 #ifdef __BIG_ENDIAN_BITFIELD
3856 uint64_t reserved_1_63:63;
3860 uint64_t reserved_1_63:63;
3865 union cvmx_mio_uartx_srr {
3867 struct cvmx_mio_uartx_srr_s {
3868 #ifdef __BIG_ENDIAN_BITFIELD
3869 uint64_t reserved_3_63:61;
3877 uint64_t reserved_3_63:61;
3882 union cvmx_mio_uartx_srt {
3884 struct cvmx_mio_uartx_srt_s {
3885 #ifdef __BIG_ENDIAN_BITFIELD
3886 uint64_t reserved_2_63:62;
3890 uint64_t reserved_2_63:62;
3895 union cvmx_mio_uartx_srts {
3897 struct cvmx_mio_uartx_srts_s {
3898 #ifdef __BIG_ENDIAN_BITFIELD
3899 uint64_t reserved_1_63:63;
3903 uint64_t reserved_1_63:63;
3908 union cvmx_mio_uartx_stt {
3910 struct cvmx_mio_uartx_stt_s {
3911 #ifdef __BIG_ENDIAN_BITFIELD
3912 uint64_t reserved_2_63:62;
3916 uint64_t reserved_2_63:62;
3921 union cvmx_mio_uartx_tfl {
3923 struct cvmx_mio_uartx_tfl_s {
3924 #ifdef __BIG_ENDIAN_BITFIELD
3925 uint64_t reserved_7_63:57;
3929 uint64_t reserved_7_63:57;
3934 union cvmx_mio_uartx_tfr {
3936 struct cvmx_mio_uartx_tfr_s {
3937 #ifdef __BIG_ENDIAN_BITFIELD
3938 uint64_t reserved_8_63:56;
3942 uint64_t reserved_8_63:56;
3947 union cvmx_mio_uartx_thr {
3949 struct cvmx_mio_uartx_thr_s {
3950 #ifdef __BIG_ENDIAN_BITFIELD
3951 uint64_t reserved_8_63:56;
3955 uint64_t reserved_8_63:56;
3960 union cvmx_mio_uartx_usr {
3962 struct cvmx_mio_uartx_usr_s {
3963 #ifdef __BIG_ENDIAN_BITFIELD
3964 uint64_t reserved_5_63:59;
3976 uint64_t reserved_5_63:59;
3981 union cvmx_mio_uart2_dlh {
3983 struct cvmx_mio_uart2_dlh_s {
3984 #ifdef __BIG_ENDIAN_BITFIELD
3985 uint64_t reserved_8_63:56;
3989 uint64_t reserved_8_63:56;
3994 union cvmx_mio_uart2_dll {
3996 struct cvmx_mio_uart2_dll_s {
3997 #ifdef __BIG_ENDIAN_BITFIELD
3998 uint64_t reserved_8_63:56;
4002 uint64_t reserved_8_63:56;
4007 union cvmx_mio_uart2_far {
4009 struct cvmx_mio_uart2_far_s {
4010 #ifdef __BIG_ENDIAN_BITFIELD
4011 uint64_t reserved_1_63:63;
4015 uint64_t reserved_1_63:63;
4020 union cvmx_mio_uart2_fcr {
4022 struct cvmx_mio_uart2_fcr_s {
4023 #ifdef __BIG_ENDIAN_BITFIELD
4024 uint64_t reserved_8_63:56;
4027 uint64_t reserved_3_3:1;
4035 uint64_t reserved_3_3:1;
4038 uint64_t reserved_8_63:56;
4043 union cvmx_mio_uart2_htx {
4045 struct cvmx_mio_uart2_htx_s {
4046 #ifdef __BIG_ENDIAN_BITFIELD
4047 uint64_t reserved_1_63:63;
4051 uint64_t reserved_1_63:63;
4056 union cvmx_mio_uart2_ier {
4058 struct cvmx_mio_uart2_ier_s {
4059 #ifdef __BIG_ENDIAN_BITFIELD
4060 uint64_t reserved_8_63:56;
4062 uint64_t reserved_4_6:3;
4072 uint64_t reserved_4_6:3;
4074 uint64_t reserved_8_63:56;
4079 union cvmx_mio_uart2_iir {
4081 struct cvmx_mio_uart2_iir_s {
4082 #ifdef __BIG_ENDIAN_BITFIELD
4083 uint64_t reserved_8_63:56;
4085 uint64_t reserved_4_5:2;
4089 uint64_t reserved_4_5:2;
4091 uint64_t reserved_8_63:56;
4096 union cvmx_mio_uart2_lcr {
4098 struct cvmx_mio_uart2_lcr_s {
4099 #ifdef __BIG_ENDIAN_BITFIELD
4100 uint64_t reserved_8_63:56;
4103 uint64_t reserved_5_5:1;
4113 uint64_t reserved_5_5:1;
4116 uint64_t reserved_8_63:56;
4121 union cvmx_mio_uart2_lsr {
4123 struct cvmx_mio_uart2_lsr_s {
4124 #ifdef __BIG_ENDIAN_BITFIELD
4125 uint64_t reserved_8_63:56;
4143 uint64_t reserved_8_63:56;
4148 union cvmx_mio_uart2_mcr {
4150 struct cvmx_mio_uart2_mcr_s {
4151 #ifdef __BIG_ENDIAN_BITFIELD
4152 uint64_t reserved_6_63:58;
4166 uint64_t reserved_6_63:58;
4171 union cvmx_mio_uart2_msr {
4173 struct cvmx_mio_uart2_msr_s {
4174 #ifdef __BIG_ENDIAN_BITFIELD
4175 uint64_t reserved_8_63:56;
4193 uint64_t reserved_8_63:56;
4198 union cvmx_mio_uart2_rbr {
4200 struct cvmx_mio_uart2_rbr_s {
4201 #ifdef __BIG_ENDIAN_BITFIELD
4202 uint64_t reserved_8_63:56;
4206 uint64_t reserved_8_63:56;
4211 union cvmx_mio_uart2_rfl {
4213 struct cvmx_mio_uart2_rfl_s {
4214 #ifdef __BIG_ENDIAN_BITFIELD
4215 uint64_t reserved_7_63:57;
4219 uint64_t reserved_7_63:57;
4224 union cvmx_mio_uart2_rfw {
4226 struct cvmx_mio_uart2_rfw_s {
4227 #ifdef __BIG_ENDIAN_BITFIELD
4228 uint64_t reserved_10_63:54;
4236 uint64_t reserved_10_63:54;
4241 union cvmx_mio_uart2_sbcr {
4243 struct cvmx_mio_uart2_sbcr_s {
4244 #ifdef __BIG_ENDIAN_BITFIELD
4245 uint64_t reserved_1_63:63;
4249 uint64_t reserved_1_63:63;
4254 union cvmx_mio_uart2_scr {
4256 struct cvmx_mio_uart2_scr_s {
4257 #ifdef __BIG_ENDIAN_BITFIELD
4258 uint64_t reserved_8_63:56;
4262 uint64_t reserved_8_63:56;
4267 union cvmx_mio_uart2_sfe {
4269 struct cvmx_mio_uart2_sfe_s {
4270 #ifdef __BIG_ENDIAN_BITFIELD
4271 uint64_t reserved_1_63:63;
4275 uint64_t reserved_1_63:63;
4280 union cvmx_mio_uart2_srr {
4282 struct cvmx_mio_uart2_srr_s {
4283 #ifdef __BIG_ENDIAN_BITFIELD
4284 uint64_t reserved_3_63:61;
4292 uint64_t reserved_3_63:61;
4297 union cvmx_mio_uart2_srt {
4299 struct cvmx_mio_uart2_srt_s {
4300 #ifdef __BIG_ENDIAN_BITFIELD
4301 uint64_t reserved_2_63:62;
4305 uint64_t reserved_2_63:62;
4310 union cvmx_mio_uart2_srts {
4312 struct cvmx_mio_uart2_srts_s {
4313 #ifdef __BIG_ENDIAN_BITFIELD
4314 uint64_t reserved_1_63:63;
4318 uint64_t reserved_1_63:63;
4323 union cvmx_mio_uart2_stt {
4325 struct cvmx_mio_uart2_stt_s {
4326 #ifdef __BIG_ENDIAN_BITFIELD
4327 uint64_t reserved_2_63:62;
4331 uint64_t reserved_2_63:62;
4336 union cvmx_mio_uart2_tfl {
4338 struct cvmx_mio_uart2_tfl_s {
4339 #ifdef __BIG_ENDIAN_BITFIELD
4340 uint64_t reserved_7_63:57;
4344 uint64_t reserved_7_63:57;
4349 union cvmx_mio_uart2_tfr {
4351 struct cvmx_mio_uart2_tfr_s {
4352 #ifdef __BIG_ENDIAN_BITFIELD
4353 uint64_t reserved_8_63:56;
4357 uint64_t reserved_8_63:56;
4362 union cvmx_mio_uart2_thr {
4364 struct cvmx_mio_uart2_thr_s {
4365 #ifdef __BIG_ENDIAN_BITFIELD
4366 uint64_t reserved_8_63:56;
4370 uint64_t reserved_8_63:56;
4375 union cvmx_mio_uart2_usr {
4377 struct cvmx_mio_uart2_usr_s {
4378 #ifdef __BIG_ENDIAN_BITFIELD
4379 uint64_t reserved_5_63:59;
4391 uint64_t reserved_5_63:59;