1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_LED_DEFS_H__
29 #define __CVMX_LED_DEFS_H__
31 #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
32 #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
33 #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
34 #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
35 #define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
36 #define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
37 #define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
38 #define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
39 #define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
40 #define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
41 #define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
42 #define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
43 #define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
45 union cvmx_led_blink {
47 struct cvmx_led_blink_s {
48 #ifdef __BIG_ENDIAN_BITFIELD
49 uint64_t reserved_8_63:56;
53 uint64_t reserved_8_63:56;
58 union cvmx_led_clk_phase {
60 struct cvmx_led_clk_phase_s {
61 #ifdef __BIG_ENDIAN_BITFIELD
62 uint64_t reserved_7_63:57;
66 uint64_t reserved_7_63:57;
71 union cvmx_led_cylon {
73 struct cvmx_led_cylon_s {
74 #ifdef __BIG_ENDIAN_BITFIELD
75 uint64_t reserved_16_63:48;
79 uint64_t reserved_16_63:48;
86 struct cvmx_led_dbg_s {
87 #ifdef __BIG_ENDIAN_BITFIELD
88 uint64_t reserved_1_63:63;
92 uint64_t reserved_1_63:63;
99 struct cvmx_led_en_s {
100 #ifdef __BIG_ENDIAN_BITFIELD
101 uint64_t reserved_1_63:63;
105 uint64_t reserved_1_63:63;
110 union cvmx_led_polarity {
112 struct cvmx_led_polarity_s {
113 #ifdef __BIG_ENDIAN_BITFIELD
114 uint64_t reserved_1_63:63;
118 uint64_t reserved_1_63:63;
125 struct cvmx_led_prt_s {
126 #ifdef __BIG_ENDIAN_BITFIELD
127 uint64_t reserved_8_63:56;
131 uint64_t reserved_8_63:56;
136 union cvmx_led_prt_fmt {
138 struct cvmx_led_prt_fmt_s {
139 #ifdef __BIG_ENDIAN_BITFIELD
140 uint64_t reserved_4_63:60;
144 uint64_t reserved_4_63:60;
149 union cvmx_led_prt_statusx {
151 struct cvmx_led_prt_statusx_s {
152 #ifdef __BIG_ENDIAN_BITFIELD
153 uint64_t reserved_6_63:58;
157 uint64_t reserved_6_63:58;
162 union cvmx_led_udd_cntx {
164 struct cvmx_led_udd_cntx_s {
165 #ifdef __BIG_ENDIAN_BITFIELD
166 uint64_t reserved_6_63:58;
170 uint64_t reserved_6_63:58;
175 union cvmx_led_udd_datx {
177 struct cvmx_led_udd_datx_s {
178 #ifdef __BIG_ENDIAN_BITFIELD
179 uint64_t reserved_32_63:32;
183 uint64_t reserved_32_63:32;
188 union cvmx_led_udd_dat_clrx {
190 struct cvmx_led_udd_dat_clrx_s {
191 #ifdef __BIG_ENDIAN_BITFIELD
192 uint64_t reserved_32_63:32;
196 uint64_t reserved_32_63:32;
201 union cvmx_led_udd_dat_setx {
203 struct cvmx_led_udd_dat_setx_s {
204 #ifdef __BIG_ENDIAN_BITFIELD
205 uint64_t reserved_32_63:32;
209 uint64_t reserved_32_63:32;