1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_IPD_DEFS_H__
29 #define __CVMX_IPD_DEFS_H__
31 #define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
32 #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
33 #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
34 #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
35 #define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
36 #define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
37 #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
38 #define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
39 #define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull))
40 #define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
41 #define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull))
42 #define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull))
43 #define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull))
44 #define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull))
45 #define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
46 #define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
47 #define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull))
48 #define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull))
49 #define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
50 #define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull))
51 #define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
52 #define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull))
53 #define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
54 #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
55 #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
56 #define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
57 #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
58 #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
59 #define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44)
60 #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
61 #define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull))
62 #define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
63 #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
64 #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
65 #define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull))
66 #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
67 #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
68 #define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
69 #define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
70 #define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
71 #define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
72 #define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
73 #define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
74 #define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
75 #define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
76 #define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
77 #define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
78 #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
79 #define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
80 #define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull))
81 #define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull))
82 #define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
83 #define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
84 #define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
85 #define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
86 #define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
87 #define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
88 #define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
89 #define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
90 #define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
91 #define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
92 #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
93 #define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull))
94 #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
95 #define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
96 #define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
97 #define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
98 #define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
100 union cvmx_ipd_1st_mbuff_skip {
102 struct cvmx_ipd_1st_mbuff_skip_s {
103 #ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_6_63:58;
108 uint64_t reserved_6_63:58;
113 union cvmx_ipd_1st_next_ptr_back {
115 struct cvmx_ipd_1st_next_ptr_back_s {
116 #ifdef __BIG_ENDIAN_BITFIELD
117 uint64_t reserved_4_63:60;
121 uint64_t reserved_4_63:60;
126 union cvmx_ipd_2nd_next_ptr_back {
128 struct cvmx_ipd_2nd_next_ptr_back_s {
129 #ifdef __BIG_ENDIAN_BITFIELD
130 uint64_t reserved_4_63:60;
134 uint64_t reserved_4_63:60;
139 union cvmx_ipd_bist_status {
141 struct cvmx_ipd_bist_status_s {
142 #ifdef __BIG_ENDIAN_BITFIELD
143 uint64_t reserved_23_63:41;
191 uint64_t reserved_23_63:41;
194 struct cvmx_ipd_bist_status_cn30xx {
195 #ifdef __BIG_ENDIAN_BITFIELD
196 uint64_t reserved_16_63:48;
230 uint64_t reserved_16_63:48;
233 struct cvmx_ipd_bist_status_cn52xx {
234 #ifdef __BIG_ENDIAN_BITFIELD
235 uint64_t reserved_18_63:46;
273 uint64_t reserved_18_63:46;
278 union cvmx_ipd_bp_prt_red_end {
280 struct cvmx_ipd_bp_prt_red_end_s {
281 #ifdef __BIG_ENDIAN_BITFIELD
282 uint64_t reserved_48_63:16;
286 uint64_t reserved_48_63:16;
289 struct cvmx_ipd_bp_prt_red_end_cn30xx {
290 #ifdef __BIG_ENDIAN_BITFIELD
291 uint64_t reserved_36_63:28;
295 uint64_t reserved_36_63:28;
298 struct cvmx_ipd_bp_prt_red_end_cn52xx {
299 #ifdef __BIG_ENDIAN_BITFIELD
300 uint64_t reserved_40_63:24;
304 uint64_t reserved_40_63:24;
307 struct cvmx_ipd_bp_prt_red_end_cn63xx {
308 #ifdef __BIG_ENDIAN_BITFIELD
309 uint64_t reserved_44_63:20;
313 uint64_t reserved_44_63:20;
318 union cvmx_ipd_bpidx_mbuf_th {
320 struct cvmx_ipd_bpidx_mbuf_th_s {
321 #ifdef __BIG_ENDIAN_BITFIELD
322 uint64_t reserved_18_63:46;
324 uint64_t page_cnt:17;
326 uint64_t page_cnt:17;
328 uint64_t reserved_18_63:46;
333 union cvmx_ipd_bpid_bp_counterx {
335 struct cvmx_ipd_bpid_bp_counterx_s {
336 #ifdef __BIG_ENDIAN_BITFIELD
337 uint64_t reserved_25_63:39;
341 uint64_t reserved_25_63:39;
346 union cvmx_ipd_clk_count {
348 struct cvmx_ipd_clk_count_s {
349 #ifdef __BIG_ENDIAN_BITFIELD
357 union cvmx_ipd_credits {
359 struct cvmx_ipd_credits_s {
360 #ifdef __BIG_ENDIAN_BITFIELD
361 uint64_t reserved_16_63:48;
367 uint64_t reserved_16_63:48;
372 union cvmx_ipd_ctl_status {
374 struct cvmx_ipd_ctl_status_s {
375 #ifdef __BIG_ENDIAN_BITFIELD
376 uint64_t reserved_18_63:46;
412 uint64_t reserved_18_63:46;
415 struct cvmx_ipd_ctl_status_cn30xx {
416 #ifdef __BIG_ENDIAN_BITFIELD
417 uint64_t reserved_10_63:54;
437 uint64_t reserved_10_63:54;
440 struct cvmx_ipd_ctl_status_cn38xxp2 {
441 #ifdef __BIG_ENDIAN_BITFIELD
442 uint64_t reserved_9_63:55;
460 uint64_t reserved_9_63:55;
463 struct cvmx_ipd_ctl_status_cn50xx {
464 #ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t reserved_15_63:49;
495 uint64_t reserved_15_63:49;
498 struct cvmx_ipd_ctl_status_cn58xx {
499 #ifdef __BIG_ENDIAN_BITFIELD
500 uint64_t reserved_12_63:52;
524 uint64_t reserved_12_63:52;
527 struct cvmx_ipd_ctl_status_cn63xxp1 {
528 #ifdef __BIG_ENDIAN_BITFIELD
529 uint64_t reserved_16_63:48;
561 uint64_t reserved_16_63:48;
566 union cvmx_ipd_ecc_ctl {
568 struct cvmx_ipd_ecc_ctl_s {
569 #ifdef __BIG_ENDIAN_BITFIELD
570 uint64_t reserved_8_63:56;
580 uint64_t reserved_8_63:56;
585 union cvmx_ipd_free_ptr_fifo_ctl {
587 struct cvmx_ipd_free_ptr_fifo_ctl_s {
588 #ifdef __BIG_ENDIAN_BITFIELD
589 uint64_t reserved_32_63:32;
601 uint64_t reserved_32_63:32;
606 union cvmx_ipd_free_ptr_value {
608 struct cvmx_ipd_free_ptr_value_s {
609 #ifdef __BIG_ENDIAN_BITFIELD
610 uint64_t reserved_33_63:31;
614 uint64_t reserved_33_63:31;
619 union cvmx_ipd_hold_ptr_fifo_ctl {
621 struct cvmx_ipd_hold_ptr_fifo_ctl_s {
622 #ifdef __BIG_ENDIAN_BITFIELD
623 uint64_t reserved_43_63:21;
635 uint64_t reserved_43_63:21;
640 union cvmx_ipd_int_enb {
642 struct cvmx_ipd_int_enb_s {
643 #ifdef __BIG_ENDIAN_BITFIELD
644 uint64_t reserved_23_63:41;
692 uint64_t reserved_23_63:41;
695 struct cvmx_ipd_int_enb_cn30xx {
696 #ifdef __BIG_ENDIAN_BITFIELD
697 uint64_t reserved_5_63:59;
709 uint64_t reserved_5_63:59;
712 struct cvmx_ipd_int_enb_cn38xx {
713 #ifdef __BIG_ENDIAN_BITFIELD
714 uint64_t reserved_10_63:54;
736 uint64_t reserved_10_63:54;
739 struct cvmx_ipd_int_enb_cn52xx {
740 #ifdef __BIG_ENDIAN_BITFIELD
741 uint64_t reserved_12_63:52;
767 uint64_t reserved_12_63:52;
772 union cvmx_ipd_int_sum {
774 struct cvmx_ipd_int_sum_s {
775 #ifdef __BIG_ENDIAN_BITFIELD
776 uint64_t reserved_23_63:41;
824 uint64_t reserved_23_63:41;
827 struct cvmx_ipd_int_sum_cn30xx {
828 #ifdef __BIG_ENDIAN_BITFIELD
829 uint64_t reserved_5_63:59;
841 uint64_t reserved_5_63:59;
844 struct cvmx_ipd_int_sum_cn38xx {
845 #ifdef __BIG_ENDIAN_BITFIELD
846 uint64_t reserved_10_63:54;
868 uint64_t reserved_10_63:54;
871 struct cvmx_ipd_int_sum_cn52xx {
872 #ifdef __BIG_ENDIAN_BITFIELD
873 uint64_t reserved_12_63:52;
899 uint64_t reserved_12_63:52;
904 union cvmx_ipd_next_pkt_ptr {
906 struct cvmx_ipd_next_pkt_ptr_s {
907 #ifdef __BIG_ENDIAN_BITFIELD
908 uint64_t reserved_33_63:31;
912 uint64_t reserved_33_63:31;
917 union cvmx_ipd_next_wqe_ptr {
919 struct cvmx_ipd_next_wqe_ptr_s {
920 #ifdef __BIG_ENDIAN_BITFIELD
921 uint64_t reserved_33_63:31;
925 uint64_t reserved_33_63:31;
930 union cvmx_ipd_not_1st_mbuff_skip {
932 struct cvmx_ipd_not_1st_mbuff_skip_s {
933 #ifdef __BIG_ENDIAN_BITFIELD
934 uint64_t reserved_6_63:58;
938 uint64_t reserved_6_63:58;
943 union cvmx_ipd_on_bp_drop_pktx {
945 struct cvmx_ipd_on_bp_drop_pktx_s {
946 #ifdef __BIG_ENDIAN_BITFIELD
954 union cvmx_ipd_packet_mbuff_size {
956 struct cvmx_ipd_packet_mbuff_size_s {
957 #ifdef __BIG_ENDIAN_BITFIELD
958 uint64_t reserved_12_63:52;
962 uint64_t reserved_12_63:52;
967 union cvmx_ipd_pkt_err {
969 struct cvmx_ipd_pkt_err_s {
970 #ifdef __BIG_ENDIAN_BITFIELD
971 uint64_t reserved_6_63:58;
975 uint64_t reserved_6_63:58;
980 union cvmx_ipd_pkt_ptr_valid {
982 struct cvmx_ipd_pkt_ptr_valid_s {
983 #ifdef __BIG_ENDIAN_BITFIELD
984 uint64_t reserved_29_63:35;
988 uint64_t reserved_29_63:35;
993 union cvmx_ipd_portx_bp_page_cnt {
995 struct cvmx_ipd_portx_bp_page_cnt_s {
996 #ifdef __BIG_ENDIAN_BITFIELD
997 uint64_t reserved_18_63:46;
999 uint64_t page_cnt:17;
1001 uint64_t page_cnt:17;
1003 uint64_t reserved_18_63:46;
1008 union cvmx_ipd_portx_bp_page_cnt2 {
1010 struct cvmx_ipd_portx_bp_page_cnt2_s {
1011 #ifdef __BIG_ENDIAN_BITFIELD
1012 uint64_t reserved_18_63:46;
1014 uint64_t page_cnt:17;
1016 uint64_t page_cnt:17;
1018 uint64_t reserved_18_63:46;
1023 union cvmx_ipd_portx_bp_page_cnt3 {
1025 struct cvmx_ipd_portx_bp_page_cnt3_s {
1026 #ifdef __BIG_ENDIAN_BITFIELD
1027 uint64_t reserved_18_63:46;
1029 uint64_t page_cnt:17;
1031 uint64_t page_cnt:17;
1033 uint64_t reserved_18_63:46;
1038 union cvmx_ipd_port_bp_counters2_pairx {
1040 struct cvmx_ipd_port_bp_counters2_pairx_s {
1041 #ifdef __BIG_ENDIAN_BITFIELD
1042 uint64_t reserved_25_63:39;
1043 uint64_t cnt_val:25;
1045 uint64_t cnt_val:25;
1046 uint64_t reserved_25_63:39;
1051 union cvmx_ipd_port_bp_counters3_pairx {
1053 struct cvmx_ipd_port_bp_counters3_pairx_s {
1054 #ifdef __BIG_ENDIAN_BITFIELD
1055 uint64_t reserved_25_63:39;
1056 uint64_t cnt_val:25;
1058 uint64_t cnt_val:25;
1059 uint64_t reserved_25_63:39;
1064 union cvmx_ipd_port_bp_counters4_pairx {
1066 struct cvmx_ipd_port_bp_counters4_pairx_s {
1067 #ifdef __BIG_ENDIAN_BITFIELD
1068 uint64_t reserved_25_63:39;
1069 uint64_t cnt_val:25;
1071 uint64_t cnt_val:25;
1072 uint64_t reserved_25_63:39;
1077 union cvmx_ipd_port_bp_counters_pairx {
1079 struct cvmx_ipd_port_bp_counters_pairx_s {
1080 #ifdef __BIG_ENDIAN_BITFIELD
1081 uint64_t reserved_25_63:39;
1082 uint64_t cnt_val:25;
1084 uint64_t cnt_val:25;
1085 uint64_t reserved_25_63:39;
1090 union cvmx_ipd_port_ptr_fifo_ctl {
1092 struct cvmx_ipd_port_ptr_fifo_ctl_s {
1093 #ifdef __BIG_ENDIAN_BITFIELD
1094 uint64_t reserved_48_63:16;
1104 uint64_t reserved_48_63:16;
1109 union cvmx_ipd_port_qos_x_cnt {
1111 struct cvmx_ipd_port_qos_x_cnt_s {
1112 #ifdef __BIG_ENDIAN_BITFIELD
1122 union cvmx_ipd_port_qos_intx {
1124 struct cvmx_ipd_port_qos_intx_s {
1125 #ifdef __BIG_ENDIAN_BITFIELD
1133 union cvmx_ipd_port_qos_int_enbx {
1135 struct cvmx_ipd_port_qos_int_enbx_s {
1136 #ifdef __BIG_ENDIAN_BITFIELD
1144 union cvmx_ipd_port_sopx {
1146 struct cvmx_ipd_port_sopx_s {
1147 #ifdef __BIG_ENDIAN_BITFIELD
1155 union cvmx_ipd_prc_hold_ptr_fifo_ctl {
1157 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
1158 #ifdef __BIG_ENDIAN_BITFIELD
1159 uint64_t reserved_39_63:25;
1171 uint64_t reserved_39_63:25;
1176 union cvmx_ipd_prc_port_ptr_fifo_ctl {
1178 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
1179 #ifdef __BIG_ENDIAN_BITFIELD
1180 uint64_t reserved_44_63:20;
1190 uint64_t reserved_44_63:20;
1195 union cvmx_ipd_ptr_count {
1197 struct cvmx_ipd_ptr_count_s {
1198 #ifdef __BIG_ENDIAN_BITFIELD
1199 uint64_t reserved_19_63:45;
1200 uint64_t pktv_cnt:1;
1201 uint64_t wqev_cnt:1;
1202 uint64_t pfif_cnt:3;
1203 uint64_t pkt_pcnt:7;
1204 uint64_t wqe_pcnt:7;
1206 uint64_t wqe_pcnt:7;
1207 uint64_t pkt_pcnt:7;
1208 uint64_t pfif_cnt:3;
1209 uint64_t wqev_cnt:1;
1210 uint64_t pktv_cnt:1;
1211 uint64_t reserved_19_63:45;
1216 union cvmx_ipd_pwp_ptr_fifo_ctl {
1218 struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220 uint64_t reserved_61_63:3;
1221 uint64_t max_cnts:7;
1233 uint64_t max_cnts:7;
1234 uint64_t reserved_61_63:3;
1239 union cvmx_ipd_qosx_red_marks {
1241 struct cvmx_ipd_qosx_red_marks_s {
1242 #ifdef __BIG_ENDIAN_BITFIELD
1252 union cvmx_ipd_que0_free_page_cnt {
1254 struct cvmx_ipd_que0_free_page_cnt_s {
1255 #ifdef __BIG_ENDIAN_BITFIELD
1256 uint64_t reserved_32_63:32;
1257 uint64_t q0_pcnt:32;
1259 uint64_t q0_pcnt:32;
1260 uint64_t reserved_32_63:32;
1265 union cvmx_ipd_red_bpid_enablex {
1267 struct cvmx_ipd_red_bpid_enablex_s {
1268 #ifdef __BIG_ENDIAN_BITFIELD
1269 uint64_t prt_enb:64;
1271 uint64_t prt_enb:64;
1276 union cvmx_ipd_red_delay {
1278 struct cvmx_ipd_red_delay_s {
1279 #ifdef __BIG_ENDIAN_BITFIELD
1280 uint64_t reserved_28_63:36;
1281 uint64_t prb_dly:14;
1282 uint64_t avg_dly:14;
1284 uint64_t avg_dly:14;
1285 uint64_t prb_dly:14;
1286 uint64_t reserved_28_63:36;
1291 union cvmx_ipd_red_port_enable {
1293 struct cvmx_ipd_red_port_enable_s {
1294 #ifdef __BIG_ENDIAN_BITFIELD
1295 uint64_t prb_dly:14;
1296 uint64_t avg_dly:14;
1297 uint64_t prt_enb:36;
1299 uint64_t prt_enb:36;
1300 uint64_t avg_dly:14;
1301 uint64_t prb_dly:14;
1306 union cvmx_ipd_red_port_enable2 {
1308 struct cvmx_ipd_red_port_enable2_s {
1309 #ifdef __BIG_ENDIAN_BITFIELD
1310 uint64_t reserved_12_63:52;
1311 uint64_t prt_enb:12;
1313 uint64_t prt_enb:12;
1314 uint64_t reserved_12_63:52;
1317 struct cvmx_ipd_red_port_enable2_cn52xx {
1318 #ifdef __BIG_ENDIAN_BITFIELD
1319 uint64_t reserved_4_63:60;
1323 uint64_t reserved_4_63:60;
1326 struct cvmx_ipd_red_port_enable2_cn63xx {
1327 #ifdef __BIG_ENDIAN_BITFIELD
1328 uint64_t reserved_8_63:56;
1332 uint64_t reserved_8_63:56;
1337 union cvmx_ipd_red_quex_param {
1339 struct cvmx_ipd_red_quex_param_s {
1340 #ifdef __BIG_ENDIAN_BITFIELD
1341 uint64_t reserved_49_63:15;
1342 uint64_t use_pcnt:1;
1345 uint64_t prb_con:32;
1347 uint64_t prb_con:32;
1350 uint64_t use_pcnt:1;
1351 uint64_t reserved_49_63:15;
1356 union cvmx_ipd_req_wgt {
1358 struct cvmx_ipd_req_wgt_s {
1359 #ifdef __BIG_ENDIAN_BITFIELD
1381 union cvmx_ipd_sub_port_bp_page_cnt {
1383 struct cvmx_ipd_sub_port_bp_page_cnt_s {
1384 #ifdef __BIG_ENDIAN_BITFIELD
1385 uint64_t reserved_31_63:33;
1387 uint64_t page_cnt:25;
1389 uint64_t page_cnt:25;
1391 uint64_t reserved_31_63:33;
1396 union cvmx_ipd_sub_port_fcs {
1398 struct cvmx_ipd_sub_port_fcs_s {
1399 #ifdef __BIG_ENDIAN_BITFIELD
1400 uint64_t reserved_40_63:24;
1401 uint64_t port_bit2:4;
1402 uint64_t reserved_32_35:4;
1403 uint64_t port_bit:32;
1405 uint64_t port_bit:32;
1406 uint64_t reserved_32_35:4;
1407 uint64_t port_bit2:4;
1408 uint64_t reserved_40_63:24;
1411 struct cvmx_ipd_sub_port_fcs_cn30xx {
1412 #ifdef __BIG_ENDIAN_BITFIELD
1413 uint64_t reserved_3_63:61;
1414 uint64_t port_bit:3;
1416 uint64_t port_bit:3;
1417 uint64_t reserved_3_63:61;
1420 struct cvmx_ipd_sub_port_fcs_cn38xx {
1421 #ifdef __BIG_ENDIAN_BITFIELD
1422 uint64_t reserved_32_63:32;
1423 uint64_t port_bit:32;
1425 uint64_t port_bit:32;
1426 uint64_t reserved_32_63:32;
1431 union cvmx_ipd_sub_port_qos_cnt {
1433 struct cvmx_ipd_sub_port_qos_cnt_s {
1434 #ifdef __BIG_ENDIAN_BITFIELD
1435 uint64_t reserved_41_63:23;
1436 uint64_t port_qos:9;
1440 uint64_t port_qos:9;
1441 uint64_t reserved_41_63:23;
1446 union cvmx_ipd_wqe_fpa_queue {
1448 struct cvmx_ipd_wqe_fpa_queue_s {
1449 #ifdef __BIG_ENDIAN_BITFIELD
1450 uint64_t reserved_3_63:61;
1451 uint64_t wqe_pool:3;
1453 uint64_t wqe_pool:3;
1454 uint64_t reserved_3_63:61;
1459 union cvmx_ipd_wqe_ptr_valid {
1461 struct cvmx_ipd_wqe_ptr_valid_s {
1462 #ifdef __BIG_ENDIAN_BITFIELD
1463 uint64_t reserved_29_63:35;
1467 uint64_t reserved_29_63:35;