1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_DPI_DEFS_H__
29 #define __CVMX_DPI_DEFS_H__
31 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35 #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41 #define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43 #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44 #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45 #define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46 #define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47 #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48 #define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49 #define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50 #define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51 #define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52 #define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53 #define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54 #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
60 switch (cvmx_get_octeon_family()) {
61 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
63 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
67 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
68 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
70 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
71 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
72 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
73 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
76 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
79 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
81 union cvmx_dpi_bist_status {
83 struct cvmx_dpi_bist_status_s {
84 #ifdef __BIG_ENDIAN_BITFIELD
85 uint64_t reserved_47_63:17;
89 uint64_t reserved_47_63:17;
92 struct cvmx_dpi_bist_status_s cn61xx;
93 struct cvmx_dpi_bist_status_cn63xx {
94 #ifdef __BIG_ENDIAN_BITFIELD
95 uint64_t reserved_45_63:19;
99 uint64_t reserved_45_63:19;
102 struct cvmx_dpi_bist_status_cn63xxp1 {
103 #ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_37_63:27;
108 uint64_t reserved_37_63:27;
111 struct cvmx_dpi_bist_status_s cn66xx;
112 struct cvmx_dpi_bist_status_cn63xx cn68xx;
113 struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
114 struct cvmx_dpi_bist_status_s cnf71xx;
119 struct cvmx_dpi_ctl_s {
120 #ifdef __BIG_ENDIAN_BITFIELD
121 uint64_t reserved_2_63:62;
127 uint64_t reserved_2_63:62;
130 struct cvmx_dpi_ctl_cn61xx {
131 #ifdef __BIG_ENDIAN_BITFIELD
132 uint64_t reserved_1_63:63;
136 uint64_t reserved_1_63:63;
139 struct cvmx_dpi_ctl_s cn63xx;
140 struct cvmx_dpi_ctl_s cn63xxp1;
141 struct cvmx_dpi_ctl_s cn66xx;
142 struct cvmx_dpi_ctl_s cn68xx;
143 struct cvmx_dpi_ctl_s cn68xxp1;
144 struct cvmx_dpi_ctl_cn61xx cnf71xx;
147 union cvmx_dpi_dmax_counts {
149 struct cvmx_dpi_dmax_counts_s {
150 #ifdef __BIG_ENDIAN_BITFIELD
151 uint64_t reserved_39_63:25;
157 uint64_t reserved_39_63:25;
160 struct cvmx_dpi_dmax_counts_s cn61xx;
161 struct cvmx_dpi_dmax_counts_s cn63xx;
162 struct cvmx_dpi_dmax_counts_s cn63xxp1;
163 struct cvmx_dpi_dmax_counts_s cn66xx;
164 struct cvmx_dpi_dmax_counts_s cn68xx;
165 struct cvmx_dpi_dmax_counts_s cn68xxp1;
166 struct cvmx_dpi_dmax_counts_s cnf71xx;
169 union cvmx_dpi_dmax_dbell {
171 struct cvmx_dpi_dmax_dbell_s {
172 #ifdef __BIG_ENDIAN_BITFIELD
173 uint64_t reserved_16_63:48;
177 uint64_t reserved_16_63:48;
180 struct cvmx_dpi_dmax_dbell_s cn61xx;
181 struct cvmx_dpi_dmax_dbell_s cn63xx;
182 struct cvmx_dpi_dmax_dbell_s cn63xxp1;
183 struct cvmx_dpi_dmax_dbell_s cn66xx;
184 struct cvmx_dpi_dmax_dbell_s cn68xx;
185 struct cvmx_dpi_dmax_dbell_s cn68xxp1;
186 struct cvmx_dpi_dmax_dbell_s cnf71xx;
189 union cvmx_dpi_dmax_err_rsp_status {
191 struct cvmx_dpi_dmax_err_rsp_status_s {
192 #ifdef __BIG_ENDIAN_BITFIELD
193 uint64_t reserved_6_63:58;
197 uint64_t reserved_6_63:58;
200 struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
201 struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
202 struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
203 struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
204 struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
207 union cvmx_dpi_dmax_ibuff_saddr {
209 struct cvmx_dpi_dmax_ibuff_saddr_s {
210 #ifdef __BIG_ENDIAN_BITFIELD
211 uint64_t reserved_62_63:2;
213 uint64_t reserved_41_47:7;
216 uint64_t reserved_0_6:7;
218 uint64_t reserved_0_6:7;
221 uint64_t reserved_41_47:7;
223 uint64_t reserved_62_63:2;
226 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
227 #ifdef __BIG_ENDIAN_BITFIELD
228 uint64_t reserved_62_63:2;
230 uint64_t reserved_41_47:7;
232 uint64_t reserved_36_39:4;
234 uint64_t reserved_0_6:7;
236 uint64_t reserved_0_6:7;
238 uint64_t reserved_36_39:4;
240 uint64_t reserved_41_47:7;
242 uint64_t reserved_62_63:2;
245 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
246 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
247 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
248 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
249 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
250 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
253 union cvmx_dpi_dmax_iflight {
255 struct cvmx_dpi_dmax_iflight_s {
256 #ifdef __BIG_ENDIAN_BITFIELD
257 uint64_t reserved_3_63:61;
261 uint64_t reserved_3_63:61;
264 struct cvmx_dpi_dmax_iflight_s cn61xx;
265 struct cvmx_dpi_dmax_iflight_s cn66xx;
266 struct cvmx_dpi_dmax_iflight_s cn68xx;
267 struct cvmx_dpi_dmax_iflight_s cn68xxp1;
268 struct cvmx_dpi_dmax_iflight_s cnf71xx;
271 union cvmx_dpi_dmax_naddr {
273 struct cvmx_dpi_dmax_naddr_s {
274 #ifdef __BIG_ENDIAN_BITFIELD
275 uint64_t reserved_40_63:24;
279 uint64_t reserved_40_63:24;
282 struct cvmx_dpi_dmax_naddr_cn61xx {
283 #ifdef __BIG_ENDIAN_BITFIELD
284 uint64_t reserved_36_63:28;
288 uint64_t reserved_36_63:28;
291 struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
292 struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
293 struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
294 struct cvmx_dpi_dmax_naddr_s cn68xx;
295 struct cvmx_dpi_dmax_naddr_s cn68xxp1;
296 struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
299 union cvmx_dpi_dmax_reqbnk0 {
301 struct cvmx_dpi_dmax_reqbnk0_s {
302 #ifdef __BIG_ENDIAN_BITFIELD
308 struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
309 struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
310 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
311 struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
312 struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
313 struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
314 struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
317 union cvmx_dpi_dmax_reqbnk1 {
319 struct cvmx_dpi_dmax_reqbnk1_s {
320 #ifdef __BIG_ENDIAN_BITFIELD
326 struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
327 struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
328 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
329 struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
330 struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
331 struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
332 struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
335 union cvmx_dpi_dma_control {
337 struct cvmx_dpi_dma_control_s {
338 #ifdef __BIG_ENDIAN_BITFIELD
339 uint64_t reserved_62_63:2;
340 uint64_t dici_mode:1;
343 uint64_t commit_mode:1;
346 uint64_t reserved_54_55:2;
348 uint64_t reserved_34_47:14;
358 uint64_t reserved_0_13:14;
360 uint64_t reserved_0_13:14;
370 uint64_t reserved_34_47:14;
372 uint64_t reserved_54_55:2;
375 uint64_t commit_mode:1;
378 uint64_t dici_mode:1;
379 uint64_t reserved_62_63:2;
382 struct cvmx_dpi_dma_control_s cn61xx;
383 struct cvmx_dpi_dma_control_cn63xx {
384 #ifdef __BIG_ENDIAN_BITFIELD
385 uint64_t reserved_61_63:3;
388 uint64_t commit_mode:1;
391 uint64_t reserved_54_55:2;
393 uint64_t reserved_34_47:14;
403 uint64_t reserved_0_13:14;
405 uint64_t reserved_0_13:14;
415 uint64_t reserved_34_47:14;
417 uint64_t reserved_54_55:2;
420 uint64_t commit_mode:1;
423 uint64_t reserved_61_63:3;
426 struct cvmx_dpi_dma_control_cn63xxp1 {
427 #ifdef __BIG_ENDIAN_BITFIELD
428 uint64_t reserved_59_63:5;
429 uint64_t commit_mode:1;
432 uint64_t reserved_54_55:2;
434 uint64_t reserved_34_47:14;
444 uint64_t reserved_0_13:14;
446 uint64_t reserved_0_13:14;
456 uint64_t reserved_34_47:14;
458 uint64_t reserved_54_55:2;
461 uint64_t commit_mode:1;
462 uint64_t reserved_59_63:5;
465 struct cvmx_dpi_dma_control_cn63xx cn66xx;
466 struct cvmx_dpi_dma_control_s cn68xx;
467 struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
468 struct cvmx_dpi_dma_control_s cnf71xx;
471 union cvmx_dpi_dma_engx_en {
473 struct cvmx_dpi_dma_engx_en_s {
474 #ifdef __BIG_ENDIAN_BITFIELD
475 uint64_t reserved_8_63:56;
479 uint64_t reserved_8_63:56;
482 struct cvmx_dpi_dma_engx_en_s cn61xx;
483 struct cvmx_dpi_dma_engx_en_s cn63xx;
484 struct cvmx_dpi_dma_engx_en_s cn63xxp1;
485 struct cvmx_dpi_dma_engx_en_s cn66xx;
486 struct cvmx_dpi_dma_engx_en_s cn68xx;
487 struct cvmx_dpi_dma_engx_en_s cn68xxp1;
488 struct cvmx_dpi_dma_engx_en_s cnf71xx;
491 union cvmx_dpi_dma_ppx_cnt {
493 struct cvmx_dpi_dma_ppx_cnt_s {
494 #ifdef __BIG_ENDIAN_BITFIELD
495 uint64_t reserved_16_63:48;
499 uint64_t reserved_16_63:48;
502 struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
503 struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
504 struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
507 union cvmx_dpi_engx_buf {
509 struct cvmx_dpi_engx_buf_s {
510 #ifdef __BIG_ENDIAN_BITFIELD
511 uint64_t reserved_37_63:27;
513 uint64_t reserved_9_31:23;
519 uint64_t reserved_9_31:23;
521 uint64_t reserved_37_63:27;
524 struct cvmx_dpi_engx_buf_s cn61xx;
525 struct cvmx_dpi_engx_buf_cn63xx {
526 #ifdef __BIG_ENDIAN_BITFIELD
527 uint64_t reserved_8_63:56;
533 uint64_t reserved_8_63:56;
536 struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
537 struct cvmx_dpi_engx_buf_s cn66xx;
538 struct cvmx_dpi_engx_buf_s cn68xx;
539 struct cvmx_dpi_engx_buf_s cn68xxp1;
540 struct cvmx_dpi_engx_buf_s cnf71xx;
543 union cvmx_dpi_info_reg {
545 struct cvmx_dpi_info_reg_s {
546 #ifdef __BIG_ENDIAN_BITFIELD
547 uint64_t reserved_8_63:56;
549 uint64_t reserved_2_3:2;
555 uint64_t reserved_2_3:2;
557 uint64_t reserved_8_63:56;
560 struct cvmx_dpi_info_reg_s cn61xx;
561 struct cvmx_dpi_info_reg_s cn63xx;
562 struct cvmx_dpi_info_reg_cn63xxp1 {
563 #ifdef __BIG_ENDIAN_BITFIELD
564 uint64_t reserved_2_63:62;
570 uint64_t reserved_2_63:62;
573 struct cvmx_dpi_info_reg_s cn66xx;
574 struct cvmx_dpi_info_reg_s cn68xx;
575 struct cvmx_dpi_info_reg_s cn68xxp1;
576 struct cvmx_dpi_info_reg_s cnf71xx;
579 union cvmx_dpi_int_en {
581 struct cvmx_dpi_int_en_s {
582 #ifdef __BIG_ENDIAN_BITFIELD
583 uint64_t reserved_28_63:36;
584 uint64_t sprt3_rst:1;
585 uint64_t sprt2_rst:1;
586 uint64_t sprt1_rst:1;
587 uint64_t sprt0_rst:1;
588 uint64_t reserved_23_23:1;
589 uint64_t req_badfil:1;
590 uint64_t req_inull:1;
591 uint64_t req_anull:1;
592 uint64_t req_undflw:1;
593 uint64_t req_ovrflw:1;
594 uint64_t req_badlen:1;
595 uint64_t req_badadr:1;
597 uint64_t reserved_2_7:6;
603 uint64_t reserved_2_7:6;
605 uint64_t req_badadr:1;
606 uint64_t req_badlen:1;
607 uint64_t req_ovrflw:1;
608 uint64_t req_undflw:1;
609 uint64_t req_anull:1;
610 uint64_t req_inull:1;
611 uint64_t req_badfil:1;
612 uint64_t reserved_23_23:1;
613 uint64_t sprt0_rst:1;
614 uint64_t sprt1_rst:1;
615 uint64_t sprt2_rst:1;
616 uint64_t sprt3_rst:1;
617 uint64_t reserved_28_63:36;
620 struct cvmx_dpi_int_en_s cn61xx;
621 struct cvmx_dpi_int_en_cn63xx {
622 #ifdef __BIG_ENDIAN_BITFIELD
623 uint64_t reserved_26_63:38;
624 uint64_t sprt1_rst:1;
625 uint64_t sprt0_rst:1;
626 uint64_t reserved_23_23:1;
627 uint64_t req_badfil:1;
628 uint64_t req_inull:1;
629 uint64_t req_anull:1;
630 uint64_t req_undflw:1;
631 uint64_t req_ovrflw:1;
632 uint64_t req_badlen:1;
633 uint64_t req_badadr:1;
635 uint64_t reserved_2_7:6;
641 uint64_t reserved_2_7:6;
643 uint64_t req_badadr:1;
644 uint64_t req_badlen:1;
645 uint64_t req_ovrflw:1;
646 uint64_t req_undflw:1;
647 uint64_t req_anull:1;
648 uint64_t req_inull:1;
649 uint64_t req_badfil:1;
650 uint64_t reserved_23_23:1;
651 uint64_t sprt0_rst:1;
652 uint64_t sprt1_rst:1;
653 uint64_t reserved_26_63:38;
656 struct cvmx_dpi_int_en_cn63xx cn63xxp1;
657 struct cvmx_dpi_int_en_s cn66xx;
658 struct cvmx_dpi_int_en_cn63xx cn68xx;
659 struct cvmx_dpi_int_en_cn63xx cn68xxp1;
660 struct cvmx_dpi_int_en_s cnf71xx;
663 union cvmx_dpi_int_reg {
665 struct cvmx_dpi_int_reg_s {
666 #ifdef __BIG_ENDIAN_BITFIELD
667 uint64_t reserved_28_63:36;
668 uint64_t sprt3_rst:1;
669 uint64_t sprt2_rst:1;
670 uint64_t sprt1_rst:1;
671 uint64_t sprt0_rst:1;
672 uint64_t reserved_23_23:1;
673 uint64_t req_badfil:1;
674 uint64_t req_inull:1;
675 uint64_t req_anull:1;
676 uint64_t req_undflw:1;
677 uint64_t req_ovrflw:1;
678 uint64_t req_badlen:1;
679 uint64_t req_badadr:1;
681 uint64_t reserved_2_7:6;
687 uint64_t reserved_2_7:6;
689 uint64_t req_badadr:1;
690 uint64_t req_badlen:1;
691 uint64_t req_ovrflw:1;
692 uint64_t req_undflw:1;
693 uint64_t req_anull:1;
694 uint64_t req_inull:1;
695 uint64_t req_badfil:1;
696 uint64_t reserved_23_23:1;
697 uint64_t sprt0_rst:1;
698 uint64_t sprt1_rst:1;
699 uint64_t sprt2_rst:1;
700 uint64_t sprt3_rst:1;
701 uint64_t reserved_28_63:36;
704 struct cvmx_dpi_int_reg_s cn61xx;
705 struct cvmx_dpi_int_reg_cn63xx {
706 #ifdef __BIG_ENDIAN_BITFIELD
707 uint64_t reserved_26_63:38;
708 uint64_t sprt1_rst:1;
709 uint64_t sprt0_rst:1;
710 uint64_t reserved_23_23:1;
711 uint64_t req_badfil:1;
712 uint64_t req_inull:1;
713 uint64_t req_anull:1;
714 uint64_t req_undflw:1;
715 uint64_t req_ovrflw:1;
716 uint64_t req_badlen:1;
717 uint64_t req_badadr:1;
719 uint64_t reserved_2_7:6;
725 uint64_t reserved_2_7:6;
727 uint64_t req_badadr:1;
728 uint64_t req_badlen:1;
729 uint64_t req_ovrflw:1;
730 uint64_t req_undflw:1;
731 uint64_t req_anull:1;
732 uint64_t req_inull:1;
733 uint64_t req_badfil:1;
734 uint64_t reserved_23_23:1;
735 uint64_t sprt0_rst:1;
736 uint64_t sprt1_rst:1;
737 uint64_t reserved_26_63:38;
740 struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
741 struct cvmx_dpi_int_reg_s cn66xx;
742 struct cvmx_dpi_int_reg_cn63xx cn68xx;
743 struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
744 struct cvmx_dpi_int_reg_s cnf71xx;
747 union cvmx_dpi_ncbx_cfg {
749 struct cvmx_dpi_ncbx_cfg_s {
750 #ifdef __BIG_ENDIAN_BITFIELD
751 uint64_t reserved_6_63:58;
755 uint64_t reserved_6_63:58;
758 struct cvmx_dpi_ncbx_cfg_s cn61xx;
759 struct cvmx_dpi_ncbx_cfg_s cn66xx;
760 struct cvmx_dpi_ncbx_cfg_s cn68xx;
761 struct cvmx_dpi_ncbx_cfg_s cnf71xx;
764 union cvmx_dpi_pint_info {
766 struct cvmx_dpi_pint_info_s {
767 #ifdef __BIG_ENDIAN_BITFIELD
768 uint64_t reserved_14_63:50;
770 uint64_t reserved_6_7:2;
774 uint64_t reserved_6_7:2;
776 uint64_t reserved_14_63:50;
779 struct cvmx_dpi_pint_info_s cn61xx;
780 struct cvmx_dpi_pint_info_s cn63xx;
781 struct cvmx_dpi_pint_info_s cn63xxp1;
782 struct cvmx_dpi_pint_info_s cn66xx;
783 struct cvmx_dpi_pint_info_s cn68xx;
784 struct cvmx_dpi_pint_info_s cn68xxp1;
785 struct cvmx_dpi_pint_info_s cnf71xx;
788 union cvmx_dpi_pkt_err_rsp {
790 struct cvmx_dpi_pkt_err_rsp_s {
791 #ifdef __BIG_ENDIAN_BITFIELD
792 uint64_t reserved_1_63:63;
796 uint64_t reserved_1_63:63;
799 struct cvmx_dpi_pkt_err_rsp_s cn61xx;
800 struct cvmx_dpi_pkt_err_rsp_s cn63xx;
801 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
802 struct cvmx_dpi_pkt_err_rsp_s cn66xx;
803 struct cvmx_dpi_pkt_err_rsp_s cn68xx;
804 struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
805 struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
808 union cvmx_dpi_req_err_rsp {
810 struct cvmx_dpi_req_err_rsp_s {
811 #ifdef __BIG_ENDIAN_BITFIELD
812 uint64_t reserved_8_63:56;
816 uint64_t reserved_8_63:56;
819 struct cvmx_dpi_req_err_rsp_s cn61xx;
820 struct cvmx_dpi_req_err_rsp_s cn63xx;
821 struct cvmx_dpi_req_err_rsp_s cn63xxp1;
822 struct cvmx_dpi_req_err_rsp_s cn66xx;
823 struct cvmx_dpi_req_err_rsp_s cn68xx;
824 struct cvmx_dpi_req_err_rsp_s cn68xxp1;
825 struct cvmx_dpi_req_err_rsp_s cnf71xx;
828 union cvmx_dpi_req_err_rsp_en {
830 struct cvmx_dpi_req_err_rsp_en_s {
831 #ifdef __BIG_ENDIAN_BITFIELD
832 uint64_t reserved_8_63:56;
836 uint64_t reserved_8_63:56;
839 struct cvmx_dpi_req_err_rsp_en_s cn61xx;
840 struct cvmx_dpi_req_err_rsp_en_s cn63xx;
841 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
842 struct cvmx_dpi_req_err_rsp_en_s cn66xx;
843 struct cvmx_dpi_req_err_rsp_en_s cn68xx;
844 struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
845 struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
848 union cvmx_dpi_req_err_rst {
850 struct cvmx_dpi_req_err_rst_s {
851 #ifdef __BIG_ENDIAN_BITFIELD
852 uint64_t reserved_8_63:56;
856 uint64_t reserved_8_63:56;
859 struct cvmx_dpi_req_err_rst_s cn61xx;
860 struct cvmx_dpi_req_err_rst_s cn63xx;
861 struct cvmx_dpi_req_err_rst_s cn63xxp1;
862 struct cvmx_dpi_req_err_rst_s cn66xx;
863 struct cvmx_dpi_req_err_rst_s cn68xx;
864 struct cvmx_dpi_req_err_rst_s cn68xxp1;
865 struct cvmx_dpi_req_err_rst_s cnf71xx;
868 union cvmx_dpi_req_err_rst_en {
870 struct cvmx_dpi_req_err_rst_en_s {
871 #ifdef __BIG_ENDIAN_BITFIELD
872 uint64_t reserved_8_63:56;
876 uint64_t reserved_8_63:56;
879 struct cvmx_dpi_req_err_rst_en_s cn61xx;
880 struct cvmx_dpi_req_err_rst_en_s cn63xx;
881 struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
882 struct cvmx_dpi_req_err_rst_en_s cn66xx;
883 struct cvmx_dpi_req_err_rst_en_s cn68xx;
884 struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
885 struct cvmx_dpi_req_err_rst_en_s cnf71xx;
888 union cvmx_dpi_req_err_skip_comp {
890 struct cvmx_dpi_req_err_skip_comp_s {
891 #ifdef __BIG_ENDIAN_BITFIELD
892 uint64_t reserved_24_63:40;
894 uint64_t reserved_8_15:8;
898 uint64_t reserved_8_15:8;
900 uint64_t reserved_24_63:40;
903 struct cvmx_dpi_req_err_skip_comp_s cn61xx;
904 struct cvmx_dpi_req_err_skip_comp_s cn66xx;
905 struct cvmx_dpi_req_err_skip_comp_s cn68xx;
906 struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
907 struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
910 union cvmx_dpi_req_gbl_en {
912 struct cvmx_dpi_req_gbl_en_s {
913 #ifdef __BIG_ENDIAN_BITFIELD
914 uint64_t reserved_8_63:56;
918 uint64_t reserved_8_63:56;
921 struct cvmx_dpi_req_gbl_en_s cn61xx;
922 struct cvmx_dpi_req_gbl_en_s cn63xx;
923 struct cvmx_dpi_req_gbl_en_s cn63xxp1;
924 struct cvmx_dpi_req_gbl_en_s cn66xx;
925 struct cvmx_dpi_req_gbl_en_s cn68xx;
926 struct cvmx_dpi_req_gbl_en_s cn68xxp1;
927 struct cvmx_dpi_req_gbl_en_s cnf71xx;
930 union cvmx_dpi_sli_prtx_cfg {
932 struct cvmx_dpi_sli_prtx_cfg_s {
933 #ifdef __BIG_ENDIAN_BITFIELD
934 uint64_t reserved_25_63:39;
937 uint64_t reserved_17_19:3;
939 uint64_t reserved_14_15:2;
942 uint64_t reserved_5_6:2;
945 uint64_t reserved_2_2:1;
949 uint64_t reserved_2_2:1;
952 uint64_t reserved_5_6:2;
955 uint64_t reserved_14_15:2;
957 uint64_t reserved_17_19:3;
960 uint64_t reserved_25_63:39;
963 struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
964 struct cvmx_dpi_sli_prtx_cfg_cn63xx {
965 #ifdef __BIG_ENDIAN_BITFIELD
966 uint64_t reserved_25_63:39;
968 uint64_t reserved_21_23:3;
970 uint64_t reserved_17_19:3;
972 uint64_t reserved_14_15:2;
975 uint64_t reserved_5_6:2;
978 uint64_t reserved_2_2:1;
982 uint64_t reserved_2_2:1;
985 uint64_t reserved_5_6:2;
988 uint64_t reserved_14_15:2;
990 uint64_t reserved_17_19:3;
992 uint64_t reserved_21_23:3;
994 uint64_t reserved_25_63:39;
997 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
998 struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
999 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
1000 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
1001 struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
1004 union cvmx_dpi_sli_prtx_err {
1006 struct cvmx_dpi_sli_prtx_err_s {
1007 #ifdef __BIG_ENDIAN_BITFIELD
1009 uint64_t reserved_0_2:3;
1011 uint64_t reserved_0_2:3;
1015 struct cvmx_dpi_sli_prtx_err_s cn61xx;
1016 struct cvmx_dpi_sli_prtx_err_s cn63xx;
1017 struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
1018 struct cvmx_dpi_sli_prtx_err_s cn66xx;
1019 struct cvmx_dpi_sli_prtx_err_s cn68xx;
1020 struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
1021 struct cvmx_dpi_sli_prtx_err_s cnf71xx;
1024 union cvmx_dpi_sli_prtx_err_info {
1026 struct cvmx_dpi_sli_prtx_err_info_s {
1027 #ifdef __BIG_ENDIAN_BITFIELD
1028 uint64_t reserved_9_63:55;
1030 uint64_t reserved_5_7:3;
1032 uint64_t reserved_3_3:1;
1036 uint64_t reserved_3_3:1;
1038 uint64_t reserved_5_7:3;
1040 uint64_t reserved_9_63:55;
1043 struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
1044 struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
1045 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
1046 struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
1047 struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
1048 struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
1049 struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;