1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_DPI_DEFS_H__
29 #define __CVMX_DPI_DEFS_H__
31 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35 #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41 #define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43 #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44 #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45 #define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46 #define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47 #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48 #define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49 #define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50 #define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51 #define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52 #define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53 #define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54 #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
60 switch (cvmx_get_octeon_family()) {
61 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
63 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
67 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
68 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
70 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
71 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
72 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
73 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
76 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
79 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
81 union cvmx_dpi_bist_status {
83 struct cvmx_dpi_bist_status_s {
84 #ifdef __BIG_ENDIAN_BITFIELD
85 uint64_t reserved_47_63:17;
89 uint64_t reserved_47_63:17;
92 struct cvmx_dpi_bist_status_cn63xx {
93 #ifdef __BIG_ENDIAN_BITFIELD
94 uint64_t reserved_45_63:19;
98 uint64_t reserved_45_63:19;
101 struct cvmx_dpi_bist_status_cn63xxp1 {
102 #ifdef __BIG_ENDIAN_BITFIELD
103 uint64_t reserved_37_63:27;
107 uint64_t reserved_37_63:27;
114 struct cvmx_dpi_ctl_s {
115 #ifdef __BIG_ENDIAN_BITFIELD
116 uint64_t reserved_2_63:62;
122 uint64_t reserved_2_63:62;
125 struct cvmx_dpi_ctl_cn61xx {
126 #ifdef __BIG_ENDIAN_BITFIELD
127 uint64_t reserved_1_63:63;
131 uint64_t reserved_1_63:63;
136 union cvmx_dpi_dmax_counts {
138 struct cvmx_dpi_dmax_counts_s {
139 #ifdef __BIG_ENDIAN_BITFIELD
140 uint64_t reserved_39_63:25;
146 uint64_t reserved_39_63:25;
151 union cvmx_dpi_dmax_dbell {
153 struct cvmx_dpi_dmax_dbell_s {
154 #ifdef __BIG_ENDIAN_BITFIELD
155 uint64_t reserved_16_63:48;
159 uint64_t reserved_16_63:48;
164 union cvmx_dpi_dmax_err_rsp_status {
166 struct cvmx_dpi_dmax_err_rsp_status_s {
167 #ifdef __BIG_ENDIAN_BITFIELD
168 uint64_t reserved_6_63:58;
172 uint64_t reserved_6_63:58;
177 union cvmx_dpi_dmax_ibuff_saddr {
179 struct cvmx_dpi_dmax_ibuff_saddr_s {
180 #ifdef __BIG_ENDIAN_BITFIELD
181 uint64_t reserved_62_63:2;
183 uint64_t reserved_41_47:7;
186 uint64_t reserved_0_6:7;
188 uint64_t reserved_0_6:7;
191 uint64_t reserved_41_47:7;
193 uint64_t reserved_62_63:2;
196 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
197 #ifdef __BIG_ENDIAN_BITFIELD
198 uint64_t reserved_62_63:2;
200 uint64_t reserved_41_47:7;
202 uint64_t reserved_36_39:4;
204 uint64_t reserved_0_6:7;
206 uint64_t reserved_0_6:7;
208 uint64_t reserved_36_39:4;
210 uint64_t reserved_41_47:7;
212 uint64_t reserved_62_63:2;
217 union cvmx_dpi_dmax_iflight {
219 struct cvmx_dpi_dmax_iflight_s {
220 #ifdef __BIG_ENDIAN_BITFIELD
221 uint64_t reserved_3_63:61;
225 uint64_t reserved_3_63:61;
230 union cvmx_dpi_dmax_naddr {
232 struct cvmx_dpi_dmax_naddr_s {
233 #ifdef __BIG_ENDIAN_BITFIELD
234 uint64_t reserved_40_63:24;
238 uint64_t reserved_40_63:24;
241 struct cvmx_dpi_dmax_naddr_cn61xx {
242 #ifdef __BIG_ENDIAN_BITFIELD
243 uint64_t reserved_36_63:28;
247 uint64_t reserved_36_63:28;
252 union cvmx_dpi_dmax_reqbnk0 {
254 struct cvmx_dpi_dmax_reqbnk0_s {
255 #ifdef __BIG_ENDIAN_BITFIELD
263 union cvmx_dpi_dmax_reqbnk1 {
265 struct cvmx_dpi_dmax_reqbnk1_s {
266 #ifdef __BIG_ENDIAN_BITFIELD
274 union cvmx_dpi_dma_control {
276 struct cvmx_dpi_dma_control_s {
277 #ifdef __BIG_ENDIAN_BITFIELD
278 uint64_t reserved_62_63:2;
279 uint64_t dici_mode:1;
282 uint64_t commit_mode:1;
285 uint64_t reserved_54_55:2;
287 uint64_t reserved_34_47:14;
297 uint64_t reserved_0_13:14;
299 uint64_t reserved_0_13:14;
309 uint64_t reserved_34_47:14;
311 uint64_t reserved_54_55:2;
314 uint64_t commit_mode:1;
317 uint64_t dici_mode:1;
318 uint64_t reserved_62_63:2;
321 struct cvmx_dpi_dma_control_cn63xx {
322 #ifdef __BIG_ENDIAN_BITFIELD
323 uint64_t reserved_61_63:3;
326 uint64_t commit_mode:1;
329 uint64_t reserved_54_55:2;
331 uint64_t reserved_34_47:14;
341 uint64_t reserved_0_13:14;
343 uint64_t reserved_0_13:14;
353 uint64_t reserved_34_47:14;
355 uint64_t reserved_54_55:2;
358 uint64_t commit_mode:1;
361 uint64_t reserved_61_63:3;
364 struct cvmx_dpi_dma_control_cn63xxp1 {
365 #ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_59_63:5;
367 uint64_t commit_mode:1;
370 uint64_t reserved_54_55:2;
372 uint64_t reserved_34_47:14;
382 uint64_t reserved_0_13:14;
384 uint64_t reserved_0_13:14;
394 uint64_t reserved_34_47:14;
396 uint64_t reserved_54_55:2;
399 uint64_t commit_mode:1;
400 uint64_t reserved_59_63:5;
405 union cvmx_dpi_dma_engx_en {
407 struct cvmx_dpi_dma_engx_en_s {
408 #ifdef __BIG_ENDIAN_BITFIELD
409 uint64_t reserved_8_63:56;
413 uint64_t reserved_8_63:56;
418 union cvmx_dpi_dma_ppx_cnt {
420 struct cvmx_dpi_dma_ppx_cnt_s {
421 #ifdef __BIG_ENDIAN_BITFIELD
422 uint64_t reserved_16_63:48;
426 uint64_t reserved_16_63:48;
431 union cvmx_dpi_engx_buf {
433 struct cvmx_dpi_engx_buf_s {
434 #ifdef __BIG_ENDIAN_BITFIELD
435 uint64_t reserved_37_63:27;
437 uint64_t reserved_9_31:23;
443 uint64_t reserved_9_31:23;
445 uint64_t reserved_37_63:27;
448 struct cvmx_dpi_engx_buf_cn63xx {
449 #ifdef __BIG_ENDIAN_BITFIELD
450 uint64_t reserved_8_63:56;
456 uint64_t reserved_8_63:56;
461 union cvmx_dpi_info_reg {
463 struct cvmx_dpi_info_reg_s {
464 #ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t reserved_8_63:56;
467 uint64_t reserved_2_3:2;
473 uint64_t reserved_2_3:2;
475 uint64_t reserved_8_63:56;
478 struct cvmx_dpi_info_reg_cn63xxp1 {
479 #ifdef __BIG_ENDIAN_BITFIELD
480 uint64_t reserved_2_63:62;
486 uint64_t reserved_2_63:62;
491 union cvmx_dpi_int_en {
493 struct cvmx_dpi_int_en_s {
494 #ifdef __BIG_ENDIAN_BITFIELD
495 uint64_t reserved_28_63:36;
496 uint64_t sprt3_rst:1;
497 uint64_t sprt2_rst:1;
498 uint64_t sprt1_rst:1;
499 uint64_t sprt0_rst:1;
500 uint64_t reserved_23_23:1;
501 uint64_t req_badfil:1;
502 uint64_t req_inull:1;
503 uint64_t req_anull:1;
504 uint64_t req_undflw:1;
505 uint64_t req_ovrflw:1;
506 uint64_t req_badlen:1;
507 uint64_t req_badadr:1;
509 uint64_t reserved_2_7:6;
515 uint64_t reserved_2_7:6;
517 uint64_t req_badadr:1;
518 uint64_t req_badlen:1;
519 uint64_t req_ovrflw:1;
520 uint64_t req_undflw:1;
521 uint64_t req_anull:1;
522 uint64_t req_inull:1;
523 uint64_t req_badfil:1;
524 uint64_t reserved_23_23:1;
525 uint64_t sprt0_rst:1;
526 uint64_t sprt1_rst:1;
527 uint64_t sprt2_rst:1;
528 uint64_t sprt3_rst:1;
529 uint64_t reserved_28_63:36;
532 struct cvmx_dpi_int_en_cn63xx {
533 #ifdef __BIG_ENDIAN_BITFIELD
534 uint64_t reserved_26_63:38;
535 uint64_t sprt1_rst:1;
536 uint64_t sprt0_rst:1;
537 uint64_t reserved_23_23:1;
538 uint64_t req_badfil:1;
539 uint64_t req_inull:1;
540 uint64_t req_anull:1;
541 uint64_t req_undflw:1;
542 uint64_t req_ovrflw:1;
543 uint64_t req_badlen:1;
544 uint64_t req_badadr:1;
546 uint64_t reserved_2_7:6;
552 uint64_t reserved_2_7:6;
554 uint64_t req_badadr:1;
555 uint64_t req_badlen:1;
556 uint64_t req_ovrflw:1;
557 uint64_t req_undflw:1;
558 uint64_t req_anull:1;
559 uint64_t req_inull:1;
560 uint64_t req_badfil:1;
561 uint64_t reserved_23_23:1;
562 uint64_t sprt0_rst:1;
563 uint64_t sprt1_rst:1;
564 uint64_t reserved_26_63:38;
569 union cvmx_dpi_int_reg {
571 struct cvmx_dpi_int_reg_s {
572 #ifdef __BIG_ENDIAN_BITFIELD
573 uint64_t reserved_28_63:36;
574 uint64_t sprt3_rst:1;
575 uint64_t sprt2_rst:1;
576 uint64_t sprt1_rst:1;
577 uint64_t sprt0_rst:1;
578 uint64_t reserved_23_23:1;
579 uint64_t req_badfil:1;
580 uint64_t req_inull:1;
581 uint64_t req_anull:1;
582 uint64_t req_undflw:1;
583 uint64_t req_ovrflw:1;
584 uint64_t req_badlen:1;
585 uint64_t req_badadr:1;
587 uint64_t reserved_2_7:6;
593 uint64_t reserved_2_7:6;
595 uint64_t req_badadr:1;
596 uint64_t req_badlen:1;
597 uint64_t req_ovrflw:1;
598 uint64_t req_undflw:1;
599 uint64_t req_anull:1;
600 uint64_t req_inull:1;
601 uint64_t req_badfil:1;
602 uint64_t reserved_23_23:1;
603 uint64_t sprt0_rst:1;
604 uint64_t sprt1_rst:1;
605 uint64_t sprt2_rst:1;
606 uint64_t sprt3_rst:1;
607 uint64_t reserved_28_63:36;
610 struct cvmx_dpi_int_reg_cn63xx {
611 #ifdef __BIG_ENDIAN_BITFIELD
612 uint64_t reserved_26_63:38;
613 uint64_t sprt1_rst:1;
614 uint64_t sprt0_rst:1;
615 uint64_t reserved_23_23:1;
616 uint64_t req_badfil:1;
617 uint64_t req_inull:1;
618 uint64_t req_anull:1;
619 uint64_t req_undflw:1;
620 uint64_t req_ovrflw:1;
621 uint64_t req_badlen:1;
622 uint64_t req_badadr:1;
624 uint64_t reserved_2_7:6;
630 uint64_t reserved_2_7:6;
632 uint64_t req_badadr:1;
633 uint64_t req_badlen:1;
634 uint64_t req_ovrflw:1;
635 uint64_t req_undflw:1;
636 uint64_t req_anull:1;
637 uint64_t req_inull:1;
638 uint64_t req_badfil:1;
639 uint64_t reserved_23_23:1;
640 uint64_t sprt0_rst:1;
641 uint64_t sprt1_rst:1;
642 uint64_t reserved_26_63:38;
647 union cvmx_dpi_ncbx_cfg {
649 struct cvmx_dpi_ncbx_cfg_s {
650 #ifdef __BIG_ENDIAN_BITFIELD
651 uint64_t reserved_6_63:58;
655 uint64_t reserved_6_63:58;
660 union cvmx_dpi_pint_info {
662 struct cvmx_dpi_pint_info_s {
663 #ifdef __BIG_ENDIAN_BITFIELD
664 uint64_t reserved_14_63:50;
666 uint64_t reserved_6_7:2;
670 uint64_t reserved_6_7:2;
672 uint64_t reserved_14_63:50;
677 union cvmx_dpi_pkt_err_rsp {
679 struct cvmx_dpi_pkt_err_rsp_s {
680 #ifdef __BIG_ENDIAN_BITFIELD
681 uint64_t reserved_1_63:63;
685 uint64_t reserved_1_63:63;
690 union cvmx_dpi_req_err_rsp {
692 struct cvmx_dpi_req_err_rsp_s {
693 #ifdef __BIG_ENDIAN_BITFIELD
694 uint64_t reserved_8_63:56;
698 uint64_t reserved_8_63:56;
703 union cvmx_dpi_req_err_rsp_en {
705 struct cvmx_dpi_req_err_rsp_en_s {
706 #ifdef __BIG_ENDIAN_BITFIELD
707 uint64_t reserved_8_63:56;
711 uint64_t reserved_8_63:56;
716 union cvmx_dpi_req_err_rst {
718 struct cvmx_dpi_req_err_rst_s {
719 #ifdef __BIG_ENDIAN_BITFIELD
720 uint64_t reserved_8_63:56;
724 uint64_t reserved_8_63:56;
729 union cvmx_dpi_req_err_rst_en {
731 struct cvmx_dpi_req_err_rst_en_s {
732 #ifdef __BIG_ENDIAN_BITFIELD
733 uint64_t reserved_8_63:56;
737 uint64_t reserved_8_63:56;
742 union cvmx_dpi_req_err_skip_comp {
744 struct cvmx_dpi_req_err_skip_comp_s {
745 #ifdef __BIG_ENDIAN_BITFIELD
746 uint64_t reserved_24_63:40;
748 uint64_t reserved_8_15:8;
752 uint64_t reserved_8_15:8;
754 uint64_t reserved_24_63:40;
759 union cvmx_dpi_req_gbl_en {
761 struct cvmx_dpi_req_gbl_en_s {
762 #ifdef __BIG_ENDIAN_BITFIELD
763 uint64_t reserved_8_63:56;
767 uint64_t reserved_8_63:56;
772 union cvmx_dpi_sli_prtx_cfg {
774 struct cvmx_dpi_sli_prtx_cfg_s {
775 #ifdef __BIG_ENDIAN_BITFIELD
776 uint64_t reserved_25_63:39;
779 uint64_t reserved_17_19:3;
781 uint64_t reserved_14_15:2;
784 uint64_t reserved_5_6:2;
787 uint64_t reserved_2_2:1;
791 uint64_t reserved_2_2:1;
794 uint64_t reserved_5_6:2;
797 uint64_t reserved_14_15:2;
799 uint64_t reserved_17_19:3;
802 uint64_t reserved_25_63:39;
805 struct cvmx_dpi_sli_prtx_cfg_cn63xx {
806 #ifdef __BIG_ENDIAN_BITFIELD
807 uint64_t reserved_25_63:39;
809 uint64_t reserved_21_23:3;
811 uint64_t reserved_17_19:3;
813 uint64_t reserved_14_15:2;
816 uint64_t reserved_5_6:2;
819 uint64_t reserved_2_2:1;
823 uint64_t reserved_2_2:1;
826 uint64_t reserved_5_6:2;
829 uint64_t reserved_14_15:2;
831 uint64_t reserved_17_19:3;
833 uint64_t reserved_21_23:3;
835 uint64_t reserved_25_63:39;
840 union cvmx_dpi_sli_prtx_err {
842 struct cvmx_dpi_sli_prtx_err_s {
843 #ifdef __BIG_ENDIAN_BITFIELD
845 uint64_t reserved_0_2:3;
847 uint64_t reserved_0_2:3;
853 union cvmx_dpi_sli_prtx_err_info {
855 struct cvmx_dpi_sli_prtx_err_info_s {
856 #ifdef __BIG_ENDIAN_BITFIELD
857 uint64_t reserved_9_63:55;
859 uint64_t reserved_5_7:3;
861 uint64_t reserved_3_3:1;
865 uint64_t reserved_3_3:1;
867 uint64_t reserved_5_7:3;
869 uint64_t reserved_9_63:55;