1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_ASXX_DEFS_H__
29 #define __CVMX_ASXX_DEFS_H__
31 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
32 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
33 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
36 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
41 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
45 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
46 #define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
47 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
48 #define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
49 #define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
50 #define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
51 #define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
52 #define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
53 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
54 #define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
55 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
56 #define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
58 union cvmx_asxx_gmii_rx_clk_set {
60 struct cvmx_asxx_gmii_rx_clk_set_s {
61 #ifdef __BIG_ENDIAN_BITFIELD
62 uint64_t reserved_5_63:59;
66 uint64_t reserved_5_63:59;
69 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
70 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
71 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
74 union cvmx_asxx_gmii_rx_dat_set {
76 struct cvmx_asxx_gmii_rx_dat_set_s {
77 #ifdef __BIG_ENDIAN_BITFIELD
78 uint64_t reserved_5_63:59;
82 uint64_t reserved_5_63:59;
85 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
86 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
87 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
90 union cvmx_asxx_int_en {
92 struct cvmx_asxx_int_en_s {
93 #ifdef __BIG_ENDIAN_BITFIELD
94 uint64_t reserved_12_63:52;
102 uint64_t reserved_12_63:52;
105 struct cvmx_asxx_int_en_cn30xx {
106 #ifdef __BIG_ENDIAN_BITFIELD
107 uint64_t reserved_11_63:53;
109 uint64_t reserved_7_7:1;
111 uint64_t reserved_3_3:1;
115 uint64_t reserved_3_3:1;
117 uint64_t reserved_7_7:1;
119 uint64_t reserved_11_63:53;
122 struct cvmx_asxx_int_en_cn30xx cn31xx;
123 struct cvmx_asxx_int_en_s cn38xx;
124 struct cvmx_asxx_int_en_s cn38xxp2;
125 struct cvmx_asxx_int_en_cn30xx cn50xx;
126 struct cvmx_asxx_int_en_s cn58xx;
127 struct cvmx_asxx_int_en_s cn58xxp1;
130 union cvmx_asxx_int_reg {
132 struct cvmx_asxx_int_reg_s {
133 #ifdef __BIG_ENDIAN_BITFIELD
134 uint64_t reserved_12_63:52;
142 uint64_t reserved_12_63:52;
145 struct cvmx_asxx_int_reg_cn30xx {
146 #ifdef __BIG_ENDIAN_BITFIELD
147 uint64_t reserved_11_63:53;
149 uint64_t reserved_7_7:1;
151 uint64_t reserved_3_3:1;
155 uint64_t reserved_3_3:1;
157 uint64_t reserved_7_7:1;
159 uint64_t reserved_11_63:53;
162 struct cvmx_asxx_int_reg_cn30xx cn31xx;
163 struct cvmx_asxx_int_reg_s cn38xx;
164 struct cvmx_asxx_int_reg_s cn38xxp2;
165 struct cvmx_asxx_int_reg_cn30xx cn50xx;
166 struct cvmx_asxx_int_reg_s cn58xx;
167 struct cvmx_asxx_int_reg_s cn58xxp1;
170 union cvmx_asxx_mii_rx_dat_set {
172 struct cvmx_asxx_mii_rx_dat_set_s {
173 #ifdef __BIG_ENDIAN_BITFIELD
174 uint64_t reserved_5_63:59;
178 uint64_t reserved_5_63:59;
181 struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
182 struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
185 union cvmx_asxx_prt_loop {
187 struct cvmx_asxx_prt_loop_s {
188 #ifdef __BIG_ENDIAN_BITFIELD
189 uint64_t reserved_8_63:56;
195 uint64_t reserved_8_63:56;
198 struct cvmx_asxx_prt_loop_cn30xx {
199 #ifdef __BIG_ENDIAN_BITFIELD
200 uint64_t reserved_7_63:57;
202 uint64_t reserved_3_3:1;
206 uint64_t reserved_3_3:1;
208 uint64_t reserved_7_63:57;
211 struct cvmx_asxx_prt_loop_cn30xx cn31xx;
212 struct cvmx_asxx_prt_loop_s cn38xx;
213 struct cvmx_asxx_prt_loop_s cn38xxp2;
214 struct cvmx_asxx_prt_loop_cn30xx cn50xx;
215 struct cvmx_asxx_prt_loop_s cn58xx;
216 struct cvmx_asxx_prt_loop_s cn58xxp1;
219 union cvmx_asxx_rld_bypass {
221 struct cvmx_asxx_rld_bypass_s {
222 #ifdef __BIG_ENDIAN_BITFIELD
223 uint64_t reserved_1_63:63;
227 uint64_t reserved_1_63:63;
230 struct cvmx_asxx_rld_bypass_s cn38xx;
231 struct cvmx_asxx_rld_bypass_s cn38xxp2;
232 struct cvmx_asxx_rld_bypass_s cn58xx;
233 struct cvmx_asxx_rld_bypass_s cn58xxp1;
236 union cvmx_asxx_rld_bypass_setting {
238 struct cvmx_asxx_rld_bypass_setting_s {
239 #ifdef __BIG_ENDIAN_BITFIELD
240 uint64_t reserved_5_63:59;
244 uint64_t reserved_5_63:59;
247 struct cvmx_asxx_rld_bypass_setting_s cn38xx;
248 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
249 struct cvmx_asxx_rld_bypass_setting_s cn58xx;
250 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
253 union cvmx_asxx_rld_comp {
255 struct cvmx_asxx_rld_comp_s {
256 #ifdef __BIG_ENDIAN_BITFIELD
257 uint64_t reserved_9_63:55;
263 uint64_t reserved_9_63:55;
266 struct cvmx_asxx_rld_comp_cn38xx {
267 #ifdef __BIG_ENDIAN_BITFIELD
268 uint64_t reserved_8_63:56;
274 uint64_t reserved_8_63:56;
277 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
278 struct cvmx_asxx_rld_comp_s cn58xx;
279 struct cvmx_asxx_rld_comp_s cn58xxp1;
282 union cvmx_asxx_rld_data_drv {
284 struct cvmx_asxx_rld_data_drv_s {
285 #ifdef __BIG_ENDIAN_BITFIELD
286 uint64_t reserved_8_63:56;
292 uint64_t reserved_8_63:56;
295 struct cvmx_asxx_rld_data_drv_s cn38xx;
296 struct cvmx_asxx_rld_data_drv_s cn38xxp2;
297 struct cvmx_asxx_rld_data_drv_s cn58xx;
298 struct cvmx_asxx_rld_data_drv_s cn58xxp1;
301 union cvmx_asxx_rld_fcram_mode {
303 struct cvmx_asxx_rld_fcram_mode_s {
304 #ifdef __BIG_ENDIAN_BITFIELD
305 uint64_t reserved_1_63:63;
309 uint64_t reserved_1_63:63;
312 struct cvmx_asxx_rld_fcram_mode_s cn38xx;
313 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
316 union cvmx_asxx_rld_nctl_strong {
318 struct cvmx_asxx_rld_nctl_strong_s {
319 #ifdef __BIG_ENDIAN_BITFIELD
320 uint64_t reserved_5_63:59;
324 uint64_t reserved_5_63:59;
327 struct cvmx_asxx_rld_nctl_strong_s cn38xx;
328 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
329 struct cvmx_asxx_rld_nctl_strong_s cn58xx;
330 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
333 union cvmx_asxx_rld_nctl_weak {
335 struct cvmx_asxx_rld_nctl_weak_s {
336 #ifdef __BIG_ENDIAN_BITFIELD
337 uint64_t reserved_5_63:59;
341 uint64_t reserved_5_63:59;
344 struct cvmx_asxx_rld_nctl_weak_s cn38xx;
345 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
346 struct cvmx_asxx_rld_nctl_weak_s cn58xx;
347 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
350 union cvmx_asxx_rld_pctl_strong {
352 struct cvmx_asxx_rld_pctl_strong_s {
353 #ifdef __BIG_ENDIAN_BITFIELD
354 uint64_t reserved_5_63:59;
358 uint64_t reserved_5_63:59;
361 struct cvmx_asxx_rld_pctl_strong_s cn38xx;
362 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
363 struct cvmx_asxx_rld_pctl_strong_s cn58xx;
364 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
367 union cvmx_asxx_rld_pctl_weak {
369 struct cvmx_asxx_rld_pctl_weak_s {
370 #ifdef __BIG_ENDIAN_BITFIELD
371 uint64_t reserved_5_63:59;
375 uint64_t reserved_5_63:59;
378 struct cvmx_asxx_rld_pctl_weak_s cn38xx;
379 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
380 struct cvmx_asxx_rld_pctl_weak_s cn58xx;
381 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
384 union cvmx_asxx_rld_setting {
386 struct cvmx_asxx_rld_setting_s {
387 #ifdef __BIG_ENDIAN_BITFIELD
388 uint64_t reserved_13_63:51;
400 uint64_t reserved_13_63:51;
403 struct cvmx_asxx_rld_setting_cn38xx {
404 #ifdef __BIG_ENDIAN_BITFIELD
405 uint64_t reserved_5_63:59;
409 uint64_t reserved_5_63:59;
412 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
413 struct cvmx_asxx_rld_setting_s cn58xx;
414 struct cvmx_asxx_rld_setting_s cn58xxp1;
417 union cvmx_asxx_rx_clk_setx {
419 struct cvmx_asxx_rx_clk_setx_s {
420 #ifdef __BIG_ENDIAN_BITFIELD
421 uint64_t reserved_5_63:59;
425 uint64_t reserved_5_63:59;
428 struct cvmx_asxx_rx_clk_setx_s cn30xx;
429 struct cvmx_asxx_rx_clk_setx_s cn31xx;
430 struct cvmx_asxx_rx_clk_setx_s cn38xx;
431 struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
432 struct cvmx_asxx_rx_clk_setx_s cn50xx;
433 struct cvmx_asxx_rx_clk_setx_s cn58xx;
434 struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
437 union cvmx_asxx_rx_prt_en {
439 struct cvmx_asxx_rx_prt_en_s {
440 #ifdef __BIG_ENDIAN_BITFIELD
441 uint64_t reserved_4_63:60;
445 uint64_t reserved_4_63:60;
448 struct cvmx_asxx_rx_prt_en_cn30xx {
449 #ifdef __BIG_ENDIAN_BITFIELD
450 uint64_t reserved_3_63:61;
454 uint64_t reserved_3_63:61;
457 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
458 struct cvmx_asxx_rx_prt_en_s cn38xx;
459 struct cvmx_asxx_rx_prt_en_s cn38xxp2;
460 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
461 struct cvmx_asxx_rx_prt_en_s cn58xx;
462 struct cvmx_asxx_rx_prt_en_s cn58xxp1;
465 union cvmx_asxx_rx_wol {
467 struct cvmx_asxx_rx_wol_s {
468 #ifdef __BIG_ENDIAN_BITFIELD
469 uint64_t reserved_2_63:62;
475 uint64_t reserved_2_63:62;
478 struct cvmx_asxx_rx_wol_s cn38xx;
479 struct cvmx_asxx_rx_wol_s cn38xxp2;
482 union cvmx_asxx_rx_wol_msk {
484 struct cvmx_asxx_rx_wol_msk_s {
485 #ifdef __BIG_ENDIAN_BITFIELD
491 struct cvmx_asxx_rx_wol_msk_s cn38xx;
492 struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
495 union cvmx_asxx_rx_wol_powok {
497 struct cvmx_asxx_rx_wol_powok_s {
498 #ifdef __BIG_ENDIAN_BITFIELD
499 uint64_t reserved_1_63:63;
503 uint64_t reserved_1_63:63;
506 struct cvmx_asxx_rx_wol_powok_s cn38xx;
507 struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
510 union cvmx_asxx_rx_wol_sig {
512 struct cvmx_asxx_rx_wol_sig_s {
513 #ifdef __BIG_ENDIAN_BITFIELD
514 uint64_t reserved_32_63:32;
518 uint64_t reserved_32_63:32;
521 struct cvmx_asxx_rx_wol_sig_s cn38xx;
522 struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
525 union cvmx_asxx_tx_clk_setx {
527 struct cvmx_asxx_tx_clk_setx_s {
528 #ifdef __BIG_ENDIAN_BITFIELD
529 uint64_t reserved_5_63:59;
533 uint64_t reserved_5_63:59;
536 struct cvmx_asxx_tx_clk_setx_s cn30xx;
537 struct cvmx_asxx_tx_clk_setx_s cn31xx;
538 struct cvmx_asxx_tx_clk_setx_s cn38xx;
539 struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
540 struct cvmx_asxx_tx_clk_setx_s cn50xx;
541 struct cvmx_asxx_tx_clk_setx_s cn58xx;
542 struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
545 union cvmx_asxx_tx_comp_byp {
547 struct cvmx_asxx_tx_comp_byp_s {
548 #ifdef __BIG_ENDIAN_BITFIELD
549 uint64_t reserved_0_63:64;
551 uint64_t reserved_0_63:64;
554 struct cvmx_asxx_tx_comp_byp_cn30xx {
555 #ifdef __BIG_ENDIAN_BITFIELD
556 uint64_t reserved_9_63:55;
564 uint64_t reserved_9_63:55;
567 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
568 struct cvmx_asxx_tx_comp_byp_cn38xx {
569 #ifdef __BIG_ENDIAN_BITFIELD
570 uint64_t reserved_8_63:56;
576 uint64_t reserved_8_63:56;
579 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
580 struct cvmx_asxx_tx_comp_byp_cn50xx {
581 #ifdef __BIG_ENDIAN_BITFIELD
582 uint64_t reserved_17_63:47;
584 uint64_t reserved_13_15:3;
586 uint64_t reserved_5_7:3;
590 uint64_t reserved_5_7:3;
592 uint64_t reserved_13_15:3;
594 uint64_t reserved_17_63:47;
597 struct cvmx_asxx_tx_comp_byp_cn58xx {
598 #ifdef __BIG_ENDIAN_BITFIELD
599 uint64_t reserved_13_63:51;
601 uint64_t reserved_5_7:3;
605 uint64_t reserved_5_7:3;
607 uint64_t reserved_13_63:51;
610 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
613 union cvmx_asxx_tx_hi_waterx {
615 struct cvmx_asxx_tx_hi_waterx_s {
616 #ifdef __BIG_ENDIAN_BITFIELD
617 uint64_t reserved_4_63:60;
621 uint64_t reserved_4_63:60;
624 struct cvmx_asxx_tx_hi_waterx_cn30xx {
625 #ifdef __BIG_ENDIAN_BITFIELD
626 uint64_t reserved_3_63:61;
630 uint64_t reserved_3_63:61;
633 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
634 struct cvmx_asxx_tx_hi_waterx_s cn38xx;
635 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
636 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
637 struct cvmx_asxx_tx_hi_waterx_s cn58xx;
638 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
641 union cvmx_asxx_tx_prt_en {
643 struct cvmx_asxx_tx_prt_en_s {
644 #ifdef __BIG_ENDIAN_BITFIELD
645 uint64_t reserved_4_63:60;
649 uint64_t reserved_4_63:60;
652 struct cvmx_asxx_tx_prt_en_cn30xx {
653 #ifdef __BIG_ENDIAN_BITFIELD
654 uint64_t reserved_3_63:61;
658 uint64_t reserved_3_63:61;
661 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
662 struct cvmx_asxx_tx_prt_en_s cn38xx;
663 struct cvmx_asxx_tx_prt_en_s cn38xxp2;
664 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
665 struct cvmx_asxx_tx_prt_en_s cn58xx;
666 struct cvmx_asxx_tx_prt_en_s cn58xxp1;