1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_AGL_DEFS_H__
29 #define __CVMX_AGL_DEFS_H__
31 #define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
32 #define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
33 #define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
34 #define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
35 #define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
36 #define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
37 #define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
38 #define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
39 #define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
40 #define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
41 #define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
42 #define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
43 #define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
44 #define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
45 #define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
46 #define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
47 #define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
48 #define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
49 #define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
50 #define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
51 #define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
52 #define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
53 #define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
54 #define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
55 #define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
56 #define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
57 #define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
58 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
59 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
60 #define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
61 #define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
62 #define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
63 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
64 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
65 #define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
66 #define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
67 #define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
68 #define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
69 #define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
70 #define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
71 #define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
72 #define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
73 #define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
74 #define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
75 #define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
76 #define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
77 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
78 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
79 #define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
80 #define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
81 #define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
82 #define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
83 #define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
84 #define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
85 #define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
86 #define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
87 #define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
88 #define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
89 #define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
90 #define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
91 #define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
92 #define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
93 #define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
94 #define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
95 #define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
96 #define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
97 #define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
98 #define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
99 #define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
100 #define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
101 #define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
102 #define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
103 #define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
104 #define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
106 union cvmx_agl_gmx_bad_reg {
108 struct cvmx_agl_gmx_bad_reg_s {
109 #ifdef __BIG_ENDIAN_BITFIELD
110 uint64_t reserved_38_63:26;
117 uint64_t reserved_27_31:5;
119 uint64_t reserved_24_25:2;
121 uint64_t reserved_4_21:18;
123 uint64_t reserved_0_1:2;
125 uint64_t reserved_0_1:2;
127 uint64_t reserved_4_21:18;
129 uint64_t reserved_24_25:2;
131 uint64_t reserved_27_31:5;
138 uint64_t reserved_38_63:26;
141 struct cvmx_agl_gmx_bad_reg_cn52xx {
142 #ifdef __BIG_ENDIAN_BITFIELD
143 uint64_t reserved_38_63:26;
150 uint64_t reserved_27_31:5;
152 uint64_t reserved_23_25:3;
154 uint64_t reserved_4_21:18;
156 uint64_t reserved_0_1:2;
158 uint64_t reserved_0_1:2;
160 uint64_t reserved_4_21:18;
162 uint64_t reserved_23_25:3;
164 uint64_t reserved_27_31:5;
171 uint64_t reserved_38_63:26;
174 struct cvmx_agl_gmx_bad_reg_cn56xx {
175 #ifdef __BIG_ENDIAN_BITFIELD
176 uint64_t reserved_35_63:29;
180 uint64_t reserved_27_31:5;
182 uint64_t reserved_23_25:3;
184 uint64_t reserved_3_21:19;
186 uint64_t reserved_0_1:2;
188 uint64_t reserved_0_1:2;
190 uint64_t reserved_3_21:19;
192 uint64_t reserved_23_25:3;
194 uint64_t reserved_27_31:5;
198 uint64_t reserved_35_63:29;
203 union cvmx_agl_gmx_bist {
205 struct cvmx_agl_gmx_bist_s {
206 #ifdef __BIG_ENDIAN_BITFIELD
207 uint64_t reserved_25_63:39;
211 uint64_t reserved_25_63:39;
214 struct cvmx_agl_gmx_bist_cn52xx {
215 #ifdef __BIG_ENDIAN_BITFIELD
216 uint64_t reserved_10_63:54;
220 uint64_t reserved_10_63:54;
225 union cvmx_agl_gmx_drv_ctl {
227 struct cvmx_agl_gmx_drv_ctl_s {
228 #ifdef __BIG_ENDIAN_BITFIELD
229 uint64_t reserved_49_63:15;
231 uint64_t reserved_45_47:3;
233 uint64_t reserved_37_39:3;
235 uint64_t reserved_17_31:15;
237 uint64_t reserved_13_15:3;
239 uint64_t reserved_5_7:3;
243 uint64_t reserved_5_7:3;
245 uint64_t reserved_13_15:3;
247 uint64_t reserved_17_31:15;
249 uint64_t reserved_37_39:3;
251 uint64_t reserved_45_47:3;
253 uint64_t reserved_49_63:15;
256 struct cvmx_agl_gmx_drv_ctl_cn56xx {
257 #ifdef __BIG_ENDIAN_BITFIELD
258 uint64_t reserved_17_63:47;
260 uint64_t reserved_13_15:3;
262 uint64_t reserved_5_7:3;
266 uint64_t reserved_5_7:3;
268 uint64_t reserved_13_15:3;
270 uint64_t reserved_17_63:47;
275 union cvmx_agl_gmx_inf_mode {
277 struct cvmx_agl_gmx_inf_mode_s {
278 #ifdef __BIG_ENDIAN_BITFIELD
279 uint64_t reserved_2_63:62;
281 uint64_t reserved_0_0:1;
283 uint64_t reserved_0_0:1;
285 uint64_t reserved_2_63:62;
290 union cvmx_agl_gmx_prtx_cfg {
292 struct cvmx_agl_gmx_prtx_cfg_s {
293 #ifdef __BIG_ENDIAN_BITFIELD
294 uint64_t reserved_14_63:50;
297 uint64_t reserved_9_11:3;
298 uint64_t speed_msb:1;
299 uint64_t reserved_7_7:1;
315 uint64_t reserved_7_7:1;
316 uint64_t speed_msb:1;
317 uint64_t reserved_9_11:3;
320 uint64_t reserved_14_63:50;
323 struct cvmx_agl_gmx_prtx_cfg_cn52xx {
324 #ifdef __BIG_ENDIAN_BITFIELD
325 uint64_t reserved_6_63:58;
339 uint64_t reserved_6_63:58;
344 union cvmx_agl_gmx_rxx_adr_cam0 {
346 struct cvmx_agl_gmx_rxx_adr_cam0_s {
347 #ifdef __BIG_ENDIAN_BITFIELD
355 union cvmx_agl_gmx_rxx_adr_cam1 {
357 struct cvmx_agl_gmx_rxx_adr_cam1_s {
358 #ifdef __BIG_ENDIAN_BITFIELD
366 union cvmx_agl_gmx_rxx_adr_cam2 {
368 struct cvmx_agl_gmx_rxx_adr_cam2_s {
369 #ifdef __BIG_ENDIAN_BITFIELD
377 union cvmx_agl_gmx_rxx_adr_cam3 {
379 struct cvmx_agl_gmx_rxx_adr_cam3_s {
380 #ifdef __BIG_ENDIAN_BITFIELD
388 union cvmx_agl_gmx_rxx_adr_cam4 {
390 struct cvmx_agl_gmx_rxx_adr_cam4_s {
391 #ifdef __BIG_ENDIAN_BITFIELD
399 union cvmx_agl_gmx_rxx_adr_cam5 {
401 struct cvmx_agl_gmx_rxx_adr_cam5_s {
402 #ifdef __BIG_ENDIAN_BITFIELD
410 union cvmx_agl_gmx_rxx_adr_cam_en {
412 struct cvmx_agl_gmx_rxx_adr_cam_en_s {
413 #ifdef __BIG_ENDIAN_BITFIELD
414 uint64_t reserved_8_63:56;
418 uint64_t reserved_8_63:56;
423 union cvmx_agl_gmx_rxx_adr_ctl {
425 struct cvmx_agl_gmx_rxx_adr_ctl_s {
426 #ifdef __BIG_ENDIAN_BITFIELD
427 uint64_t reserved_4_63:60;
435 uint64_t reserved_4_63:60;
440 union cvmx_agl_gmx_rxx_decision {
442 struct cvmx_agl_gmx_rxx_decision_s {
443 #ifdef __BIG_ENDIAN_BITFIELD
444 uint64_t reserved_5_63:59;
448 uint64_t reserved_5_63:59;
453 union cvmx_agl_gmx_rxx_frm_chk {
455 struct cvmx_agl_gmx_rxx_frm_chk_s {
456 #ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t reserved_10_63:54;
479 uint64_t reserved_10_63:54;
482 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
483 #ifdef __BIG_ENDIAN_BITFIELD
484 uint64_t reserved_9_63:55;
492 uint64_t reserved_1_1:1;
496 uint64_t reserved_1_1:1;
504 uint64_t reserved_9_63:55;
509 union cvmx_agl_gmx_rxx_frm_ctl {
511 struct cvmx_agl_gmx_rxx_frm_ctl_s {
512 #ifdef __BIG_ENDIAN_BITFIELD
513 uint64_t reserved_13_63:51;
515 uint64_t reserved_11_11:1;
517 uint64_t pre_align:1;
537 uint64_t pre_align:1;
539 uint64_t reserved_11_11:1;
541 uint64_t reserved_13_63:51;
544 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
545 #ifdef __BIG_ENDIAN_BITFIELD
546 uint64_t reserved_10_63:54;
547 uint64_t pre_align:1;
567 uint64_t pre_align:1;
568 uint64_t reserved_10_63:54;
573 union cvmx_agl_gmx_rxx_frm_max {
575 struct cvmx_agl_gmx_rxx_frm_max_s {
576 #ifdef __BIG_ENDIAN_BITFIELD
577 uint64_t reserved_16_63:48;
581 uint64_t reserved_16_63:48;
586 union cvmx_agl_gmx_rxx_frm_min {
588 struct cvmx_agl_gmx_rxx_frm_min_s {
589 #ifdef __BIG_ENDIAN_BITFIELD
590 uint64_t reserved_16_63:48;
594 uint64_t reserved_16_63:48;
599 union cvmx_agl_gmx_rxx_ifg {
601 struct cvmx_agl_gmx_rxx_ifg_s {
602 #ifdef __BIG_ENDIAN_BITFIELD
603 uint64_t reserved_4_63:60;
607 uint64_t reserved_4_63:60;
612 union cvmx_agl_gmx_rxx_int_en {
614 struct cvmx_agl_gmx_rxx_int_en_s {
615 #ifdef __BIG_ENDIAN_BITFIELD
616 uint64_t reserved_20_63:44;
617 uint64_t pause_drp:1;
657 uint64_t pause_drp:1;
658 uint64_t reserved_20_63:44;
661 struct cvmx_agl_gmx_rxx_int_en_cn52xx {
662 #ifdef __BIG_ENDIAN_BITFIELD
663 uint64_t reserved_20_63:44;
664 uint64_t pause_drp:1;
665 uint64_t reserved_16_18:3;
672 uint64_t reserved_9_9:1;
680 uint64_t reserved_1_1:1;
684 uint64_t reserved_1_1:1;
692 uint64_t reserved_9_9:1;
699 uint64_t reserved_16_18:3;
700 uint64_t pause_drp:1;
701 uint64_t reserved_20_63:44;
706 union cvmx_agl_gmx_rxx_int_reg {
708 struct cvmx_agl_gmx_rxx_int_reg_s {
709 #ifdef __BIG_ENDIAN_BITFIELD
710 uint64_t reserved_20_63:44;
711 uint64_t pause_drp:1;
751 uint64_t pause_drp:1;
752 uint64_t reserved_20_63:44;
755 struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
756 #ifdef __BIG_ENDIAN_BITFIELD
757 uint64_t reserved_20_63:44;
758 uint64_t pause_drp:1;
759 uint64_t reserved_16_18:3;
766 uint64_t reserved_9_9:1;
774 uint64_t reserved_1_1:1;
778 uint64_t reserved_1_1:1;
786 uint64_t reserved_9_9:1;
793 uint64_t reserved_16_18:3;
794 uint64_t pause_drp:1;
795 uint64_t reserved_20_63:44;
800 union cvmx_agl_gmx_rxx_jabber {
802 struct cvmx_agl_gmx_rxx_jabber_s {
803 #ifdef __BIG_ENDIAN_BITFIELD
804 uint64_t reserved_16_63:48;
808 uint64_t reserved_16_63:48;
813 union cvmx_agl_gmx_rxx_pause_drop_time {
815 struct cvmx_agl_gmx_rxx_pause_drop_time_s {
816 #ifdef __BIG_ENDIAN_BITFIELD
817 uint64_t reserved_16_63:48;
821 uint64_t reserved_16_63:48;
826 union cvmx_agl_gmx_rxx_rx_inbnd {
828 struct cvmx_agl_gmx_rxx_rx_inbnd_s {
829 #ifdef __BIG_ENDIAN_BITFIELD
830 uint64_t reserved_4_63:60;
838 uint64_t reserved_4_63:60;
843 union cvmx_agl_gmx_rxx_stats_ctl {
845 struct cvmx_agl_gmx_rxx_stats_ctl_s {
846 #ifdef __BIG_ENDIAN_BITFIELD
847 uint64_t reserved_1_63:63;
851 uint64_t reserved_1_63:63;
856 union cvmx_agl_gmx_rxx_stats_octs {
858 struct cvmx_agl_gmx_rxx_stats_octs_s {
859 #ifdef __BIG_ENDIAN_BITFIELD
860 uint64_t reserved_48_63:16;
864 uint64_t reserved_48_63:16;
869 union cvmx_agl_gmx_rxx_stats_octs_ctl {
871 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
872 #ifdef __BIG_ENDIAN_BITFIELD
873 uint64_t reserved_48_63:16;
877 uint64_t reserved_48_63:16;
882 union cvmx_agl_gmx_rxx_stats_octs_dmac {
884 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
885 #ifdef __BIG_ENDIAN_BITFIELD
886 uint64_t reserved_48_63:16;
890 uint64_t reserved_48_63:16;
895 union cvmx_agl_gmx_rxx_stats_octs_drp {
897 struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
898 #ifdef __BIG_ENDIAN_BITFIELD
899 uint64_t reserved_48_63:16;
903 uint64_t reserved_48_63:16;
908 union cvmx_agl_gmx_rxx_stats_pkts {
910 struct cvmx_agl_gmx_rxx_stats_pkts_s {
911 #ifdef __BIG_ENDIAN_BITFIELD
912 uint64_t reserved_32_63:32;
916 uint64_t reserved_32_63:32;
921 union cvmx_agl_gmx_rxx_stats_pkts_bad {
923 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
924 #ifdef __BIG_ENDIAN_BITFIELD
925 uint64_t reserved_32_63:32;
929 uint64_t reserved_32_63:32;
934 union cvmx_agl_gmx_rxx_stats_pkts_ctl {
936 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
937 #ifdef __BIG_ENDIAN_BITFIELD
938 uint64_t reserved_32_63:32;
942 uint64_t reserved_32_63:32;
947 union cvmx_agl_gmx_rxx_stats_pkts_dmac {
949 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
950 #ifdef __BIG_ENDIAN_BITFIELD
951 uint64_t reserved_32_63:32;
955 uint64_t reserved_32_63:32;
960 union cvmx_agl_gmx_rxx_stats_pkts_drp {
962 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
963 #ifdef __BIG_ENDIAN_BITFIELD
964 uint64_t reserved_32_63:32;
968 uint64_t reserved_32_63:32;
973 union cvmx_agl_gmx_rxx_udd_skp {
975 struct cvmx_agl_gmx_rxx_udd_skp_s {
976 #ifdef __BIG_ENDIAN_BITFIELD
977 uint64_t reserved_9_63:55;
979 uint64_t reserved_7_7:1;
983 uint64_t reserved_7_7:1;
985 uint64_t reserved_9_63:55;
990 union cvmx_agl_gmx_rx_bp_dropx {
992 struct cvmx_agl_gmx_rx_bp_dropx_s {
993 #ifdef __BIG_ENDIAN_BITFIELD
994 uint64_t reserved_6_63:58;
998 uint64_t reserved_6_63:58;
1003 union cvmx_agl_gmx_rx_bp_offx {
1005 struct cvmx_agl_gmx_rx_bp_offx_s {
1006 #ifdef __BIG_ENDIAN_BITFIELD
1007 uint64_t reserved_6_63:58;
1011 uint64_t reserved_6_63:58;
1016 union cvmx_agl_gmx_rx_bp_onx {
1018 struct cvmx_agl_gmx_rx_bp_onx_s {
1019 #ifdef __BIG_ENDIAN_BITFIELD
1020 uint64_t reserved_9_63:55;
1024 uint64_t reserved_9_63:55;
1029 union cvmx_agl_gmx_rx_prt_info {
1031 struct cvmx_agl_gmx_rx_prt_info_s {
1032 #ifdef __BIG_ENDIAN_BITFIELD
1033 uint64_t reserved_18_63:46;
1035 uint64_t reserved_2_15:14;
1039 uint64_t reserved_2_15:14;
1041 uint64_t reserved_18_63:46;
1044 struct cvmx_agl_gmx_rx_prt_info_cn56xx {
1045 #ifdef __BIG_ENDIAN_BITFIELD
1046 uint64_t reserved_17_63:47;
1048 uint64_t reserved_1_15:15;
1052 uint64_t reserved_1_15:15;
1054 uint64_t reserved_17_63:47;
1059 union cvmx_agl_gmx_rx_tx_status {
1061 struct cvmx_agl_gmx_rx_tx_status_s {
1062 #ifdef __BIG_ENDIAN_BITFIELD
1063 uint64_t reserved_6_63:58;
1065 uint64_t reserved_2_3:2;
1069 uint64_t reserved_2_3:2;
1071 uint64_t reserved_6_63:58;
1074 struct cvmx_agl_gmx_rx_tx_status_cn56xx {
1075 #ifdef __BIG_ENDIAN_BITFIELD
1076 uint64_t reserved_5_63:59;
1078 uint64_t reserved_1_3:3;
1082 uint64_t reserved_1_3:3;
1084 uint64_t reserved_5_63:59;
1089 union cvmx_agl_gmx_smacx {
1091 struct cvmx_agl_gmx_smacx_s {
1092 #ifdef __BIG_ENDIAN_BITFIELD
1093 uint64_t reserved_48_63:16;
1097 uint64_t reserved_48_63:16;
1102 union cvmx_agl_gmx_stat_bp {
1104 struct cvmx_agl_gmx_stat_bp_s {
1105 #ifdef __BIG_ENDIAN_BITFIELD
1106 uint64_t reserved_17_63:47;
1112 uint64_t reserved_17_63:47;
1117 union cvmx_agl_gmx_txx_append {
1119 struct cvmx_agl_gmx_txx_append_s {
1120 #ifdef __BIG_ENDIAN_BITFIELD
1121 uint64_t reserved_4_63:60;
1122 uint64_t force_fcs:1;
1125 uint64_t preamble:1;
1127 uint64_t preamble:1;
1130 uint64_t force_fcs:1;
1131 uint64_t reserved_4_63:60;
1136 union cvmx_agl_gmx_txx_clk {
1138 struct cvmx_agl_gmx_txx_clk_s {
1139 #ifdef __BIG_ENDIAN_BITFIELD
1140 uint64_t reserved_6_63:58;
1144 uint64_t reserved_6_63:58;
1149 union cvmx_agl_gmx_txx_ctl {
1151 struct cvmx_agl_gmx_txx_ctl_s {
1152 #ifdef __BIG_ENDIAN_BITFIELD
1153 uint64_t reserved_2_63:62;
1154 uint64_t xsdef_en:1;
1155 uint64_t xscol_en:1;
1157 uint64_t xscol_en:1;
1158 uint64_t xsdef_en:1;
1159 uint64_t reserved_2_63:62;
1164 union cvmx_agl_gmx_txx_min_pkt {
1166 struct cvmx_agl_gmx_txx_min_pkt_s {
1167 #ifdef __BIG_ENDIAN_BITFIELD
1168 uint64_t reserved_8_63:56;
1169 uint64_t min_size:8;
1171 uint64_t min_size:8;
1172 uint64_t reserved_8_63:56;
1177 union cvmx_agl_gmx_txx_pause_pkt_interval {
1179 struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
1180 #ifdef __BIG_ENDIAN_BITFIELD
1181 uint64_t reserved_16_63:48;
1182 uint64_t interval:16;
1184 uint64_t interval:16;
1185 uint64_t reserved_16_63:48;
1190 union cvmx_agl_gmx_txx_pause_pkt_time {
1192 struct cvmx_agl_gmx_txx_pause_pkt_time_s {
1193 #ifdef __BIG_ENDIAN_BITFIELD
1194 uint64_t reserved_16_63:48;
1198 uint64_t reserved_16_63:48;
1203 union cvmx_agl_gmx_txx_pause_togo {
1205 struct cvmx_agl_gmx_txx_pause_togo_s {
1206 #ifdef __BIG_ENDIAN_BITFIELD
1207 uint64_t reserved_16_63:48;
1211 uint64_t reserved_16_63:48;
1216 union cvmx_agl_gmx_txx_pause_zero {
1218 struct cvmx_agl_gmx_txx_pause_zero_s {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220 uint64_t reserved_1_63:63;
1224 uint64_t reserved_1_63:63;
1229 union cvmx_agl_gmx_txx_soft_pause {
1231 struct cvmx_agl_gmx_txx_soft_pause_s {
1232 #ifdef __BIG_ENDIAN_BITFIELD
1233 uint64_t reserved_16_63:48;
1237 uint64_t reserved_16_63:48;
1242 union cvmx_agl_gmx_txx_stat0 {
1244 struct cvmx_agl_gmx_txx_stat0_s {
1245 #ifdef __BIG_ENDIAN_BITFIELD
1255 union cvmx_agl_gmx_txx_stat1 {
1257 struct cvmx_agl_gmx_txx_stat1_s {
1258 #ifdef __BIG_ENDIAN_BITFIELD
1268 union cvmx_agl_gmx_txx_stat2 {
1270 struct cvmx_agl_gmx_txx_stat2_s {
1271 #ifdef __BIG_ENDIAN_BITFIELD
1272 uint64_t reserved_48_63:16;
1276 uint64_t reserved_48_63:16;
1281 union cvmx_agl_gmx_txx_stat3 {
1283 struct cvmx_agl_gmx_txx_stat3_s {
1284 #ifdef __BIG_ENDIAN_BITFIELD
1285 uint64_t reserved_32_63:32;
1289 uint64_t reserved_32_63:32;
1294 union cvmx_agl_gmx_txx_stat4 {
1296 struct cvmx_agl_gmx_txx_stat4_s {
1297 #ifdef __BIG_ENDIAN_BITFIELD
1307 union cvmx_agl_gmx_txx_stat5 {
1309 struct cvmx_agl_gmx_txx_stat5_s {
1310 #ifdef __BIG_ENDIAN_BITFIELD
1320 union cvmx_agl_gmx_txx_stat6 {
1322 struct cvmx_agl_gmx_txx_stat6_s {
1323 #ifdef __BIG_ENDIAN_BITFIELD
1333 union cvmx_agl_gmx_txx_stat7 {
1335 struct cvmx_agl_gmx_txx_stat7_s {
1336 #ifdef __BIG_ENDIAN_BITFIELD
1346 union cvmx_agl_gmx_txx_stat8 {
1348 struct cvmx_agl_gmx_txx_stat8_s {
1349 #ifdef __BIG_ENDIAN_BITFIELD
1359 union cvmx_agl_gmx_txx_stat9 {
1361 struct cvmx_agl_gmx_txx_stat9_s {
1362 #ifdef __BIG_ENDIAN_BITFIELD
1372 union cvmx_agl_gmx_txx_stats_ctl {
1374 struct cvmx_agl_gmx_txx_stats_ctl_s {
1375 #ifdef __BIG_ENDIAN_BITFIELD
1376 uint64_t reserved_1_63:63;
1380 uint64_t reserved_1_63:63;
1385 union cvmx_agl_gmx_txx_thresh {
1387 struct cvmx_agl_gmx_txx_thresh_s {
1388 #ifdef __BIG_ENDIAN_BITFIELD
1389 uint64_t reserved_6_63:58;
1393 uint64_t reserved_6_63:58;
1398 union cvmx_agl_gmx_tx_bp {
1400 struct cvmx_agl_gmx_tx_bp_s {
1401 #ifdef __BIG_ENDIAN_BITFIELD
1402 uint64_t reserved_2_63:62;
1406 uint64_t reserved_2_63:62;
1409 struct cvmx_agl_gmx_tx_bp_cn56xx {
1410 #ifdef __BIG_ENDIAN_BITFIELD
1411 uint64_t reserved_1_63:63;
1415 uint64_t reserved_1_63:63;
1420 union cvmx_agl_gmx_tx_col_attempt {
1422 struct cvmx_agl_gmx_tx_col_attempt_s {
1423 #ifdef __BIG_ENDIAN_BITFIELD
1424 uint64_t reserved_5_63:59;
1428 uint64_t reserved_5_63:59;
1433 union cvmx_agl_gmx_tx_ifg {
1435 struct cvmx_agl_gmx_tx_ifg_s {
1436 #ifdef __BIG_ENDIAN_BITFIELD
1437 uint64_t reserved_8_63:56;
1443 uint64_t reserved_8_63:56;
1448 union cvmx_agl_gmx_tx_int_en {
1450 struct cvmx_agl_gmx_tx_int_en_s {
1451 #ifdef __BIG_ENDIAN_BITFIELD
1452 uint64_t reserved_22_63:42;
1453 uint64_t ptp_lost:2;
1454 uint64_t reserved_18_19:2;
1455 uint64_t late_col:2;
1456 uint64_t reserved_14_15:2;
1458 uint64_t reserved_10_11:2;
1460 uint64_t reserved_4_7:4;
1462 uint64_t reserved_1_1:1;
1466 uint64_t reserved_1_1:1;
1468 uint64_t reserved_4_7:4;
1470 uint64_t reserved_10_11:2;
1472 uint64_t reserved_14_15:2;
1473 uint64_t late_col:2;
1474 uint64_t reserved_18_19:2;
1475 uint64_t ptp_lost:2;
1476 uint64_t reserved_22_63:42;
1479 struct cvmx_agl_gmx_tx_int_en_cn52xx {
1480 #ifdef __BIG_ENDIAN_BITFIELD
1481 uint64_t reserved_18_63:46;
1482 uint64_t late_col:2;
1483 uint64_t reserved_14_15:2;
1485 uint64_t reserved_10_11:2;
1487 uint64_t reserved_4_7:4;
1489 uint64_t reserved_1_1:1;
1493 uint64_t reserved_1_1:1;
1495 uint64_t reserved_4_7:4;
1497 uint64_t reserved_10_11:2;
1499 uint64_t reserved_14_15:2;
1500 uint64_t late_col:2;
1501 uint64_t reserved_18_63:46;
1504 struct cvmx_agl_gmx_tx_int_en_cn56xx {
1505 #ifdef __BIG_ENDIAN_BITFIELD
1506 uint64_t reserved_17_63:47;
1507 uint64_t late_col:1;
1508 uint64_t reserved_13_15:3;
1510 uint64_t reserved_9_11:3;
1512 uint64_t reserved_3_7:5;
1514 uint64_t reserved_1_1:1;
1518 uint64_t reserved_1_1:1;
1520 uint64_t reserved_3_7:5;
1522 uint64_t reserved_9_11:3;
1524 uint64_t reserved_13_15:3;
1525 uint64_t late_col:1;
1526 uint64_t reserved_17_63:47;
1531 union cvmx_agl_gmx_tx_int_reg {
1533 struct cvmx_agl_gmx_tx_int_reg_s {
1534 #ifdef __BIG_ENDIAN_BITFIELD
1535 uint64_t reserved_22_63:42;
1536 uint64_t ptp_lost:2;
1537 uint64_t reserved_18_19:2;
1538 uint64_t late_col:2;
1539 uint64_t reserved_14_15:2;
1541 uint64_t reserved_10_11:2;
1543 uint64_t reserved_4_7:4;
1545 uint64_t reserved_1_1:1;
1549 uint64_t reserved_1_1:1;
1551 uint64_t reserved_4_7:4;
1553 uint64_t reserved_10_11:2;
1555 uint64_t reserved_14_15:2;
1556 uint64_t late_col:2;
1557 uint64_t reserved_18_19:2;
1558 uint64_t ptp_lost:2;
1559 uint64_t reserved_22_63:42;
1562 struct cvmx_agl_gmx_tx_int_reg_cn52xx {
1563 #ifdef __BIG_ENDIAN_BITFIELD
1564 uint64_t reserved_18_63:46;
1565 uint64_t late_col:2;
1566 uint64_t reserved_14_15:2;
1568 uint64_t reserved_10_11:2;
1570 uint64_t reserved_4_7:4;
1572 uint64_t reserved_1_1:1;
1576 uint64_t reserved_1_1:1;
1578 uint64_t reserved_4_7:4;
1580 uint64_t reserved_10_11:2;
1582 uint64_t reserved_14_15:2;
1583 uint64_t late_col:2;
1584 uint64_t reserved_18_63:46;
1587 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1588 #ifdef __BIG_ENDIAN_BITFIELD
1589 uint64_t reserved_17_63:47;
1590 uint64_t late_col:1;
1591 uint64_t reserved_13_15:3;
1593 uint64_t reserved_9_11:3;
1595 uint64_t reserved_3_7:5;
1597 uint64_t reserved_1_1:1;
1601 uint64_t reserved_1_1:1;
1603 uint64_t reserved_3_7:5;
1605 uint64_t reserved_9_11:3;
1607 uint64_t reserved_13_15:3;
1608 uint64_t late_col:1;
1609 uint64_t reserved_17_63:47;
1614 union cvmx_agl_gmx_tx_jam {
1616 struct cvmx_agl_gmx_tx_jam_s {
1617 #ifdef __BIG_ENDIAN_BITFIELD
1618 uint64_t reserved_8_63:56;
1622 uint64_t reserved_8_63:56;
1627 union cvmx_agl_gmx_tx_lfsr {
1629 struct cvmx_agl_gmx_tx_lfsr_s {
1630 #ifdef __BIG_ENDIAN_BITFIELD
1631 uint64_t reserved_16_63:48;
1635 uint64_t reserved_16_63:48;
1640 union cvmx_agl_gmx_tx_ovr_bp {
1642 struct cvmx_agl_gmx_tx_ovr_bp_s {
1643 #ifdef __BIG_ENDIAN_BITFIELD
1644 uint64_t reserved_10_63:54;
1646 uint64_t reserved_6_7:2;
1648 uint64_t reserved_2_3:2;
1649 uint64_t ign_full:2;
1651 uint64_t ign_full:2;
1652 uint64_t reserved_2_3:2;
1654 uint64_t reserved_6_7:2;
1656 uint64_t reserved_10_63:54;
1659 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661 uint64_t reserved_9_63:55;
1663 uint64_t reserved_5_7:3;
1665 uint64_t reserved_1_3:3;
1666 uint64_t ign_full:1;
1668 uint64_t ign_full:1;
1669 uint64_t reserved_1_3:3;
1671 uint64_t reserved_5_7:3;
1673 uint64_t reserved_9_63:55;
1678 union cvmx_agl_gmx_tx_pause_pkt_dmac {
1680 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1681 #ifdef __BIG_ENDIAN_BITFIELD
1682 uint64_t reserved_48_63:16;
1686 uint64_t reserved_48_63:16;
1691 union cvmx_agl_gmx_tx_pause_pkt_type {
1693 struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1694 #ifdef __BIG_ENDIAN_BITFIELD
1695 uint64_t reserved_16_63:48;
1699 uint64_t reserved_16_63:48;
1704 union cvmx_agl_prtx_ctl {
1706 struct cvmx_agl_prtx_ctl_s {
1707 #ifdef __BIG_ENDIAN_BITFIELD
1709 uint64_t reserved_62_62:1;
1710 uint64_t cmp_pctl:6;
1711 uint64_t reserved_54_55:2;
1712 uint64_t cmp_nctl:6;
1713 uint64_t reserved_46_47:2;
1714 uint64_t drv_pctl:6;
1715 uint64_t reserved_38_39:2;
1716 uint64_t drv_nctl:6;
1717 uint64_t reserved_29_31:3;
1719 uint64_t clkrx_byp:1;
1720 uint64_t reserved_21_22:2;
1721 uint64_t clkrx_set:5;
1722 uint64_t clktx_byp:1;
1723 uint64_t reserved_13_14:2;
1724 uint64_t clktx_set:5;
1725 uint64_t reserved_5_7:3;
1737 uint64_t reserved_5_7:3;
1738 uint64_t clktx_set:5;
1739 uint64_t reserved_13_14:2;
1740 uint64_t clktx_byp:1;
1741 uint64_t clkrx_set:5;
1742 uint64_t reserved_21_22:2;
1743 uint64_t clkrx_byp:1;
1745 uint64_t reserved_29_31:3;
1746 uint64_t drv_nctl:6;
1747 uint64_t reserved_38_39:2;
1748 uint64_t drv_pctl:6;
1749 uint64_t reserved_46_47:2;
1750 uint64_t cmp_nctl:6;
1751 uint64_t reserved_54_55:2;
1752 uint64_t cmp_pctl:6;
1753 uint64_t reserved_62_62:1;