2 * Switch a MMU context.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 #ifndef _ASM_MMU_CONTEXT_H
12 #define _ASM_MMU_CONTEXT_H
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/mm_types.h>
17 #include <linux/smp.h>
18 #include <linux/slab.h>
20 #include <asm/cacheflush.h>
21 #include <asm/dsemul.h>
22 #include <asm/hazards.h>
23 #include <asm/tlbflush.h>
24 #include <asm-generic/mm_hooks.h>
26 #define htw_set_pwbase(pgd) \
29 write_c0_pwbase(pgd); \
30 back_to_back_c0_hazard(); \
34 extern void tlbmiss_handler_setup_pgd(unsigned long);
35 extern char tlbmiss_handler_setup_pgd_end[];
37 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
38 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
40 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
41 htw_set_pwbase((unsigned long)pgd); \
44 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
46 #define TLBMISS_HANDLER_RESTORE() \
47 write_c0_xcontext((unsigned long) smp_processor_id() << \
50 #define TLBMISS_HANDLER_SETUP() \
52 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
53 TLBMISS_HANDLER_RESTORE(); \
56 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
59 * For the fast tlb miss handlers, we keep a per cpu array of pointers
60 * to the current pgd for each processor. Also, the proc. id is stuffed
61 * into the context register.
63 extern unsigned long pgd_current[];
65 #define TLBMISS_HANDLER_RESTORE() \
66 write_c0_context((unsigned long) smp_processor_id() << \
69 #define TLBMISS_HANDLER_SETUP() \
70 TLBMISS_HANDLER_RESTORE(); \
71 back_to_back_c0_hazard(); \
72 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
73 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
76 * All unused by hardware upper bits will be considered
77 * as a software asid extension.
79 static inline u64 asid_version_mask(unsigned int cpu)
81 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
83 return ~(u64)(asid_mask | (asid_mask - 1));
86 static inline u64 asid_first_version(unsigned int cpu)
88 return ~asid_version_mask(cpu) + 1;
91 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
92 #define asid_cache(cpu) (cpu_data[cpu].asid_cache)
93 #define cpu_asid(cpu, mm) \
94 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
96 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
101 /* Normal, classic MIPS get_new_mmu_context */
103 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
105 u64 asid = asid_cache(cpu);
107 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {
108 if (cpu_has_vtag_icache)
110 local_flush_tlb_all(); /* start new asid cycle */
113 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
117 * Initialize the context related info for a new mm_struct
121 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
125 for_each_possible_cpu(i)
126 cpu_context(i, mm) = 0;
128 mm->context.bd_emupage_allocmap = NULL;
129 spin_lock_init(&mm->context.bd_emupage_lock);
130 init_waitqueue_head(&mm->context.bd_emupage_queue);
135 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
136 struct task_struct *tsk)
138 unsigned int cpu = smp_processor_id();
140 local_irq_save(flags);
143 /* Check if our ASID is of an older version and thus invalid */
144 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu))
145 get_new_mmu_context(next, cpu);
146 write_c0_entryhi(cpu_asid(cpu, next));
147 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
150 * Mark current->active_mm as not "active" anymore.
151 * We don't want to mislead possible IPI tlb flush routines.
153 cpumask_clear_cpu(cpu, mm_cpumask(prev));
154 cpumask_set_cpu(cpu, mm_cpumask(next));
157 local_irq_restore(flags);
161 * Destroy context related info for an mm_struct that is about
164 static inline void destroy_context(struct mm_struct *mm)
166 dsemul_mm_cleanup(mm);
169 #define deactivate_mm(tsk, mm) do { } while (0)
172 * After we have set current->mm to a new value, this activates
173 * the context for the new mm so we see the new mappings.
176 activate_mm(struct mm_struct *prev, struct mm_struct *next)
179 unsigned int cpu = smp_processor_id();
181 local_irq_save(flags);
184 /* Unconditionally get a new ASID. */
185 get_new_mmu_context(next, cpu);
187 write_c0_entryhi(cpu_asid(cpu, next));
188 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
190 /* mark mmu ownership change */
191 cpumask_clear_cpu(cpu, mm_cpumask(prev));
192 cpumask_set_cpu(cpu, mm_cpumask(next));
195 local_irq_restore(flags);
199 * If mm is currently active_mm, we can't really drop it. Instead,
200 * we will get a new one for it.
203 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
207 local_irq_save(flags);
210 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
211 get_new_mmu_context(mm, cpu);
212 write_c0_entryhi(cpu_asid(cpu, mm));
214 /* will get a new context next time */
215 cpu_context(cpu, mm) = 0;
218 local_irq_restore(flags);
221 #endif /* _ASM_MMU_CONTEXT_H */