2 * Switch a MMU context.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 #ifndef _ASM_MMU_CONTEXT_H
12 #define _ASM_MMU_CONTEXT_H
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/mm_types.h>
17 #include <linux/smp.h>
18 #include <linux/slab.h>
20 #include <asm/cacheflush.h>
21 #include <asm/dsemul.h>
22 #include <asm/hazards.h>
23 #include <asm/tlbflush.h>
24 #include <asm-generic/mm_hooks.h>
26 #define htw_set_pwbase(pgd) \
29 write_c0_pwbase(pgd); \
30 back_to_back_c0_hazard(); \
34 extern void tlbmiss_handler_setup_pgd(unsigned long);
36 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
37 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
39 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
40 htw_set_pwbase((unsigned long)pgd); \
43 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
45 #define TLBMISS_HANDLER_RESTORE() \
46 write_c0_xcontext((unsigned long) smp_processor_id() << \
49 #define TLBMISS_HANDLER_SETUP() \
51 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
52 TLBMISS_HANDLER_RESTORE(); \
55 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
58 * For the fast tlb miss handlers, we keep a per cpu array of pointers
59 * to the current pgd for each processor. Also, the proc. id is stuffed
60 * into the context register.
62 extern unsigned long pgd_current[];
64 #define TLBMISS_HANDLER_RESTORE() \
65 write_c0_context((unsigned long) smp_processor_id() << \
68 #define TLBMISS_HANDLER_SETUP() \
69 TLBMISS_HANDLER_RESTORE(); \
70 back_to_back_c0_hazard(); \
71 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
72 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
75 * All unused by hardware upper bits will be considered
76 * as a software asid extension.
78 static inline u64 asid_version_mask(unsigned int cpu)
80 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
82 return ~(u64)(asid_mask | (asid_mask - 1));
85 static inline u64 asid_first_version(unsigned int cpu)
87 return ~asid_version_mask(cpu) + 1;
90 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
91 #define asid_cache(cpu) (cpu_data[cpu].asid_cache)
92 #define cpu_asid(cpu, mm) \
93 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
95 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
100 /* Normal, classic MIPS get_new_mmu_context */
102 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
104 u64 asid = asid_cache(cpu);
106 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {
107 if (cpu_has_vtag_icache)
109 local_flush_tlb_all(); /* start new asid cycle */
112 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
116 * Initialize the context related info for a new mm_struct
120 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
124 for_each_possible_cpu(i)
125 cpu_context(i, mm) = 0;
127 atomic_set(&mm->context.fp_mode_switching, 0);
129 mm->context.bd_emupage_allocmap = NULL;
130 spin_lock_init(&mm->context.bd_emupage_lock);
131 init_waitqueue_head(&mm->context.bd_emupage_queue);
136 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
137 struct task_struct *tsk)
139 unsigned int cpu = smp_processor_id();
141 local_irq_save(flags);
144 /* Check if our ASID is of an older version and thus invalid */
145 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu))
146 get_new_mmu_context(next, cpu);
147 write_c0_entryhi(cpu_asid(cpu, next));
148 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
151 * Mark current->active_mm as not "active" anymore.
152 * We don't want to mislead possible IPI tlb flush routines.
154 cpumask_clear_cpu(cpu, mm_cpumask(prev));
155 cpumask_set_cpu(cpu, mm_cpumask(next));
158 local_irq_restore(flags);
162 * Destroy context related info for an mm_struct that is about
165 static inline void destroy_context(struct mm_struct *mm)
167 dsemul_mm_cleanup(mm);
170 #define deactivate_mm(tsk, mm) do { } while (0)
173 * After we have set current->mm to a new value, this activates
174 * the context for the new mm so we see the new mappings.
177 activate_mm(struct mm_struct *prev, struct mm_struct *next)
180 unsigned int cpu = smp_processor_id();
182 local_irq_save(flags);
185 /* Unconditionally get a new ASID. */
186 get_new_mmu_context(next, cpu);
188 write_c0_entryhi(cpu_asid(cpu, next));
189 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
191 /* mark mmu ownership change */
192 cpumask_clear_cpu(cpu, mm_cpumask(prev));
193 cpumask_set_cpu(cpu, mm_cpumask(next));
196 local_irq_restore(flags);
200 * If mm is currently active_mm, we can't really drop it. Instead,
201 * we will get a new one for it.
204 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
208 local_irq_save(flags);
211 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
212 get_new_mmu_context(mm, cpu);
213 write_c0_entryhi(cpu_asid(cpu, mm));
215 /* will get a new context next time */
216 cpu_context(cpu, mm) = 0;
219 local_irq_restore(flags);
222 #endif /* _ASM_MMU_CONTEXT_H */